/* * The p*d_populate functions call virt_to_phys implicitly so they can't be used * directly on kernel symbols (bm_p*d). All the early functions are called too * early to use lm_alias so __p*d_populate functions must be used to populate * with the physical address from __pa_symbol.
*/
/* * Return whether 'addr' is aligned to the size covered by a root level * descriptor.
*/ staticbool __init root_level_aligned(u64 addr)
{ int shift = (ARM64_HW_PGTABLE_LEVELS(vabits_actual) - 1) * PTDESC_TABLE_SHIFT;
return (addr % (PAGE_SIZE << shift)) == 0;
}
/* The early shadow maps everything to a single page of zeroes */
asmlinkage void __init kasan_early_init(void)
{
BUILD_BUG_ON(KASAN_SHADOW_OFFSET !=
KASAN_SHADOW_END - (1UL << (64 - KASAN_SHADOW_SCALE_SHIFT)));
BUILD_BUG_ON(!IS_ALIGNED(_KASAN_SHADOW_START(VA_BITS), SHADOW_ALIGN));
BUILD_BUG_ON(!IS_ALIGNED(_KASAN_SHADOW_START(VA_BITS_MIN), SHADOW_ALIGN));
BUILD_BUG_ON(!IS_ALIGNED(KASAN_SHADOW_END, SHADOW_ALIGN));
if (!root_level_aligned(KASAN_SHADOW_START)) { /* * The start address is misaligned, and so the next level table * will be shared with the linear region. This can happen with * 4 or 5 level paging, so install a generic pte_t[] as the * next level. This prevents the kasan_pgd_populate call below * from inserting an entry that refers to the shared KASAN zero * shadow pud_t[]/p4d_t[], which could end up getting corrupted * when the linear region is mapped.
*/ static pte_t tbl[PTRS_PER_PTE] __page_aligned_bss;
pgd_t *pgdp = pgd_offset_k(KASAN_SHADOW_START);
/* Set up full kasan mappings, ensuring that the mapped pages are zeroed */ staticvoid __init kasan_map_populate(unsignedlong start, unsignedlong end, int node)
{
kasan_pgd_populate(start & PAGE_MASK, PAGE_ALIGN(end), node, false);
}
/* * Return the descriptor index of 'addr' in the root level table
*/ staticint __init root_level_idx(u64 addr)
{ /* * On 64k pages, the TTBR1 range root tables are extended for 52-bit * virtual addressing, and TTBR1 will simply point to the pgd_t entry * that covers the start of the 48-bit addressable VA space if LVA is * not implemented. This means we need to index the table as usual, * instead of masking off bits based on vabits_actual.
*/
u64 vabits = IS_ENABLED(CONFIG_ARM64_64K_PAGES) ? VA_BITS
: vabits_actual; int shift = (ARM64_HW_PGTABLE_LEVELS(vabits) - 1) * PTDESC_TABLE_SHIFT;
/* * Return the descriptor index of 'addr' in the next level table
*/ staticint __init next_level_idx(u64 addr)
{ int shift = (ARM64_HW_PGTABLE_LEVELS(vabits_actual) - 2) * PTDESC_TABLE_SHIFT;
/* * Dereference the table descriptor at 'pgd_idx' and clear the entries from * 'start' to 'end' (exclusive) from the table.
*/ staticvoid __init clear_next_level(int pgd_idx, int start, int end)
{
pgd_t pgd = READ_ONCE(swapper_pg_dir[pgd_idx]);
pud_t *pudp = (pud_t *)__phys_to_kimg(__pgd_to_phys(pgd));
/* * We are going to perform proper setup of shadow memory. * At first we should unmap early shadow (clear_pgds() call below). * However, instrumented code couldn't execute without shadow memory. * tmp_pg_dir used to keep early shadow mapped until full shadow * setup will be finished.
*/
memcpy(tmp_pg_dir, swapper_pg_dir, sizeof(tmp_pg_dir));
/* * If the start or end address of the shadow region is not aligned to * the root level size, we have to allocate a temporary next-level table * in each case, clone the next level of descriptors, and install the * table into tmp_pg_dir. Note that with 5 levels of paging, the next * level will in fact be p4d_t, but that makes no difference in this * case.
*/ if (!root_level_aligned(KASAN_SHADOW_START))
clone_next_level(KASAN_SHADOW_START, tmp_pg_dir, pud[0]); if (!root_level_aligned(KASAN_SHADOW_END))
clone_next_level(KASAN_SHADOW_END, tmp_pg_dir, pud[1]);
dsb(ishst);
cpu_replace_ttbr1(lm_alias(tmp_pg_dir));
/* * KAsan may reuse the contents of kasan_early_shadow_pte directly, * so we should make sure that it maps the zero page read-only.
*/ for (i = 0; i < PTRS_PER_PTE; i++)
__set_pte(&kasan_early_shadow_pte[i],
pfn_pte(sym_to_pfn(kasan_early_shadow_page),
PAGE_KERNEL_RO));
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