int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
{ return 1;
}
/* * Common checks before entering the guest world. Call with interrupts * enabled. * * returns: * * == 1 if we're ready to go into guest state * <= 0 if we need to go back to the host with return value
*/ int kvmppc_prepare_to_enter(struct kvm_vcpu *vcpu)
{ int r;
WARN_ON(irqs_disabled());
hard_irq_disable();
while (true) { if (need_resched()) {
local_irq_enable();
cond_resched();
hard_irq_disable(); continue;
}
if (signal_pending(current)) {
kvmppc_account_exit(vcpu, SIGNAL_EXITS);
vcpu->run->exit_reason = KVM_EXIT_INTR;
r = -EINTR; break;
}
vcpu->mode = IN_GUEST_MODE;
/* * Reading vcpu->requests must happen after setting vcpu->mode, * so we don't miss a request because the requester sees * OUTSIDE_GUEST_MODE and assumes we'll be checking requests * before next entering the guest (and thus doesn't IPI). * This also orders the write to mode from any reads * to the page tables done while the VCPU is running. * Please see the comment in kvm_flush_remote_tlbs.
*/
smp_mb();
if (kvm_request_pending(vcpu)) { /* Make sure we process requests preemptable */
local_irq_enable();
trace_kvm_check_requests(vcpu);
r = kvmppc_core_check_requests(vcpu);
hard_irq_disable(); if (r > 0) continue; break;
}
if (kvmppc_core_prepare_to_enter(vcpu)) { /* interrupts got enabled in between, so we
are back at square 1 */ continue;
}
guest_enter_irqoff(); return 1;
}
/* return to host */
local_irq_enable(); return r;
}
EXPORT_SYMBOL_GPL(kvmppc_prepare_to_enter);
switch (nr) { case KVM_HCALL_TOKEN(KVM_HC_PPC_MAP_MAGIC_PAGE):
{ #ifdefined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE) /* Book3S can be little endian, find it out here */ int shared_big_endian = true; if (vcpu->arch.intr_msr & MSR_LE)
shared_big_endian = false; if (shared_big_endian != vcpu->arch.shared_big_endian)
kvmppc_swab_shared(vcpu);
vcpu->arch.shared_big_endian = shared_big_endian; #endif
if (!(param2 & MAGIC_PAGE_FLAG_NOT_MAPPED_NX)) { /* * Older versions of the Linux magic page code had * a bug where they would map their trampoline code * NX. If that's the case, remove !PR NX capability.
*/
vcpu->arch.disable_kernel_nx = true;
kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
}
#ifdef CONFIG_PPC_64K_PAGES /* * Make sure our 4k magic page is in the same window of a 64k * page within the guest and within the host's page.
*/ if ((vcpu->arch.magic_page_pa & 0xf000) !=
((ulong)vcpu->arch.shared & 0xf000)) { void *old_shared = vcpu->arch.shared;
ulong shared = (ulong)vcpu->arch.shared; void *new_shared;
r = EV_SUCCESS; break;
} case KVM_HCALL_TOKEN(KVM_HC_FEATURES):
r = EV_SUCCESS; #ifdefined(CONFIG_PPC_BOOK3S) || defined(CONFIG_KVM_E500V2)
r2 |= (1 << KVM_FEATURE_MAGIC_PAGE); #endif
/* Second return value is in r4 */ break; case EV_HCALL_TOKEN(EV_IDLE):
r = EV_SUCCESS;
kvm_vcpu_halt(vcpu); break; default:
r = EV_UNIMPLEMENTED; break;
}
kvmppc_set_gpr(vcpu, 4, r2);
return r;
}
EXPORT_SYMBOL_GPL(kvmppc_kvm_pv);
int kvmppc_sanity_check(struct kvm_vcpu *vcpu)
{ int r = false;
/* We have to know what CPU to virtualize */ if (!vcpu->arch.pvr) goto out;
/* PAPR only works with book3s_64 */ if ((vcpu->arch.cpu_type != KVM_CPU_3S_64) && vcpu->arch.papr_enabled) goto out;
/* HV KVM can only do PAPR mode for now */ if (!vcpu->arch.papr_enabled && is_kvmppc_hv_enabled(vcpu->kvm)) goto out;
#ifdef CONFIG_KVM_BOOKE_HV if (!cpu_has_feature(CPU_FTR_EMB_HV)) goto out; #endif
int kvmppc_emulate_mmio(struct kvm_vcpu *vcpu)
{ enum emulation_result er; int r;
er = kvmppc_emulate_loadstore(vcpu); switch (er) { case EMULATE_DONE: /* Future optimization: only reload non-volatiles if they were
* actually modified. */
r = RESUME_GUEST_NV; break; case EMULATE_AGAIN:
r = RESUME_GUEST; break; case EMULATE_DO_MMIO:
vcpu->run->exit_reason = KVM_EXIT_MMIO; /* We must reload nonvolatiles because "update" load/store
* instructions modify register state. */ /* Future optimization: only reload non-volatiles if they were
* actually modified. */
r = RESUME_HOST_NV; break; case EMULATE_FAIL:
{
ppc_inst_t last_inst;
kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
kvm_debug_ratelimited("Guest access to device memory using unsupported instruction (opcode: %#08x)\n",
ppc_inst_val(last_inst));
/* * Injecting a Data Storage here is a bit more * accurate since the instruction that caused the * access could still be a valid one.
*/ if (!IS_ENABLED(CONFIG_BOOKE)) {
ulong dsisr = DSISR_BADACCESS;
if (vcpu->mmio_is_write)
dsisr |= DSISR_ISSTORE;
kvmppc_core_queue_data_storage(vcpu,
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
vcpu->arch.vaddr_accessed, dsisr);
} else { /* * BookE does not send a SIGBUS on a bad * fault, so use a Program interrupt instead * to avoid a fault loop.
*/
kvmppc_core_queue_program(vcpu, 0);
}
r = RESUME_GUEST; break;
} default:
WARN_ON(1);
r = RESUME_GUEST;
}
int kvm_arch_init_vm(struct kvm *kvm, unsignedlong type)
{ struct kvmppc_ops *kvm_ops = NULL; int r;
/* * if we have both HV and PR enabled, default is HV
*/ if (type == 0) { if (kvmppc_hv_ops)
kvm_ops = kvmppc_hv_ops; else
kvm_ops = kvmppc_pr_ops; if (!kvm_ops) goto err_out;
} elseif (type == KVM_VM_PPC_HV) { if (!kvmppc_hv_ops) goto err_out;
kvm_ops = kvmppc_hv_ops;
} elseif (type == KVM_VM_PPC_PR) { if (!kvmppc_pr_ops) goto err_out;
kvm_ops = kvmppc_pr_ops;
} else goto err_out;
if (!try_module_get(kvm_ops->owner)) return -ENOENT;
kvm->arch.kvm_ops = kvm_ops;
r = kvmppc_core_init_vm(kvm); if (r)
module_put(kvm_ops->owner); return r;
err_out: return -EINVAL;
}
void kvm_arch_destroy_vm(struct kvm *kvm)
{ #ifdef CONFIG_KVM_XICS /* * We call kick_all_cpus_sync() to ensure that all * CPUs have executed any pending IPIs before we * continue and free VCPUs structures below.
*/ if (is_kvmppc_hv_enabled(kvm))
kick_all_cpus_sync(); #endif
kvm_destroy_vcpus(kvm);
mutex_lock(&kvm->lock);
kvmppc_core_destroy_vm(kvm);
mutex_unlock(&kvm->lock);
/* drop the module reference */
module_put(kvm->arch.kvm_ops->owner);
}
int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
{ int r; /* Assume we're using HV mode when the HV module is loaded */ int hv_enabled = kvmppc_hv_ops ? 1 : 0;
if (kvm) { /* * Hooray - we know which VM type we're running on. Depend on * that rather than the guess above.
*/
hv_enabled = is_kvmppc_hv_enabled(kvm);
}
switch (ext) { #ifdef CONFIG_BOOKE case KVM_CAP_PPC_BOOKE_SREGS: case KVM_CAP_PPC_BOOKE_WATCHDOG: case KVM_CAP_PPC_EPR: #else case KVM_CAP_PPC_SEGSTATE: case KVM_CAP_PPC_HIOR: case KVM_CAP_PPC_PAPR: #endif case KVM_CAP_PPC_UNSET_IRQ: case KVM_CAP_PPC_IRQ_LEVEL: case KVM_CAP_ENABLE_CAP: case KVM_CAP_ONE_REG: case KVM_CAP_IOEVENTFD: case KVM_CAP_IMMEDIATE_EXIT: case KVM_CAP_SET_GUEST_DEBUG:
r = 1; break; case KVM_CAP_PPC_GUEST_DEBUG_SSTEP: case KVM_CAP_PPC_PAIRED_SINGLES: case KVM_CAP_PPC_OSI: case KVM_CAP_PPC_GET_PVINFO: #ifdefined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC) case KVM_CAP_SW_TLB: #endif /* We support this only for PR */
r = !hv_enabled; break; #ifdef CONFIG_KVM_MPIC case KVM_CAP_IRQ_MPIC:
r = 1; break; #endif
#ifdef CONFIG_PPC_BOOK3S_64 case KVM_CAP_SPAPR_TCE:
fallthrough; case KVM_CAP_SPAPR_TCE_64: case KVM_CAP_SPAPR_TCE_VFIO: case KVM_CAP_PPC_RTAS: case KVM_CAP_PPC_FIXUP_HCALL: case KVM_CAP_PPC_ENABLE_HCALL: #ifdef CONFIG_KVM_XICS case KVM_CAP_IRQ_XICS: #endif case KVM_CAP_PPC_GET_CPU_CHAR:
r = 1; break; #ifdef CONFIG_KVM_XIVE case KVM_CAP_PPC_IRQ_XIVE: /* * We need XIVE to be enabled on the platform (implies * a POWER9 processor) and the PowerNV platform, as * nested is not yet supported.
*/
r = xive_enabled() && !!cpu_has_feature(CPU_FTR_HVMODE) &&
kvmppc_xive_native_supported(); break; #endif
#ifdef CONFIG_HAVE_KVM_IRQCHIP case KVM_CAP_IRQFD_RESAMPLE:
r = !xive_enabled(); break; #endif
case KVM_CAP_PPC_ALLOC_HTAB:
r = hv_enabled; break; #endif/* CONFIG_PPC_BOOK3S_64 */ #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE case KVM_CAP_PPC_SMT:
r = 0; if (kvm) { if (kvm->arch.emul_smt_mode > 1)
r = kvm->arch.emul_smt_mode; else
r = kvm->arch.smt_mode;
} elseif (hv_enabled) { if (cpu_has_feature(CPU_FTR_ARCH_300))
r = 1; else
r = threads_per_subcore;
} break; case KVM_CAP_PPC_SMT_POSSIBLE:
r = 1; if (hv_enabled) { if (!cpu_has_feature(CPU_FTR_ARCH_300))
r = ((threads_per_subcore << 1) - 1); else /* P9 can emulate dbells, so allow any mode */
r = 8 | 4 | 2 | 1;
} break; case KVM_CAP_PPC_HWRNG:
r = kvmppc_hwrng_present(); break; case KVM_CAP_PPC_MMU_RADIX:
r = !!(hv_enabled && radix_enabled()); break; case KVM_CAP_PPC_MMU_HASH_V3:
r = !!(hv_enabled && kvmppc_hv_ops->hash_v3_possible &&
kvmppc_hv_ops->hash_v3_possible()); break; case KVM_CAP_PPC_NESTED_HV:
r = !!(hv_enabled && kvmppc_hv_ops->enable_nested &&
!kvmppc_hv_ops->enable_nested(NULL)); break; #endif case KVM_CAP_SYNC_MMU:
BUILD_BUG_ON(!IS_ENABLED(CONFIG_KVM_GENERIC_MMU_NOTIFIER));
r = 1; break; #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE case KVM_CAP_PPC_HTAB_FD:
r = hv_enabled; break; #endif case KVM_CAP_NR_VCPUS: /* * Recommending a number of CPUs is somewhat arbitrary; we * return the number of present CPUs for -HV (since a host * will have secondary threads "offline"), and for other KVM * implementations just count online CPUs.
*/ if (hv_enabled)
r = min_t(unsignedint, num_present_cpus(), KVM_MAX_VCPUS); else
r = min_t(unsignedint, num_online_cpus(), KVM_MAX_VCPUS); break; case KVM_CAP_MAX_VCPUS:
r = KVM_MAX_VCPUS; break; case KVM_CAP_MAX_VCPU_ID:
r = KVM_MAX_VCPU_IDS; break; #ifdef CONFIG_PPC_BOOK3S_64 case KVM_CAP_PPC_GET_SMMU_INFO:
r = 1; break; case KVM_CAP_SPAPR_MULTITCE:
r = 1; break; case KVM_CAP_SPAPR_RESIZE_HPT:
r = !!hv_enabled; break; #endif #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE case KVM_CAP_PPC_FWNMI:
r = hv_enabled; break; #endif #ifdef CONFIG_PPC_TRANSACTIONAL_MEM case KVM_CAP_PPC_HTM:
r = !!(cur_cpu_spec->cpu_user_features2 & PPC_FEATURE2_HTM) ||
(hv_enabled && cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST)); break; #endif #ifdefined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) case KVM_CAP_PPC_SECURE_GUEST:
r = hv_enabled && kvmppc_hv_ops->enable_svm &&
!kvmppc_hv_ops->enable_svm(NULL); break; case KVM_CAP_PPC_DAWR1:
r = !!(hv_enabled && kvmppc_hv_ops->enable_dawr1 &&
!kvmppc_hv_ops->enable_dawr1(NULL)); break; case KVM_CAP_PPC_RPT_INVALIDATE:
r = 1; break; #endif case KVM_CAP_PPC_AIL_MODE_3:
r = 0; /* * KVM PR, POWER7, and some POWER9s don't support AIL=3 mode. * The POWER9s can support it if the guest runs in hash mode, * but QEMU doesn't necessarily query the capability in time.
*/ if (hv_enabled) { if (kvmhv_on_pseries()) { if (pseries_reloc_on_exception())
r = 1;
} elseif (cpu_has_feature(CPU_FTR_ARCH_207S) &&
!cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG)) {
r = 1;
}
} break; default:
r = 0; break;
} return r;
void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
{ /* Make sure we're not using the vcpu anymore */
hrtimer_cancel(&vcpu->arch.dec_timer);
switch (vcpu->arch.irq_type) { case KVMPPC_IRQ_MPIC:
kvmppc_mpic_disconnect_vcpu(vcpu->arch.mpic, vcpu); break; case KVMPPC_IRQ_XICS: if (xics_on_xive())
kvmppc_xive_cleanup_vcpu(vcpu); else
kvmppc_xics_free_icp(vcpu); break; case KVMPPC_IRQ_XIVE:
kvmppc_xive_native_cleanup_vcpu(vcpu); break;
}
kvmppc_core_vcpu_free(vcpu);
kvmppc_subarch_vcpu_uninit(vcpu);
}
int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
{ return kvmppc_core_pending_dec(vcpu);
}
void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
{ #ifdef CONFIG_BOOKE /* * vrsave (formerly usprg0) isn't used by Linux, but may * be used by the guest. * * On non-booke this is associated with Altivec and * is handled by code in book3s.c.
*/
mtspr(SPRN_VRSAVE, vcpu->arch.vrsave); #endif
kvmppc_core_vcpu_load(vcpu, cpu);
}
/* * irq_bypass_add_producer and irq_bypass_del_producer are only * useful if the architecture supports PCI passthrough. * irq_bypass_stop and irq_bypass_start are not needed and so * kvm_ops are not defined for them.
*/ bool kvm_arch_has_irq_bypass(void)
{ return ((kvmppc_hv_ops && kvmppc_hv_ops->irq_bypass_add_producer) ||
(kvmppc_pr_ops && kvmppc_pr_ops->irq_bypass_add_producer));
}
staticinlinevoid kvmppc_set_vsr_dword(struct kvm_vcpu *vcpu,
u64 gpr)
{ union kvmppc_one_reg val; int offset = kvmppc_get_vsr_dword_offset(vcpu->arch.mmio_vsx_offset); int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK;
if (offset == -1) return;
if (index >= 32) {
kvmppc_get_vsx_vr(vcpu, index - 32, &val.vval);
val.vsxval[offset] = gpr;
kvmppc_set_vsx_vr(vcpu, index - 32, &val.vval);
} else {
kvmppc_set_vsx_fpr(vcpu, index, offset, gpr);
}
}
staticinlinevoid kvmppc_set_vsr_dword_dump(struct kvm_vcpu *vcpu,
u64 gpr)
{ union kvmppc_one_reg val; int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK;
staticinlinevoid kvmppc_set_vsr_word(struct kvm_vcpu *vcpu,
u32 gpr32)
{ union kvmppc_one_reg val; int offset = kvmppc_get_vsr_word_offset(vcpu->arch.mmio_vsx_offset); int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK; int dword_offset, word_offset;
#ifdef CONFIG_ALTIVEC staticinlineint kvmppc_get_vmx_offset_generic(struct kvm_vcpu *vcpu, int index, int element_size)
{ int offset; int elts = sizeof(vector128)/element_size;
if ((index < 0) || (index >= elts)) return -1;
if (kvmppc_need_byteswap(vcpu))
offset = elts - index - 1; else
offset = index;
#ifdef CONFIG_VSX staticinlineint kvmppc_get_vsr_data(struct kvm_vcpu *vcpu, int rs, u64 *val)
{
u32 dword_offset, word_offset; union kvmppc_one_reg reg; int vsx_offset = 0; int copy_type = vcpu->arch.mmio_copy_type; int result = 0;
switch (copy_type) { case KVMPPC_VSX_COPY_DWORD:
vsx_offset =
kvmppc_get_vsr_dword_offset(vcpu->arch.mmio_vsx_offset);
r = -EPERM;
dev = kvm_device_from_filp(fd_file(f)); if (dev) { if (xics_on_xive())
r = kvmppc_xive_connect_vcpu(dev, vcpu, cap->args[1]); else
r = kvmppc_xics_connect_vcpu(dev, vcpu, cap->args[1]);
} break;
} #endif/* CONFIG_KVM_XICS */ #ifdef CONFIG_KVM_XIVE case KVM_CAP_PPC_IRQ_XIVE: { CLASS(fd, f)(cap->args[0]); struct kvm_device *dev;
r = -EBADF; if (fd_empty(f)) break;
r = -ENXIO; if (!xive_enabled()) break;
r = -EPERM;
dev = kvm_device_from_filp(fd_file(f)); if (dev)
r = kvmppc_xive_native_connect_vcpu(dev, vcpu,
cap->args[1]); break;
} #endif/* CONFIG_KVM_XIVE */ #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE case KVM_CAP_PPC_FWNMI:
r = -EINVAL; if (!is_kvmppc_hv_enabled(vcpu->kvm)) break;
r = 0;
vcpu->kvm->arch.fwnmi_enabled = true; break; #endif/* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ default:
r = -EINVAL; break;
}
switch (ioctl) { case KVM_ENABLE_CAP:
{ struct kvm_enable_cap cap;
r = -EFAULT; if (copy_from_user(&cap, argp, sizeof(cap))) goto out;
vcpu_load(vcpu);
r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
vcpu_put(vcpu); break;
}
case KVM_SET_ONE_REG: case KVM_GET_ONE_REG:
{ struct kvm_one_reg reg;
r = -EFAULT; if (copy_from_user(®, argp, sizeof(reg))) goto out; if (ioctl == KVM_SET_ONE_REG)
r = kvm_vcpu_ioctl_set_one_reg(vcpu, ®); else
r = kvm_vcpu_ioctl_get_one_reg(vcpu, ®); break;
}
#ifdefined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC) case KVM_DIRTY_TLB: { struct kvm_dirty_tlb dirty;
r = -EFAULT; if (copy_from_user(&dirty, argp, sizeof(dirty))) goto out;
vcpu_load(vcpu);
r = kvm_vcpu_ioctl_dirty_tlb(vcpu, &dirty);
vcpu_put(vcpu); break;
} #endif default:
r = -EINVAL;
}
r = -EINVAL; if (hcall > MAX_HCALL_OPCODE || (hcall & 3) ||
cap->args[1] > 1) break; if (!kvmppc_book3s_hcall_implemented(kvm, hcall)) break; if (cap->args[1])
set_bit(hcall / 4, kvm->arch.enabled_hcalls); else
clear_bit(hcall / 4, kvm->arch.enabled_hcalls);
r = 0; break;
} case KVM_CAP_PPC_SMT: { unsignedlong mode = cap->args[0]; unsignedlong flags = cap->args[1];
r = -EINVAL; if (kvm->arch.kvm_ops->set_smt_mode)
r = kvm->arch.kvm_ops->set_smt_mode(kvm, mode, flags); break;
}
case KVM_CAP_PPC_NESTED_HV:
r = -EINVAL; if (!is_kvmppc_hv_enabled(kvm) ||
!kvm->arch.kvm_ops->enable_nested) break;
r = kvm->arch.kvm_ops->enable_nested(kvm); break; #endif #ifdefined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) case KVM_CAP_PPC_SECURE_GUEST:
r = -EINVAL; if (!is_kvmppc_hv_enabled(kvm) || !kvm->arch.kvm_ops->enable_svm) break;
r = kvm->arch.kvm_ops->enable_svm(kvm); break; case KVM_CAP_PPC_DAWR1:
r = -EINVAL; if (!is_kvmppc_hv_enabled(kvm) || !kvm->arch.kvm_ops->enable_dawr1) break;
r = kvm->arch.kvm_ops->enable_dawr1(kvm); break; #endif default:
r = -EINVAL; break;
}
return r;
}
#ifdef CONFIG_PPC_BOOK3S_64 /* * These functions check whether the underlying hardware is safe * against attacks based on observing the effects of speculatively * executed instructions, and whether it supplies instructions for * use in workarounds. The information comes from firmware, either * via the device tree on powernv platforms or from an hcall on * pseries platforms.
*/ #ifdef CONFIG_PPC_PSERIES staticint pseries_get_cpu_char(struct kvm_ppc_cpu_char *cp)
{ struct h_cpu_char_result c; unsignedlong rc;
memset(&info, 0, sizeof(info));
r = kvm->arch.kvm_ops->get_smmu_info(kvm, &info); if (r >= 0 && copy_to_user(argp, &info, sizeof(info)))
r = -EFAULT; break;
} case KVM_PPC_RTAS_DEFINE_TOKEN: { struct kvm *kvm = filp->private_data;
r = kvm_vm_ioctl_rtas_define_token(kvm, argp); break;
} case KVM_PPC_CONFIGURE_V3_MMU: { struct kvm *kvm = filp->private_data; struct kvm_ppc_mmuv3_cfg cfg;
r = -EINVAL; if (!kvm->arch.kvm_ops->configure_mmu) goto out;
r = -EFAULT; if (copy_from_user(&cfg, argp, sizeof(cfg))) goto out;
r = kvm->arch.kvm_ops->configure_mmu(kvm, &cfg); break;
} case KVM_PPC_GET_RMMU_INFO: { struct kvm *kvm = filp->private_data; struct kvm_ppc_rmmu_info info;
r = -EINVAL; if (!kvm->arch.kvm_ops->get_rmmu_info) goto out;
r = kvm->arch.kvm_ops->get_rmmu_info(kvm, &info); if (r >= 0 && copy_to_user(argp, &info, sizeof(info)))
r = -EFAULT; break;
} case KVM_PPC_GET_CPU_CHAR: { struct kvm_ppc_cpu_char cpuchar;
r = kvmppc_get_cpu_char(&cpuchar); if (r >= 0 && copy_to_user(argp, &cpuchar, sizeof(cpuchar)))
r = -EFAULT; break;
} case KVM_PPC_SVM_OFF: { struct kvm *kvm = filp->private_data;
/* The host LPID must always be 0 (allocation starts at 1) */
lpid = ida_alloc_range(&lpid_inuse, 1, nr_lpids - 1, GFP_KERNEL); if (lpid < 0) { if (lpid == -ENOMEM)
pr_err("%s: Out of memory\n", __func__); else
pr_err("%s: No LPIDs free\n", __func__); return -ENOMEM;
}
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