Quelle  gaudi2.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0

/*
 * Copyright 2020-2022 HabanaLabs, Ltd.
 * All Rights Reserved.
 */

#include "gaudi2P.h"
#include "gaudi2_masks.h"
#include "../include/gaudi2/gaudi2_special_blocks.h"
#include "../include/hw_ip/mmu/mmu_general.h"
#include "../include/hw_ip/mmu/mmu_v2_0.h"
#include "../include/gaudi2/gaudi2_packets.h"
#include "../include/gaudi2/gaudi2_reg_map.h"
#include "../include/gaudi2/gaudi2_async_ids_map_extended.h"
#include "../include/gaudi2/arc/gaudi2_arc_common_packets.h"

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/hwmon.h>
#include <linux/iommu.h>

#define GAUDI2_DMA_POOL_BLK_SIZE  SZ_256  /* 256 bytes */

#define GAUDI2_RESET_TIMEOUT_MSEC  2000  /* 2000ms */

#define GAUDI2_RESET_POLL_TIMEOUT_USEC  500000  /* 500ms */
#define GAUDI2_PLDM_HRESET_TIMEOUT_MSEC  25000  /* 25s */
#define GAUDI2_PLDM_SRESET_TIMEOUT_MSEC  25000  /* 25s */
#define GAUDI2_PLDM_RESET_POLL_TIMEOUT_USEC 3000000  /* 3s */
#define GAUDI2_RESET_POLL_CNT   3
#define GAUDI2_RESET_WAIT_MSEC   1  /* 1ms */
#define GAUDI2_CPU_RESET_WAIT_MSEC  100  /* 100ms */
#define GAUDI2_PLDM_RESET_WAIT_MSEC  1000  /* 1s */
#define GAUDI2_CB_POOL_CB_CNT   512
#define GAUDI2_CB_POOL_CB_SIZE   SZ_128K  /* 128KB */
#define GAUDI2_MSG_TO_CPU_TIMEOUT_USEC  4000000  /* 4s */
#define GAUDI2_WAIT_FOR_BL_TIMEOUT_USEC  25000000 /* 25s */
#define GAUDI2_TEST_QUEUE_WAIT_USEC  100000  /* 100ms */
#define GAUDI2_PLDM_TEST_QUEUE_WAIT_USEC 1000000  /* 1s */

#define GAUDI2_ALLOC_CPU_MEM_RETRY_CNT  3

/*
 * since the code already has built-in support for binning of up to MAX_FAULTY_TPCS TPCs
 * and the code relies on that value (for array size etc..) we define another value
 * for MAX faulty TPCs which reflects the cluster binning requirements
 */
#define MAX_CLUSTER_BINNING_FAULTY_TPCS  1
#define MAX_FAULTY_XBARS   1
#define MAX_FAULTY_EDMAS   1
#define MAX_FAULTY_DECODERS   1

#define GAUDI2_TPC_FULL_MASK   0x1FFFFFF
#define GAUDI2_HIF_HMMU_FULL_MASK  0xFFFF
#define GAUDI2_DECODER_FULL_MASK  0x3FF

#define GAUDI2_NA_EVENT_CAUSE   0xFF
#define GAUDI2_NUM_OF_QM_ERR_CAUSE  18
#define GAUDI2_NUM_OF_LOWER_QM_ERR_CAUSE 25
#define GAUDI2_NUM_OF_QM_ARB_ERR_CAUSE  3
#define GAUDI2_NUM_OF_ARC_SEI_ERR_CAUSE  14
#define GAUDI2_NUM_OF_CPU_SEI_ERR_CAUSE  3
#define GAUDI2_NUM_OF_QM_SEI_ERR_CAUSE  2
#define GAUDI2_NUM_OF_ROT_ERR_CAUSE  22
#define GAUDI2_NUM_OF_TPC_INTR_CAUSE  31
#define GAUDI2_NUM_OF_DEC_ERR_CAUSE  25
#define GAUDI2_NUM_OF_MME_ERR_CAUSE  16
#define GAUDI2_NUM_OF_MME_WAP_ERR_CAUSE  7
#define GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE 8
#define GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE  19
#define GAUDI2_NUM_OF_HBM_SEI_CAUSE  9
#define GAUDI2_NUM_OF_SM_SEI_ERR_CAUSE  3
#define GAUDI2_NUM_OF_PCIE_ADDR_DEC_ERR_CAUSE 3
#define GAUDI2_NUM_OF_PMMU_FATAL_ERR_CAUSE 2
#define GAUDI2_NUM_OF_HIF_FATAL_ERR_CAUSE 2
#define GAUDI2_NUM_OF_AXI_DRAIN_ERR_CAUSE 2
#define GAUDI2_NUM_OF_HBM_MC_SPI_CAUSE  5

#define GAUDI2_MMU_CACHE_INV_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 10)
#define GAUDI2_PLDM_MMU_TIMEOUT_USEC  (MMU_CONFIG_TIMEOUT_USEC * 200)
#define GAUDI2_ARB_WDT_TIMEOUT   (0x1000000)

#define GAUDI2_VDEC_TIMEOUT_USEC  10000  /* 10ms */
#define GAUDI2_PLDM_VDEC_TIMEOUT_USEC  (GAUDI2_VDEC_TIMEOUT_USEC * 100)

#define KDMA_TIMEOUT_USEC   USEC_PER_SEC

#define IS_DMA_IDLE(dma_core_sts0) \
 (!((dma_core_sts0) & (DCORE0_EDMA0_CORE_STS0_BUSY_MASK)))

#define IS_DMA_HALTED(dma_core_sts1) \
 ((dma_core_sts1) & (DCORE0_EDMA0_CORE_STS1_IS_HALT_MASK))

#define IS_MME_IDLE(mme_arch_sts) (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)

#define IS_TPC_IDLE(tpc_cfg_sts) (((tpc_cfg_sts) & (TPC_IDLE_MASK)) == (TPC_IDLE_MASK))

#define IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) \
 ((((qm_glbl_sts0) & (QM_IDLE_MASK)) == (QM_IDLE_MASK)) && \
 (((qm_glbl_sts1) & (QM_ARC_IDLE_MASK)) == (QM_ARC_IDLE_MASK)) && \
 (((qm_cgm_sts) & (CGM_IDLE_MASK)) == (CGM_IDLE_MASK)))

#define PCIE_DEC_EN_MASK   0x300
#define DEC_WORK_STATE_IDLE   0
#define DEC_WORK_STATE_PEND   3
#define IS_DEC_IDLE(dec_swreg15) \
 (((dec_swreg15) & DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK) == DEC_WORK_STATE_IDLE || \
 ((dec_swreg15) & DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK) ==  DEC_WORK_STATE_PEND)

/* HBM MMU address scrambling parameters */
#define GAUDI2_HBM_MMU_SCRM_MEM_SIZE  SZ_8M
#define GAUDI2_HBM_MMU_SCRM_DIV_SHIFT  26
#define GAUDI2_HBM_MMU_SCRM_MOD_SHIFT  0
#define GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK DRAM_VA_HINT_MASK
#define GAUDI2_COMPENSATE_TLB_PAGE_SIZE_FACTOR 16
#define MMU_RANGE_INV_VA_LSB_SHIFT  12
#define MMU_RANGE_INV_VA_MSB_SHIFT  44
#define MMU_RANGE_INV_EN_SHIFT   0
#define MMU_RANGE_INV_ASID_EN_SHIFT  1
#define MMU_RANGE_INV_ASID_SHIFT  2

/* The last SPI_SEI cause bit, "burst_fifo_full", is expected to be triggered in PMMU because it has
 * a 2 entries FIFO, and hence it is not enabled for it.
 */
#define GAUDI2_PMMU_SPI_SEI_ENABLE_MASK  GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 2, 0)
#define GAUDI2_HMMU_SPI_SEI_ENABLE_MASK  GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 1, 0)

#define GAUDI2_MAX_STRING_LEN   64

#define GAUDI2_VDEC_MSIX_ENTRIES  (GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM - \
       GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM + 1)

#define ENGINE_ID_DCORE_OFFSET (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)

/* RAZWI initiator coordinates */
#define RAZWI_GET_AXUSER_XY(x) \
 ((x & 0xF8001FF0) >> 4)

#define RAZWI_GET_AXUSER_LOW_XY(x) \
 ((x & 0x00001FF0) >> 4)

#define RAZWI_INITIATOR_AXUER_L_X_SHIFT  0
#define RAZWI_INITIATOR_AXUER_L_X_MASK  0x1F
#define RAZWI_INITIATOR_AXUER_L_Y_SHIFT  5
#define RAZWI_INITIATOR_AXUER_L_Y_MASK  0xF

#define RAZWI_INITIATOR_AXUER_H_X_SHIFT  23
#define RAZWI_INITIATOR_AXUER_H_X_MASK  0x1F

#define RAZWI_INITIATOR_ID_X_Y_LOW(x, y) \
 ((((y) & RAZWI_INITIATOR_AXUER_L_Y_MASK) << RAZWI_INITIATOR_AXUER_L_Y_SHIFT) | \
  (((x) & RAZWI_INITIATOR_AXUER_L_X_MASK) << RAZWI_INITIATOR_AXUER_L_X_SHIFT))

#define RAZWI_INITIATOR_ID_X_HIGH(x) \
  (((x) & RAZWI_INITIATOR_AXUER_H_X_MASK) << RAZWI_INITIATOR_AXUER_H_X_SHIFT)

#define RAZWI_INITIATOR_ID_X_Y(xl, yl, xh) \
 (RAZWI_INITIATOR_ID_X_Y_LOW(xl, yl) | RAZWI_INITIATOR_ID_X_HIGH(xh))

#define PSOC_RAZWI_ENG_STR_SIZE   128
#define PSOC_RAZWI_MAX_ENG_PER_RTR  5

/* HW scrambles only bits 0-25 */
#define HW_UNSCRAMBLED_BITS_MASK  GENMASK_ULL(63, 26)

#define GAUDI2_GLBL_ERR_MAX_CAUSE_NUM  17

struct gaudi2_razwi_info {
 u32 axuser_xy;
 u32 rtr_ctrl;
 u16 eng_id;
 char *eng_name;
};

static struct gaudi2_razwi_info common_razwi_info[] = {
  {RAZWI_INITIATOR_ID_X_Y(2, 4, 0), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_DEC_0, "DEC0"},
  {RAZWI_INITIATOR_ID_X_Y(2, 4, 4), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_DEC_1, "DEC1"},
  {RAZWI_INITIATOR_ID_X_Y(17, 4, 18), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_DEC_0, "DEC2"},
  {RAZWI_INITIATOR_ID_X_Y(17, 4, 14), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_DEC_1, "DEC3"},
  {RAZWI_INITIATOR_ID_X_Y(2, 11, 0), mmDCORE2_RTR0_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_DEC_0, "DEC4"},
  {RAZWI_INITIATOR_ID_X_Y(2, 11, 4), mmDCORE2_RTR0_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_DEC_1, "DEC5"},
  {RAZWI_INITIATOR_ID_X_Y(17, 11, 18), mmDCORE3_RTR7_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_DEC_0, "DEC6"},
  {RAZWI_INITIATOR_ID_X_Y(17, 11, 14), mmDCORE3_RTR7_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_DEC_1, "DEC7"},
  {RAZWI_INITIATOR_ID_X_Y(2, 4, 6), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_PCIE_ENGINE_ID_DEC_0, "DEC8"},
  {RAZWI_INITIATOR_ID_X_Y(2, 4, 7), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_PCIE_ENGINE_ID_DEC_0, "DEC9"},
  {RAZWI_INITIATOR_ID_X_Y(3, 4, 2), mmDCORE0_RTR1_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_TPC_0, "TPC0"},
  {RAZWI_INITIATOR_ID_X_Y(3, 4, 4), mmDCORE0_RTR1_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_TPC_1, "TPC1"},
  {RAZWI_INITIATOR_ID_X_Y(4, 4, 2), mmDCORE0_RTR2_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_TPC_2, "TPC2"},
  {RAZWI_INITIATOR_ID_X_Y(4, 4, 4), mmDCORE0_RTR2_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_TPC_3, "TPC3"},
  {RAZWI_INITIATOR_ID_X_Y(5, 4, 2), mmDCORE0_RTR3_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_TPC_4, "TPC4"},
  {RAZWI_INITIATOR_ID_X_Y(5, 4, 4), mmDCORE0_RTR3_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_TPC_5, "TPC5"},
  {RAZWI_INITIATOR_ID_X_Y(16, 4, 14), mmDCORE1_RTR6_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_TPC_0, "TPC6"},
  {RAZWI_INITIATOR_ID_X_Y(16, 4, 16), mmDCORE1_RTR6_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_TPC_1, "TPC7"},
  {RAZWI_INITIATOR_ID_X_Y(15, 4, 14), mmDCORE1_RTR5_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_TPC_2, "TPC8"},
  {RAZWI_INITIATOR_ID_X_Y(15, 4, 16), mmDCORE1_RTR5_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_TPC_3, "TPC9"},
  {RAZWI_INITIATOR_ID_X_Y(14, 4, 14), mmDCORE1_RTR4_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_TPC_4, "TPC10"},
  {RAZWI_INITIATOR_ID_X_Y(14, 4, 16), mmDCORE1_RTR4_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_TPC_5, "TPC11"},
  {RAZWI_INITIATOR_ID_X_Y(5, 11, 2), mmDCORE2_RTR3_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_TPC_0, "TPC12"},
  {RAZWI_INITIATOR_ID_X_Y(5, 11, 4), mmDCORE2_RTR3_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_TPC_1, "TPC13"},
  {RAZWI_INITIATOR_ID_X_Y(4, 11, 2), mmDCORE2_RTR2_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_TPC_2, "TPC14"},
  {RAZWI_INITIATOR_ID_X_Y(4, 11, 4), mmDCORE2_RTR2_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_TPC_3, "TPC15"},
  {RAZWI_INITIATOR_ID_X_Y(3, 11, 2), mmDCORE2_RTR1_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_TPC_4, "TPC16"},
  {RAZWI_INITIATOR_ID_X_Y(3, 11, 4), mmDCORE2_RTR1_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_TPC_5, "TPC17"},
  {RAZWI_INITIATOR_ID_X_Y(14, 11, 14), mmDCORE3_RTR4_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_TPC_0, "TPC18"},
  {RAZWI_INITIATOR_ID_X_Y(14, 11, 16), mmDCORE3_RTR4_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_TPC_1, "TPC19"},
  {RAZWI_INITIATOR_ID_X_Y(15, 11, 14), mmDCORE3_RTR5_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_TPC_2, "TPC20"},
  {RAZWI_INITIATOR_ID_X_Y(15, 11, 16), mmDCORE3_RTR5_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_TPC_3, "TPC21"},
  {RAZWI_INITIATOR_ID_X_Y(16, 11, 14), mmDCORE3_RTR6_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_TPC_4, "TPC22"},
  {RAZWI_INITIATOR_ID_X_Y(16, 11, 16), mmDCORE3_RTR6_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_TPC_5, "TPC23"},
  {RAZWI_INITIATOR_ID_X_Y(2, 4, 2), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_TPC_5, "TPC24"},
  {RAZWI_INITIATOR_ID_X_Y(17, 4, 8), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_NIC0_0, "NIC0"},
  {RAZWI_INITIATOR_ID_X_Y(17, 4, 10), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_NIC0_1, "NIC1"},
  {RAZWI_INITIATOR_ID_X_Y(17, 4, 12), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_NIC1_0, "NIC2"},
  {RAZWI_INITIATOR_ID_X_Y(17, 4, 14), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_NIC1_1, "NIC3"},
  {RAZWI_INITIATOR_ID_X_Y(17, 4, 15), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_NIC2_0, "NIC4"},
  {RAZWI_INITIATOR_ID_X_Y(2, 11, 2), mmDCORE2_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_NIC2_1, "NIC5"},
  {RAZWI_INITIATOR_ID_X_Y(2, 11, 4), mmDCORE2_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_NIC3_0, "NIC6"},
  {RAZWI_INITIATOR_ID_X_Y(2, 11, 6), mmDCORE2_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_NIC3_1, "NIC7"},
  {RAZWI_INITIATOR_ID_X_Y(2, 11, 8), mmDCORE2_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_NIC4_0, "NIC8"},
  {RAZWI_INITIATOR_ID_X_Y(17, 11, 12), mmDCORE3_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_NIC4_1, "NIC9"},
  {RAZWI_INITIATOR_ID_X_Y(17, 11, 14), mmDCORE3_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_NIC5_0, "NIC10"},
  {RAZWI_INITIATOR_ID_X_Y(17, 11, 16), mmDCORE3_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_NIC5_1, "NIC11"},
  {RAZWI_INITIATOR_ID_X_Y(2, 4, 2), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_PDMA_0, "PDMA0"},
  {RAZWI_INITIATOR_ID_X_Y(2, 4, 3), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_PDMA_1, "PDMA1"},
  {RAZWI_INITIATOR_ID_X_Y(2, 4, 4), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "PMMU"},
  {RAZWI_INITIATOR_ID_X_Y(2, 4, 5), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "PCIE"},
  {RAZWI_INITIATOR_ID_X_Y(17, 4, 16), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_ARC_FARM, "ARC_FARM"},
  {RAZWI_INITIATOR_ID_X_Y(17, 4, 17), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_KDMA, "KDMA"},
  {RAZWI_INITIATOR_ID_X_Y(1, 5, 1), mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_EDMA_0, "EDMA0"},
  {RAZWI_INITIATOR_ID_X_Y(1, 5, 1), mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_EDMA_1, "EDMA1"},
  {RAZWI_INITIATOR_ID_X_Y(18, 5, 18), mmSFT1_HBW_RTR_IF1_RTR_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_EDMA_0, "EDMA2"},
  {RAZWI_INITIATOR_ID_X_Y(18, 5, 18), mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_EDMA_1, "EDMA3"},
  {RAZWI_INITIATOR_ID_X_Y(1, 10, 1), mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_EDMA_0, "EDMA4"},
  {RAZWI_INITIATOR_ID_X_Y(1, 10, 1), mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_EDMA_1, "EDMA5"},
  {RAZWI_INITIATOR_ID_X_Y(18, 10, 18), mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_EDMA_0, "EDMA6"},
  {RAZWI_INITIATOR_ID_X_Y(18, 10, 18), mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_EDMA_1, "EDMA7"},
  {RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU0"},
  {RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU1"},
  {RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU2"},
  {RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU3"},
  {RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU4"},
  {RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU5"},
  {RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU6"},
  {RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU7"},
  {RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU8"},
  {RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU9"},
  {RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU10"},
  {RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU11"},
  {RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU12"},
  {RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU13"},
  {RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU14"},
  {RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_SIZE, "HMMU15"},
  {RAZWI_INITIATOR_ID_X_Y(2, 11, 2), mmDCORE2_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_ROT_0, "ROT0"},
  {RAZWI_INITIATOR_ID_X_Y(17, 11, 16), mmDCORE3_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_ROT_1, "ROT1"},
  {RAZWI_INITIATOR_ID_X_Y(2, 11, 2), mmDCORE2_RTR0_CTRL_BASE,
    GAUDI2_ENGINE_ID_PSOC, "CPU"},
  {RAZWI_INITIATOR_ID_X_Y(17, 11, 11), mmDCORE3_RTR7_CTRL_BASE,
    GAUDI2_ENGINE_ID_PSOC, "PSOC"}
};

static struct gaudi2_razwi_info mme_razwi_info[] = {
  /* MME X high coordinate is N/A, hence using only low coordinates */
  {RAZWI_INITIATOR_ID_X_Y_LOW(7, 4), mmDCORE0_RTR5_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_WAP0"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(9, 4), mmDCORE0_RTR7_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_WAP1"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(8, 4), mmDCORE0_RTR6_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_CTRL_WR"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(9, 4), mmDCORE0_RTR7_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_CTRL_RD"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(6, 4), mmDCORE0_RTR4_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE0"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(6, 4), mmDCORE0_RTR4_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE1"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(7, 4), mmDCORE0_RTR5_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE2"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(8, 4), mmDCORE0_RTR6_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE3"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(9, 4), mmDCORE0_RTR7_CTRL_BASE,
    GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE4"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(12, 4), mmDCORE1_RTR2_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_WAP0"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(10, 4), mmDCORE1_RTR0_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_WAP1"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(11, 4), mmDCORE1_RTR1_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_CTRL_WR"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(10, 4), mmDCORE1_RTR0_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_CTRL_RD"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(13, 4), mmDCORE1_RTR3_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE0"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(13, 4), mmDCORE1_RTR3_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE1"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(12, 4), mmDCORE1_RTR2_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE2"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(11, 4), mmDCORE1_RTR1_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE3"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(10, 4), mmDCORE1_RTR0_CTRL_BASE,
    GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE4"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(7, 11), mmDCORE2_RTR5_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_WAP0"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(9, 11), mmDCORE2_RTR7_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_WAP1"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(8, 11), mmDCORE2_RTR6_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_CTRL_WR"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(9, 11), mmDCORE2_RTR7_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_CTRL_RD"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(6, 11), mmDCORE2_RTR4_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE0"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(6, 11), mmDCORE2_RTR4_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE1"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(7, 11), mmDCORE2_RTR5_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE2"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(8, 11), mmDCORE2_RTR6_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE3"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(9, 11), mmDCORE2_RTR7_CTRL_BASE,
    GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE4"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(12, 11), mmDCORE3_RTR2_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_WAP0"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(10, 11), mmDCORE3_RTR0_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_WAP1"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(11, 11), mmDCORE3_RTR1_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_CTRL_WR"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(10, 11), mmDCORE3_RTR0_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_CTRL_RD"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(13, 11), mmDCORE3_RTR3_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE0"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(13, 11), mmDCORE3_RTR3_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE1"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(12, 11), mmDCORE3_RTR2_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE2"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(11, 11), mmDCORE3_RTR1_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE3"},
  {RAZWI_INITIATOR_ID_X_Y_LOW(10, 11), mmDCORE3_RTR0_CTRL_BASE,
    GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE4"}
};

enum hl_pmmu_fatal_cause {
 LATENCY_RD_OUT_FIFO_OVERRUN,
 LATENCY_WR_OUT_FIFO_OVERRUN,
};

enum hl_pcie_drain_ind_cause {
 LBW_AXI_DRAIN_IND,
 HBW_AXI_DRAIN_IND
};

static const u32 cluster_hmmu_hif_enabled_mask[GAUDI2_HBM_NUM] = {
 [HBM_ID0] = 0xFFFC,
 [HBM_ID1] = 0xFFCF,
 [HBM_ID2] = 0xF7F7,
 [HBM_ID3] = 0x7F7F,
 [HBM_ID4] = 0xFCFF,
 [HBM_ID5] = 0xCFFF,
};

static const u8 xbar_edge_to_hbm_cluster[EDMA_ID_SIZE] = {
 [0] = HBM_ID0,
 [1] = HBM_ID1,
 [2] = HBM_ID4,
 [3] = HBM_ID5,
};

static const u8 edma_to_hbm_cluster[EDMA_ID_SIZE] = {
 [EDMA_ID_DCORE0_INSTANCE0] = HBM_ID0,
 [EDMA_ID_DCORE0_INSTANCE1] = HBM_ID2,
 [EDMA_ID_DCORE1_INSTANCE0] = HBM_ID1,
 [EDMA_ID_DCORE1_INSTANCE1] = HBM_ID3,
 [EDMA_ID_DCORE2_INSTANCE0] = HBM_ID2,
 [EDMA_ID_DCORE2_INSTANCE1] = HBM_ID4,
 [EDMA_ID_DCORE3_INSTANCE0] = HBM_ID3,
 [EDMA_ID_DCORE3_INSTANCE1] = HBM_ID5,
};

static const int gaudi2_qman_async_event_id[] = {
 [GAUDI2_QUEUE_ID_PDMA_0_0] = GAUDI2_EVENT_PDMA0_QM,
 [GAUDI2_QUEUE_ID_PDMA_0_1] = GAUDI2_EVENT_PDMA0_QM,
 [GAUDI2_QUEUE_ID_PDMA_0_2] = GAUDI2_EVENT_PDMA0_QM,
 [GAUDI2_QUEUE_ID_PDMA_0_3] = GAUDI2_EVENT_PDMA0_QM,
 [GAUDI2_QUEUE_ID_PDMA_1_0] = GAUDI2_EVENT_PDMA1_QM,
 [GAUDI2_QUEUE_ID_PDMA_1_1] = GAUDI2_EVENT_PDMA1_QM,
 [GAUDI2_QUEUE_ID_PDMA_1_2] = GAUDI2_EVENT_PDMA1_QM,
 [GAUDI2_QUEUE_ID_PDMA_1_3] = GAUDI2_EVENT_PDMA1_QM,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0] = GAUDI2_EVENT_HDMA0_QM,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1] = GAUDI2_EVENT_HDMA0_QM,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2] = GAUDI2_EVENT_HDMA0_QM,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] = GAUDI2_EVENT_HDMA0_QM,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0] = GAUDI2_EVENT_HDMA1_QM,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1] = GAUDI2_EVENT_HDMA1_QM,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2] = GAUDI2_EVENT_HDMA1_QM,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] = GAUDI2_EVENT_HDMA1_QM,
 [GAUDI2_QUEUE_ID_DCORE0_MME_0_0] = GAUDI2_EVENT_MME0_QM,
 [GAUDI2_QUEUE_ID_DCORE0_MME_0_1] = GAUDI2_EVENT_MME0_QM,
 [GAUDI2_QUEUE_ID_DCORE0_MME_0_2] = GAUDI2_EVENT_MME0_QM,
 [GAUDI2_QUEUE_ID_DCORE0_MME_0_3] = GAUDI2_EVENT_MME0_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_0] = GAUDI2_EVENT_TPC0_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_1] = GAUDI2_EVENT_TPC0_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_2] = GAUDI2_EVENT_TPC0_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = GAUDI2_EVENT_TPC0_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_1_0] = GAUDI2_EVENT_TPC1_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_1_1] = GAUDI2_EVENT_TPC1_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_1_2] = GAUDI2_EVENT_TPC1_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] = GAUDI2_EVENT_TPC1_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_2_0] = GAUDI2_EVENT_TPC2_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_2_1] = GAUDI2_EVENT_TPC2_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_2_2] = GAUDI2_EVENT_TPC2_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] = GAUDI2_EVENT_TPC2_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_3_0] = GAUDI2_EVENT_TPC3_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_3_1] = GAUDI2_EVENT_TPC3_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_3_2] = GAUDI2_EVENT_TPC3_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] = GAUDI2_EVENT_TPC3_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_4_0] = GAUDI2_EVENT_TPC4_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_4_1] = GAUDI2_EVENT_TPC4_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_4_2] = GAUDI2_EVENT_TPC4_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] = GAUDI2_EVENT_TPC4_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_5_0] = GAUDI2_EVENT_TPC5_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_5_1] = GAUDI2_EVENT_TPC5_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_5_2] = GAUDI2_EVENT_TPC5_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] = GAUDI2_EVENT_TPC5_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_6_0] = GAUDI2_EVENT_TPC24_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_6_1] = GAUDI2_EVENT_TPC24_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_6_2] = GAUDI2_EVENT_TPC24_QM,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] = GAUDI2_EVENT_TPC24_QM,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0] = GAUDI2_EVENT_HDMA2_QM,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1] = GAUDI2_EVENT_HDMA2_QM,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2] = GAUDI2_EVENT_HDMA2_QM,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] = GAUDI2_EVENT_HDMA2_QM,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0] = GAUDI2_EVENT_HDMA3_QM,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1] = GAUDI2_EVENT_HDMA3_QM,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2] = GAUDI2_EVENT_HDMA3_QM,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] = GAUDI2_EVENT_HDMA3_QM,
 [GAUDI2_QUEUE_ID_DCORE1_MME_0_0] = GAUDI2_EVENT_MME1_QM,
 [GAUDI2_QUEUE_ID_DCORE1_MME_0_1] = GAUDI2_EVENT_MME1_QM,
 [GAUDI2_QUEUE_ID_DCORE1_MME_0_2] = GAUDI2_EVENT_MME1_QM,
 [GAUDI2_QUEUE_ID_DCORE1_MME_0_3] = GAUDI2_EVENT_MME1_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_0_0] = GAUDI2_EVENT_TPC6_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_0_1] = GAUDI2_EVENT_TPC6_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_0_2] = GAUDI2_EVENT_TPC6_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] = GAUDI2_EVENT_TPC6_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_1_0] = GAUDI2_EVENT_TPC7_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_1_1] = GAUDI2_EVENT_TPC7_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_1_2] = GAUDI2_EVENT_TPC7_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] = GAUDI2_EVENT_TPC7_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_2_0] = GAUDI2_EVENT_TPC8_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_2_1] = GAUDI2_EVENT_TPC8_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_2_2] = GAUDI2_EVENT_TPC8_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] = GAUDI2_EVENT_TPC8_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_3_0] = GAUDI2_EVENT_TPC9_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_3_1] = GAUDI2_EVENT_TPC9_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_3_2] = GAUDI2_EVENT_TPC9_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] = GAUDI2_EVENT_TPC9_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_4_0] = GAUDI2_EVENT_TPC10_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_4_1] = GAUDI2_EVENT_TPC10_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_4_2] = GAUDI2_EVENT_TPC10_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] = GAUDI2_EVENT_TPC10_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_5_0] = GAUDI2_EVENT_TPC11_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_5_1] = GAUDI2_EVENT_TPC11_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_5_2] = GAUDI2_EVENT_TPC11_QM,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] = GAUDI2_EVENT_TPC11_QM,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0] = GAUDI2_EVENT_HDMA4_QM,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1] = GAUDI2_EVENT_HDMA4_QM,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2] = GAUDI2_EVENT_HDMA4_QM,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] = GAUDI2_EVENT_HDMA4_QM,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0] = GAUDI2_EVENT_HDMA5_QM,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1] = GAUDI2_EVENT_HDMA5_QM,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2] = GAUDI2_EVENT_HDMA5_QM,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] = GAUDI2_EVENT_HDMA5_QM,
 [GAUDI2_QUEUE_ID_DCORE2_MME_0_0] = GAUDI2_EVENT_MME2_QM,
 [GAUDI2_QUEUE_ID_DCORE2_MME_0_1] = GAUDI2_EVENT_MME2_QM,
 [GAUDI2_QUEUE_ID_DCORE2_MME_0_2] = GAUDI2_EVENT_MME2_QM,
 [GAUDI2_QUEUE_ID_DCORE2_MME_0_3] = GAUDI2_EVENT_MME2_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_0_0] = GAUDI2_EVENT_TPC12_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_0_1] = GAUDI2_EVENT_TPC12_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_0_2] = GAUDI2_EVENT_TPC12_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] = GAUDI2_EVENT_TPC12_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_1_0] = GAUDI2_EVENT_TPC13_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_1_1] = GAUDI2_EVENT_TPC13_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_1_2] = GAUDI2_EVENT_TPC13_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] = GAUDI2_EVENT_TPC13_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_2_0] = GAUDI2_EVENT_TPC14_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_2_1] = GAUDI2_EVENT_TPC14_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_2_2] = GAUDI2_EVENT_TPC14_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] = GAUDI2_EVENT_TPC14_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_3_0] = GAUDI2_EVENT_TPC15_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_3_1] = GAUDI2_EVENT_TPC15_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_3_2] = GAUDI2_EVENT_TPC15_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] = GAUDI2_EVENT_TPC15_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_4_0] = GAUDI2_EVENT_TPC16_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_4_1] = GAUDI2_EVENT_TPC16_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_4_2] = GAUDI2_EVENT_TPC16_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] = GAUDI2_EVENT_TPC16_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_5_0] = GAUDI2_EVENT_TPC17_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_5_1] = GAUDI2_EVENT_TPC17_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_5_2] = GAUDI2_EVENT_TPC17_QM,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] = GAUDI2_EVENT_TPC17_QM,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0] = GAUDI2_EVENT_HDMA6_QM,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1] = GAUDI2_EVENT_HDMA6_QM,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2] = GAUDI2_EVENT_HDMA6_QM,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] = GAUDI2_EVENT_HDMA6_QM,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0] = GAUDI2_EVENT_HDMA7_QM,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1] = GAUDI2_EVENT_HDMA7_QM,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2] = GAUDI2_EVENT_HDMA7_QM,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] = GAUDI2_EVENT_HDMA7_QM,
 [GAUDI2_QUEUE_ID_DCORE3_MME_0_0] = GAUDI2_EVENT_MME3_QM,
 [GAUDI2_QUEUE_ID_DCORE3_MME_0_1] = GAUDI2_EVENT_MME3_QM,
 [GAUDI2_QUEUE_ID_DCORE3_MME_0_2] = GAUDI2_EVENT_MME3_QM,
 [GAUDI2_QUEUE_ID_DCORE3_MME_0_3] = GAUDI2_EVENT_MME3_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_0_0] = GAUDI2_EVENT_TPC18_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_0_1] = GAUDI2_EVENT_TPC18_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_0_2] = GAUDI2_EVENT_TPC18_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] = GAUDI2_EVENT_TPC18_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_1_0] = GAUDI2_EVENT_TPC19_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_1_1] = GAUDI2_EVENT_TPC19_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_1_2] = GAUDI2_EVENT_TPC19_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] = GAUDI2_EVENT_TPC19_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_2_0] = GAUDI2_EVENT_TPC20_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_2_1] = GAUDI2_EVENT_TPC20_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_2_2] = GAUDI2_EVENT_TPC20_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] = GAUDI2_EVENT_TPC20_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_3_0] = GAUDI2_EVENT_TPC21_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_3_1] = GAUDI2_EVENT_TPC21_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_3_2] = GAUDI2_EVENT_TPC21_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] = GAUDI2_EVENT_TPC21_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_4_0] = GAUDI2_EVENT_TPC22_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_4_1] = GAUDI2_EVENT_TPC22_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_4_2] = GAUDI2_EVENT_TPC22_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] = GAUDI2_EVENT_TPC22_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_5_0] = GAUDI2_EVENT_TPC23_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_5_1] = GAUDI2_EVENT_TPC23_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_5_2] = GAUDI2_EVENT_TPC23_QM,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] = GAUDI2_EVENT_TPC23_QM,
 [GAUDI2_QUEUE_ID_NIC_0_0] = GAUDI2_EVENT_NIC0_QM0,
 [GAUDI2_QUEUE_ID_NIC_0_1] = GAUDI2_EVENT_NIC0_QM0,
 [GAUDI2_QUEUE_ID_NIC_0_2] = GAUDI2_EVENT_NIC0_QM0,
 [GAUDI2_QUEUE_ID_NIC_0_3] = GAUDI2_EVENT_NIC0_QM0,
 [GAUDI2_QUEUE_ID_NIC_1_0] = GAUDI2_EVENT_NIC0_QM1,
 [GAUDI2_QUEUE_ID_NIC_1_1] = GAUDI2_EVENT_NIC0_QM1,
 [GAUDI2_QUEUE_ID_NIC_1_2] = GAUDI2_EVENT_NIC0_QM1,
 [GAUDI2_QUEUE_ID_NIC_1_3] = GAUDI2_EVENT_NIC0_QM1,
 [GAUDI2_QUEUE_ID_NIC_2_0] = GAUDI2_EVENT_NIC1_QM0,
 [GAUDI2_QUEUE_ID_NIC_2_1] = GAUDI2_EVENT_NIC1_QM0,
 [GAUDI2_QUEUE_ID_NIC_2_2] = GAUDI2_EVENT_NIC1_QM0,
 [GAUDI2_QUEUE_ID_NIC_2_3] = GAUDI2_EVENT_NIC1_QM0,
 [GAUDI2_QUEUE_ID_NIC_3_0] = GAUDI2_EVENT_NIC1_QM1,
 [GAUDI2_QUEUE_ID_NIC_3_1] = GAUDI2_EVENT_NIC1_QM1,
 [GAUDI2_QUEUE_ID_NIC_3_2] = GAUDI2_EVENT_NIC1_QM1,
 [GAUDI2_QUEUE_ID_NIC_3_3] = GAUDI2_EVENT_NIC1_QM1,
 [GAUDI2_QUEUE_ID_NIC_4_0] = GAUDI2_EVENT_NIC2_QM0,
 [GAUDI2_QUEUE_ID_NIC_4_1] = GAUDI2_EVENT_NIC2_QM0,
 [GAUDI2_QUEUE_ID_NIC_4_2] = GAUDI2_EVENT_NIC2_QM0,
 [GAUDI2_QUEUE_ID_NIC_4_3] = GAUDI2_EVENT_NIC2_QM0,
 [GAUDI2_QUEUE_ID_NIC_5_0] = GAUDI2_EVENT_NIC2_QM1,
 [GAUDI2_QUEUE_ID_NIC_5_1] = GAUDI2_EVENT_NIC2_QM1,
 [GAUDI2_QUEUE_ID_NIC_5_2] = GAUDI2_EVENT_NIC2_QM1,
 [GAUDI2_QUEUE_ID_NIC_5_3] = GAUDI2_EVENT_NIC2_QM1,
 [GAUDI2_QUEUE_ID_NIC_6_0] = GAUDI2_EVENT_NIC3_QM0,
 [GAUDI2_QUEUE_ID_NIC_6_1] = GAUDI2_EVENT_NIC3_QM0,
 [GAUDI2_QUEUE_ID_NIC_6_2] = GAUDI2_EVENT_NIC3_QM0,
 [GAUDI2_QUEUE_ID_NIC_6_3] = GAUDI2_EVENT_NIC3_QM0,
 [GAUDI2_QUEUE_ID_NIC_7_0] = GAUDI2_EVENT_NIC3_QM1,
 [GAUDI2_QUEUE_ID_NIC_7_1] = GAUDI2_EVENT_NIC3_QM1,
 [GAUDI2_QUEUE_ID_NIC_7_2] = GAUDI2_EVENT_NIC3_QM1,
 [GAUDI2_QUEUE_ID_NIC_7_3] = GAUDI2_EVENT_NIC3_QM1,
 [GAUDI2_QUEUE_ID_NIC_8_0] = GAUDI2_EVENT_NIC4_QM0,
 [GAUDI2_QUEUE_ID_NIC_8_1] = GAUDI2_EVENT_NIC4_QM0,
 [GAUDI2_QUEUE_ID_NIC_8_2] = GAUDI2_EVENT_NIC4_QM0,
 [GAUDI2_QUEUE_ID_NIC_8_3] = GAUDI2_EVENT_NIC4_QM0,
 [GAUDI2_QUEUE_ID_NIC_9_0] = GAUDI2_EVENT_NIC4_QM1,
 [GAUDI2_QUEUE_ID_NIC_9_1] = GAUDI2_EVENT_NIC4_QM1,
 [GAUDI2_QUEUE_ID_NIC_9_2] = GAUDI2_EVENT_NIC4_QM1,
 [GAUDI2_QUEUE_ID_NIC_9_3] = GAUDI2_EVENT_NIC4_QM1,
 [GAUDI2_QUEUE_ID_NIC_10_0] = GAUDI2_EVENT_NIC5_QM0,
 [GAUDI2_QUEUE_ID_NIC_10_1] = GAUDI2_EVENT_NIC5_QM0,
 [GAUDI2_QUEUE_ID_NIC_10_2] = GAUDI2_EVENT_NIC5_QM0,
 [GAUDI2_QUEUE_ID_NIC_10_3] = GAUDI2_EVENT_NIC5_QM0,
 [GAUDI2_QUEUE_ID_NIC_11_0] = GAUDI2_EVENT_NIC5_QM1,
 [GAUDI2_QUEUE_ID_NIC_11_1] = GAUDI2_EVENT_NIC5_QM1,
 [GAUDI2_QUEUE_ID_NIC_11_2] = GAUDI2_EVENT_NIC5_QM1,
 [GAUDI2_QUEUE_ID_NIC_11_3] = GAUDI2_EVENT_NIC5_QM1,
 [GAUDI2_QUEUE_ID_NIC_12_0] = GAUDI2_EVENT_NIC6_QM0,
 [GAUDI2_QUEUE_ID_NIC_12_1] = GAUDI2_EVENT_NIC6_QM0,
 [GAUDI2_QUEUE_ID_NIC_12_2] = GAUDI2_EVENT_NIC6_QM0,
 [GAUDI2_QUEUE_ID_NIC_12_3] = GAUDI2_EVENT_NIC6_QM0,
 [GAUDI2_QUEUE_ID_NIC_13_0] = GAUDI2_EVENT_NIC6_QM1,
 [GAUDI2_QUEUE_ID_NIC_13_1] = GAUDI2_EVENT_NIC6_QM1,
 [GAUDI2_QUEUE_ID_NIC_13_2] = GAUDI2_EVENT_NIC6_QM1,
 [GAUDI2_QUEUE_ID_NIC_13_3] = GAUDI2_EVENT_NIC6_QM1,
 [GAUDI2_QUEUE_ID_NIC_14_0] = GAUDI2_EVENT_NIC7_QM0,
 [GAUDI2_QUEUE_ID_NIC_14_1] = GAUDI2_EVENT_NIC7_QM0,
 [GAUDI2_QUEUE_ID_NIC_14_2] = GAUDI2_EVENT_NIC7_QM0,
 [GAUDI2_QUEUE_ID_NIC_14_3] = GAUDI2_EVENT_NIC7_QM0,
 [GAUDI2_QUEUE_ID_NIC_15_0] = GAUDI2_EVENT_NIC7_QM1,
 [GAUDI2_QUEUE_ID_NIC_15_1] = GAUDI2_EVENT_NIC7_QM1,
 [GAUDI2_QUEUE_ID_NIC_15_2] = GAUDI2_EVENT_NIC7_QM1,
 [GAUDI2_QUEUE_ID_NIC_15_3] = GAUDI2_EVENT_NIC7_QM1,
 [GAUDI2_QUEUE_ID_NIC_16_0] = GAUDI2_EVENT_NIC8_QM0,
 [GAUDI2_QUEUE_ID_NIC_16_1] = GAUDI2_EVENT_NIC8_QM0,
 [GAUDI2_QUEUE_ID_NIC_16_2] = GAUDI2_EVENT_NIC8_QM0,
 [GAUDI2_QUEUE_ID_NIC_16_3] = GAUDI2_EVENT_NIC8_QM0,
 [GAUDI2_QUEUE_ID_NIC_17_0] = GAUDI2_EVENT_NIC8_QM1,
 [GAUDI2_QUEUE_ID_NIC_17_1] = GAUDI2_EVENT_NIC8_QM1,
 [GAUDI2_QUEUE_ID_NIC_17_2] = GAUDI2_EVENT_NIC8_QM1,
 [GAUDI2_QUEUE_ID_NIC_17_3] = GAUDI2_EVENT_NIC8_QM1,
 [GAUDI2_QUEUE_ID_NIC_18_0] = GAUDI2_EVENT_NIC9_QM0,
 [GAUDI2_QUEUE_ID_NIC_18_1] = GAUDI2_EVENT_NIC9_QM0,
 [GAUDI2_QUEUE_ID_NIC_18_2] = GAUDI2_EVENT_NIC9_QM0,
 [GAUDI2_QUEUE_ID_NIC_18_3] = GAUDI2_EVENT_NIC9_QM0,
 [GAUDI2_QUEUE_ID_NIC_19_0] = GAUDI2_EVENT_NIC9_QM1,
 [GAUDI2_QUEUE_ID_NIC_19_1] = GAUDI2_EVENT_NIC9_QM1,
 [GAUDI2_QUEUE_ID_NIC_19_2] = GAUDI2_EVENT_NIC9_QM1,
 [GAUDI2_QUEUE_ID_NIC_19_3] = GAUDI2_EVENT_NIC9_QM1,
 [GAUDI2_QUEUE_ID_NIC_20_0] = GAUDI2_EVENT_NIC10_QM0,
 [GAUDI2_QUEUE_ID_NIC_20_1] = GAUDI2_EVENT_NIC10_QM0,
 [GAUDI2_QUEUE_ID_NIC_20_2] = GAUDI2_EVENT_NIC10_QM0,
 [GAUDI2_QUEUE_ID_NIC_20_3] = GAUDI2_EVENT_NIC10_QM0,
 [GAUDI2_QUEUE_ID_NIC_21_0] = GAUDI2_EVENT_NIC10_QM1,
 [GAUDI2_QUEUE_ID_NIC_21_1] = GAUDI2_EVENT_NIC10_QM1,
 [GAUDI2_QUEUE_ID_NIC_21_2] = GAUDI2_EVENT_NIC10_QM1,
 [GAUDI2_QUEUE_ID_NIC_21_3] = GAUDI2_EVENT_NIC10_QM1,
 [GAUDI2_QUEUE_ID_NIC_22_0] = GAUDI2_EVENT_NIC11_QM0,
 [GAUDI2_QUEUE_ID_NIC_22_1] = GAUDI2_EVENT_NIC11_QM0,
 [GAUDI2_QUEUE_ID_NIC_22_2] = GAUDI2_EVENT_NIC11_QM0,
 [GAUDI2_QUEUE_ID_NIC_22_3] = GAUDI2_EVENT_NIC11_QM0,
 [GAUDI2_QUEUE_ID_NIC_23_0] = GAUDI2_EVENT_NIC11_QM1,
 [GAUDI2_QUEUE_ID_NIC_23_1] = GAUDI2_EVENT_NIC11_QM1,
 [GAUDI2_QUEUE_ID_NIC_23_2] = GAUDI2_EVENT_NIC11_QM1,
 [GAUDI2_QUEUE_ID_NIC_23_3] = GAUDI2_EVENT_NIC11_QM1,
 [GAUDI2_QUEUE_ID_ROT_0_0] = GAUDI2_EVENT_ROTATOR0_ROT0_QM,
 [GAUDI2_QUEUE_ID_ROT_0_1] = GAUDI2_EVENT_ROTATOR0_ROT0_QM,
 [GAUDI2_QUEUE_ID_ROT_0_2] = GAUDI2_EVENT_ROTATOR0_ROT0_QM,
 [GAUDI2_QUEUE_ID_ROT_0_3] = GAUDI2_EVENT_ROTATOR0_ROT0_QM,
 [GAUDI2_QUEUE_ID_ROT_1_0] = GAUDI2_EVENT_ROTATOR1_ROT1_QM,
 [GAUDI2_QUEUE_ID_ROT_1_1] = GAUDI2_EVENT_ROTATOR1_ROT1_QM,
 [GAUDI2_QUEUE_ID_ROT_1_2] = GAUDI2_EVENT_ROTATOR1_ROT1_QM,
 [GAUDI2_QUEUE_ID_ROT_1_3] = GAUDI2_EVENT_ROTATOR1_ROT1_QM
};

static const int gaudi2_dma_core_async_event_id[] = {
 [DMA_CORE_ID_EDMA0] = GAUDI2_EVENT_HDMA0_CORE,
 [DMA_CORE_ID_EDMA1] = GAUDI2_EVENT_HDMA1_CORE,
 [DMA_CORE_ID_EDMA2] = GAUDI2_EVENT_HDMA2_CORE,
 [DMA_CORE_ID_EDMA3] = GAUDI2_EVENT_HDMA3_CORE,
 [DMA_CORE_ID_EDMA4] = GAUDI2_EVENT_HDMA4_CORE,
 [DMA_CORE_ID_EDMA5] = GAUDI2_EVENT_HDMA5_CORE,
 [DMA_CORE_ID_EDMA6] = GAUDI2_EVENT_HDMA6_CORE,
 [DMA_CORE_ID_EDMA7] = GAUDI2_EVENT_HDMA7_CORE,
 [DMA_CORE_ID_PDMA0] = GAUDI2_EVENT_PDMA0_CORE,
 [DMA_CORE_ID_PDMA1] = GAUDI2_EVENT_PDMA1_CORE,
 [DMA_CORE_ID_KDMA] = GAUDI2_EVENT_KDMA0_CORE,
};

static const char * const gaudi2_qm_sei_error_cause[GAUDI2_NUM_OF_QM_SEI_ERR_CAUSE] = {
 "qman sei intr",
 "arc sei intr"
};

static const char * const gaudi2_cpu_sei_error_cause[GAUDI2_NUM_OF_CPU_SEI_ERR_CAUSE] = {
 "AXI_TERMINATOR WR",
 "AXI_TERMINATOR RD",
 "AXI SPLIT SEI Status"
};

static const char * const gaudi2_arc_sei_error_cause[GAUDI2_NUM_OF_ARC_SEI_ERR_CAUSE] = {
 "cbu_bresp_sei_intr_cause",
 "cbu_rresp_sei_intr_cause",
 "lbu_bresp_sei_intr_cause",
 "lbu_rresp_sei_intr_cause",
 "cbu_axi_split_intr_cause",
 "lbu_axi_split_intr_cause",
 "arc_ip_excptn_sei_intr_cause",
 "dmi_bresp_sei_intr_cause",
 "aux2apb_err_sei_intr_cause",
 "cfg_lbw_wr_terminated_intr_cause",
 "cfg_lbw_rd_terminated_intr_cause",
 "cfg_dccm_wr_terminated_intr_cause",
 "cfg_dccm_rd_terminated_intr_cause",
 "cfg_hbw_rd_terminated_intr_cause"
};

static const char * const gaudi2_dec_error_cause[GAUDI2_NUM_OF_DEC_ERR_CAUSE] = {
 "msix_vcd_hbw_sei",
 "msix_l2c_hbw_sei",
 "msix_nrm_hbw_sei",
 "msix_abnrm_hbw_sei",
 "msix_vcd_lbw_sei",
 "msix_l2c_lbw_sei",
 "msix_nrm_lbw_sei",
 "msix_abnrm_lbw_sei",
 "apb_vcd_lbw_sei",
 "apb_l2c_lbw_sei",
 "apb_nrm_lbw_sei",
 "apb_abnrm_lbw_sei",
 "dec_sei",
 "dec_apb_sei",
 "trc_apb_sei",
 "lbw_mstr_if_sei",
 "axi_split_bresp_err_sei",
 "hbw_axi_wr_viol_sei",
 "hbw_axi_rd_viol_sei",
 "lbw_axi_wr_viol_sei",
 "lbw_axi_rd_viol_sei",
 "vcd_spi",
 "l2c_spi",
 "nrm_spi",
 "abnrm_spi",
};

static const char * const gaudi2_qman_error_cause[GAUDI2_NUM_OF_QM_ERR_CAUSE] = {
 "PQ AXI HBW error",
 "CQ AXI HBW error",
 "CP AXI HBW error",
 "CP error due to undefined OPCODE",
 "CP encountered STOP OPCODE",
 "CP AXI LBW error",
 "CP WRREG32 or WRBULK returned error",
 "N/A",
 "FENCE 0 inc over max value and clipped",
 "FENCE 1 inc over max value and clipped",
 "FENCE 2 inc over max value and clipped",
 "FENCE 3 inc over max value and clipped",
 "FENCE 0 dec under min value and clipped",
 "FENCE 1 dec under min value and clipped",
 "FENCE 2 dec under min value and clipped",
 "FENCE 3 dec under min value and clipped",
 "CPDMA Up overflow",
 "PQC L2H error"
};

static const char * const gaudi2_lower_qman_error_cause[GAUDI2_NUM_OF_LOWER_QM_ERR_CAUSE] = {
 "RSVD0",
 "CQ AXI HBW error",
 "CP AXI HBW error",
 "CP error due to undefined OPCODE",
 "CP encountered STOP OPCODE",
 "CP AXI LBW error",
 "CP WRREG32 or WRBULK returned error",
 "N/A",
 "FENCE 0 inc over max value and clipped",
 "FENCE 1 inc over max value and clipped",
 "FENCE 2 inc over max value and clipped",
 "FENCE 3 inc over max value and clipped",
 "FENCE 0 dec under min value and clipped",
 "FENCE 1 dec under min value and clipped",
 "FENCE 2 dec under min value and clipped",
 "FENCE 3 dec under min value and clipped",
 "CPDMA Up overflow",
 "RSVD17",
 "CQ_WR_IFIFO_CI_ERR",
 "CQ_WR_CTL_CI_ERR",
 "ARC_CQF_RD_ERR",
 "ARC_CQ_WR_IFIFO_CI_ERR",
 "ARC_CQ_WR_CTL_CI_ERR",
 "ARC_AXI_ERR",
 "CP_SWITCH_WDT_ERR"
};

static const char * const gaudi2_qman_arb_error_cause[GAUDI2_NUM_OF_QM_ARB_ERR_CAUSE] = {
 "Choice push while full error",
 "Choice Q watchdog error",
 "MSG AXI LBW returned with error"
};

static const char * const guadi2_rot_error_cause[GAUDI2_NUM_OF_ROT_ERR_CAUSE] = {
 "qm_axi_err",
 "qm_trace_fence_events",
 "qm_sw_err",
 "qm_cp_sw_stop",
 "lbw_mstr_rresp_err",
 "lbw_mstr_bresp_err",
 "lbw_msg_slverr",
 "hbw_msg_slverr",
 "wbc_slverr",
 "hbw_mstr_rresp_err",
 "hbw_mstr_bresp_err",
 "sb_resp_intr",
 "mrsb_resp_intr",
 "core_dw_status_0",
 "core_dw_status_1",
 "core_dw_status_2",
 "core_dw_status_3",
 "core_dw_status_4",
 "core_dw_status_5",
 "core_dw_status_6",
 "core_dw_status_7",
 "async_arc2cpu_sei_intr",
};

static const char * const gaudi2_tpc_interrupts_cause[GAUDI2_NUM_OF_TPC_INTR_CAUSE] = {
 "tpc_address_exceed_slm",
 "tpc_div_by_0",
 "tpc_spu_mac_overflow",
 "tpc_spu_addsub_overflow",
 "tpc_spu_abs_overflow",
 "tpc_spu_fma_fp_dst_nan",
 "tpc_spu_fma_fp_dst_inf",
 "tpc_spu_convert_fp_dst_nan",
 "tpc_spu_convert_fp_dst_inf",
 "tpc_spu_fp_dst_denorm",
 "tpc_vpu_mac_overflow",
 "tpc_vpu_addsub_overflow",
 "tpc_vpu_abs_overflow",
 "tpc_vpu_convert_fp_dst_nan",
 "tpc_vpu_convert_fp_dst_inf",
 "tpc_vpu_fma_fp_dst_nan",
 "tpc_vpu_fma_fp_dst_inf",
 "tpc_vpu_fp_dst_denorm",
 "tpc_assertions",
 "tpc_illegal_instruction",
 "tpc_pc_wrap_around",
 "tpc_qm_sw_err",
 "tpc_hbw_rresp_err",
 "tpc_hbw_bresp_err",
 "tpc_lbw_rresp_err",
 "tpc_lbw_bresp_err",
 "st_unlock_already_locked",
 "invalid_lock_access",
 "LD_L protection violation",
 "ST_L protection violation",
 "D$ L0CS mismatch",
};

static const char * const guadi2_mme_error_cause[GAUDI2_NUM_OF_MME_ERR_CAUSE] = {
 "agu_resp_intr",
 "qman_axi_err",
 "wap sei (wbc axi err)",
 "arc sei",
 "cfg access error",
 "qm_sw_err",
 "sbte_dbg_intr_0",
 "sbte_dbg_intr_1",
 "sbte_dbg_intr_2",
 "sbte_dbg_intr_3",
 "sbte_dbg_intr_4",
 "sbte_prtn_intr_0",
 "sbte_prtn_intr_1",
 "sbte_prtn_intr_2",
 "sbte_prtn_intr_3",
 "sbte_prtn_intr_4",
};

static const char * const guadi2_mme_wap_error_cause[GAUDI2_NUM_OF_MME_WAP_ERR_CAUSE] = {
 "WBC ERR RESP_0",
 "WBC ERR RESP_1",
 "AP SOURCE POS INF",
 "AP SOURCE NEG INF",
 "AP SOURCE NAN",
 "AP RESULT POS INF",
 "AP RESULT NEG INF",
};

static const char * const gaudi2_dma_core_interrupts_cause[GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE] = {
 "HBW Read returned with error RRESP",
 "HBW write returned with error BRESP",
 "LBW write returned with error BRESP",
 "descriptor_fifo_overflow",
 "KDMA SB LBW Read returned with error",
 "KDMA WBC LBW Write returned with error",
 "TRANSPOSE ENGINE DESC FIFO OVERFLOW",
 "WRONG CFG FOR COMMIT IN LIN DMA"
};

static const char * const gaudi2_kdma_core_interrupts_cause[GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE] = {
 "HBW/LBW Read returned with error RRESP",
 "HBW/LBW write returned with error BRESP",
 "LBW write returned with error BRESP",
 "descriptor_fifo_overflow",
 "KDMA SB LBW Read returned with error",
 "KDMA WBC LBW Write returned with error",
 "TRANSPOSE ENGINE DESC FIFO OVERFLOW",
 "WRONG CFG FOR COMMIT IN LIN DMA"
};

struct gaudi2_sm_sei_cause_data {
 const char *cause_name;
 const char *log_name;
};

static const struct gaudi2_sm_sei_cause_data
gaudi2_sm_sei_cause[GAUDI2_NUM_OF_SM_SEI_ERR_CAUSE] = {
 {"calculated SO value overflow/underflow", "SOB ID"},
 {"payload address of monitor is not aligned to 4B", "monitor addr"},
 {"armed monitor write got BRESP (SLVERR or DECERR)", "AXI id"},
};

static const char * const
gaudi2_pmmu_fatal_interrupts_cause[GAUDI2_NUM_OF_PMMU_FATAL_ERR_CAUSE] = {
 "LATENCY_RD_OUT_FIFO_OVERRUN",
 "LATENCY_WR_OUT_FIFO_OVERRUN",
};

static const char * const
gaudi2_hif_fatal_interrupts_cause[GAUDI2_NUM_OF_HIF_FATAL_ERR_CAUSE] = {
 "LATENCY_RD_OUT_FIFO_OVERRUN",
 "LATENCY_WR_OUT_FIFO_OVERRUN",
};

static const char * const
gaudi2_psoc_axi_drain_interrupts_cause[GAUDI2_NUM_OF_AXI_DRAIN_ERR_CAUSE] = {
 "AXI drain HBW",
 "AXI drain LBW",
};

static const char * const
gaudi2_pcie_addr_dec_error_cause[GAUDI2_NUM_OF_PCIE_ADDR_DEC_ERR_CAUSE] = {
 "HBW error response",
 "LBW error response",
 "TLP is blocked by RR"
};

static const int gaudi2_queue_id_to_engine_id[] = {
 [GAUDI2_QUEUE_ID_PDMA_0_0...GAUDI2_QUEUE_ID_PDMA_0_3] = GAUDI2_ENGINE_ID_PDMA_0,
 [GAUDI2_QUEUE_ID_PDMA_1_0...GAUDI2_QUEUE_ID_PDMA_1_3] = GAUDI2_ENGINE_ID_PDMA_1,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] =
       GAUDI2_DCORE0_ENGINE_ID_EDMA_0,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] =
       GAUDI2_DCORE0_ENGINE_ID_EDMA_1,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] =
       GAUDI2_DCORE1_ENGINE_ID_EDMA_0,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0...GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] =
       GAUDI2_DCORE1_ENGINE_ID_EDMA_1,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] =
       GAUDI2_DCORE2_ENGINE_ID_EDMA_0,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0...GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] =
       GAUDI2_DCORE2_ENGINE_ID_EDMA_1,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] =
       GAUDI2_DCORE3_ENGINE_ID_EDMA_0,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0...GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] =
       GAUDI2_DCORE3_ENGINE_ID_EDMA_1,
 [GAUDI2_QUEUE_ID_DCORE0_MME_0_0...GAUDI2_QUEUE_ID_DCORE0_MME_0_3] =
       GAUDI2_DCORE0_ENGINE_ID_MME,
 [GAUDI2_QUEUE_ID_DCORE1_MME_0_0...GAUDI2_QUEUE_ID_DCORE1_MME_0_3] =
       GAUDI2_DCORE1_ENGINE_ID_MME,
 [GAUDI2_QUEUE_ID_DCORE2_MME_0_0...GAUDI2_QUEUE_ID_DCORE2_MME_0_3] =
       GAUDI2_DCORE2_ENGINE_ID_MME,
 [GAUDI2_QUEUE_ID_DCORE3_MME_0_0...GAUDI2_QUEUE_ID_DCORE3_MME_0_3] =
       GAUDI2_DCORE3_ENGINE_ID_MME,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_0...GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] =
       GAUDI2_DCORE0_ENGINE_ID_TPC_0,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_1_0...GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] =
       GAUDI2_DCORE0_ENGINE_ID_TPC_1,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_2_0...GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] =
       GAUDI2_DCORE0_ENGINE_ID_TPC_2,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_3_0...GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] =
       GAUDI2_DCORE0_ENGINE_ID_TPC_3,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_4_0...GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] =
       GAUDI2_DCORE0_ENGINE_ID_TPC_4,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_5_0...GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] =
       GAUDI2_DCORE0_ENGINE_ID_TPC_5,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_6_0...GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] =
       GAUDI2_DCORE0_ENGINE_ID_TPC_6,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_0_0...GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] =
       GAUDI2_DCORE1_ENGINE_ID_TPC_0,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_1_0...GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] =
       GAUDI2_DCORE1_ENGINE_ID_TPC_1,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_2_0...GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] =
       GAUDI2_DCORE1_ENGINE_ID_TPC_2,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_3_0...GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] =
       GAUDI2_DCORE1_ENGINE_ID_TPC_3,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_4_0...GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] =
       GAUDI2_DCORE1_ENGINE_ID_TPC_4,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_5_0...GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] =
       GAUDI2_DCORE1_ENGINE_ID_TPC_5,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_0_0...GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] =
       GAUDI2_DCORE2_ENGINE_ID_TPC_0,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_1_0...GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] =
       GAUDI2_DCORE2_ENGINE_ID_TPC_1,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_2_0...GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] =
       GAUDI2_DCORE2_ENGINE_ID_TPC_2,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_3_0...GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] =
       GAUDI2_DCORE2_ENGINE_ID_TPC_3,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_4_0...GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] =
       GAUDI2_DCORE2_ENGINE_ID_TPC_4,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_5_0...GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] =
       GAUDI2_DCORE2_ENGINE_ID_TPC_5,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_0_0...GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] =
       GAUDI2_DCORE3_ENGINE_ID_TPC_0,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_1_0...GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] =
       GAUDI2_DCORE3_ENGINE_ID_TPC_1,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_2_0...GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] =
       GAUDI2_DCORE3_ENGINE_ID_TPC_2,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_3_0...GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] =
       GAUDI2_DCORE3_ENGINE_ID_TPC_3,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_4_0...GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] =
       GAUDI2_DCORE3_ENGINE_ID_TPC_4,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_5_0...GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] =
       GAUDI2_DCORE3_ENGINE_ID_TPC_5,
 [GAUDI2_QUEUE_ID_NIC_0_0...GAUDI2_QUEUE_ID_NIC_0_3] = GAUDI2_ENGINE_ID_NIC0_0,
 [GAUDI2_QUEUE_ID_NIC_1_0...GAUDI2_QUEUE_ID_NIC_1_3] = GAUDI2_ENGINE_ID_NIC0_1,
 [GAUDI2_QUEUE_ID_NIC_2_0...GAUDI2_QUEUE_ID_NIC_2_3] = GAUDI2_ENGINE_ID_NIC1_0,
 [GAUDI2_QUEUE_ID_NIC_3_0...GAUDI2_QUEUE_ID_NIC_3_3] = GAUDI2_ENGINE_ID_NIC1_1,
 [GAUDI2_QUEUE_ID_NIC_4_0...GAUDI2_QUEUE_ID_NIC_4_3] = GAUDI2_ENGINE_ID_NIC2_0,
 [GAUDI2_QUEUE_ID_NIC_5_0...GAUDI2_QUEUE_ID_NIC_5_3] = GAUDI2_ENGINE_ID_NIC2_1,
 [GAUDI2_QUEUE_ID_NIC_6_0...GAUDI2_QUEUE_ID_NIC_6_3] = GAUDI2_ENGINE_ID_NIC3_0,
 [GAUDI2_QUEUE_ID_NIC_7_0...GAUDI2_QUEUE_ID_NIC_7_3] = GAUDI2_ENGINE_ID_NIC3_1,
 [GAUDI2_QUEUE_ID_NIC_8_0...GAUDI2_QUEUE_ID_NIC_8_3] = GAUDI2_ENGINE_ID_NIC4_0,
 [GAUDI2_QUEUE_ID_NIC_9_0...GAUDI2_QUEUE_ID_NIC_9_3] = GAUDI2_ENGINE_ID_NIC4_1,
 [GAUDI2_QUEUE_ID_NIC_10_0...GAUDI2_QUEUE_ID_NIC_10_3] = GAUDI2_ENGINE_ID_NIC5_0,
 [GAUDI2_QUEUE_ID_NIC_11_0...GAUDI2_QUEUE_ID_NIC_11_3] = GAUDI2_ENGINE_ID_NIC5_1,
 [GAUDI2_QUEUE_ID_NIC_12_0...GAUDI2_QUEUE_ID_NIC_12_3] = GAUDI2_ENGINE_ID_NIC6_0,
 [GAUDI2_QUEUE_ID_NIC_13_0...GAUDI2_QUEUE_ID_NIC_13_3] = GAUDI2_ENGINE_ID_NIC6_1,
 [GAUDI2_QUEUE_ID_NIC_14_0...GAUDI2_QUEUE_ID_NIC_14_3] = GAUDI2_ENGINE_ID_NIC7_0,
 [GAUDI2_QUEUE_ID_NIC_15_0...GAUDI2_QUEUE_ID_NIC_15_3] = GAUDI2_ENGINE_ID_NIC7_1,
 [GAUDI2_QUEUE_ID_NIC_16_0...GAUDI2_QUEUE_ID_NIC_16_3] = GAUDI2_ENGINE_ID_NIC8_0,
 [GAUDI2_QUEUE_ID_NIC_17_0...GAUDI2_QUEUE_ID_NIC_17_3] = GAUDI2_ENGINE_ID_NIC8_1,
 [GAUDI2_QUEUE_ID_NIC_18_0...GAUDI2_QUEUE_ID_NIC_18_3] = GAUDI2_ENGINE_ID_NIC9_0,
 [GAUDI2_QUEUE_ID_NIC_19_0...GAUDI2_QUEUE_ID_NIC_19_3] = GAUDI2_ENGINE_ID_NIC9_1,
 [GAUDI2_QUEUE_ID_NIC_20_0...GAUDI2_QUEUE_ID_NIC_20_3] = GAUDI2_ENGINE_ID_NIC10_0,
 [GAUDI2_QUEUE_ID_NIC_21_0...GAUDI2_QUEUE_ID_NIC_21_3] = GAUDI2_ENGINE_ID_NIC10_1,
 [GAUDI2_QUEUE_ID_NIC_22_0...GAUDI2_QUEUE_ID_NIC_22_3] = GAUDI2_ENGINE_ID_NIC11_0,
 [GAUDI2_QUEUE_ID_NIC_23_0...GAUDI2_QUEUE_ID_NIC_23_3] = GAUDI2_ENGINE_ID_NIC11_1,
 [GAUDI2_QUEUE_ID_ROT_0_0...GAUDI2_QUEUE_ID_ROT_0_3] = GAUDI2_ENGINE_ID_ROT_0,
 [GAUDI2_QUEUE_ID_ROT_1_0...GAUDI2_QUEUE_ID_ROT_1_3] = GAUDI2_ENGINE_ID_ROT_1,
};

const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE] = {
 [GAUDI2_QUEUE_ID_PDMA_0_0] = mmPDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_PDMA_0_1] = mmPDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_PDMA_0_2] = mmPDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_PDMA_0_3] = mmPDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_PDMA_1_0] = mmPDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_PDMA_1_1] = mmPDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_PDMA_1_2] = mmPDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_PDMA_1_3] = mmPDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0] = mmDCORE0_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1] = mmDCORE0_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2] = mmDCORE0_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] = mmDCORE0_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0] = mmDCORE0_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1] = mmDCORE0_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2] = mmDCORE0_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] = mmDCORE0_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_MME_0_0] = mmDCORE0_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_MME_0_1] = mmDCORE0_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_MME_0_2] = mmDCORE0_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_MME_0_3] = mmDCORE0_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_0] = mmDCORE0_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_1] = mmDCORE0_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_2] = mmDCORE0_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = mmDCORE0_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_1_0] = mmDCORE0_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_1_1] = mmDCORE0_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_1_2] = mmDCORE0_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] = mmDCORE0_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_2_0] = mmDCORE0_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_2_1] = mmDCORE0_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_2_2] = mmDCORE0_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] = mmDCORE0_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_3_0] = mmDCORE0_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_3_1] = mmDCORE0_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_3_2] = mmDCORE0_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] = mmDCORE0_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_4_0] = mmDCORE0_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_4_1] = mmDCORE0_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_4_2] = mmDCORE0_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] = mmDCORE0_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_5_0] = mmDCORE0_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_5_1] = mmDCORE0_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_5_2] = mmDCORE0_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] = mmDCORE0_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_6_0] = mmDCORE0_TPC6_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_6_1] = mmDCORE0_TPC6_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_6_2] = mmDCORE0_TPC6_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] = mmDCORE0_TPC6_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0] = mmDCORE1_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1] = mmDCORE1_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2] = mmDCORE1_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] = mmDCORE1_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0] = mmDCORE1_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1] = mmDCORE1_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2] = mmDCORE1_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] = mmDCORE1_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_MME_0_0] = mmDCORE1_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_MME_0_1] = mmDCORE1_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_MME_0_2] = mmDCORE1_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_MME_0_3] = mmDCORE1_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_0_0] = mmDCORE1_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_0_1] = mmDCORE1_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_0_2] = mmDCORE1_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] = mmDCORE1_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_1_0] = mmDCORE1_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_1_1] = mmDCORE1_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_1_2] = mmDCORE1_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] = mmDCORE1_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_2_0] = mmDCORE1_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_2_1] = mmDCORE1_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_2_2] = mmDCORE1_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] = mmDCORE1_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_3_0] = mmDCORE1_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_3_1] = mmDCORE1_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_3_2] = mmDCORE1_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] = mmDCORE1_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_4_0] = mmDCORE1_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_4_1] = mmDCORE1_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_4_2] = mmDCORE1_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] = mmDCORE1_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_5_0] = mmDCORE1_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_5_1] = mmDCORE1_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_5_2] = mmDCORE1_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] = mmDCORE1_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0] = mmDCORE2_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1] = mmDCORE2_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2] = mmDCORE2_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] = mmDCORE2_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0] = mmDCORE2_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1] = mmDCORE2_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2] = mmDCORE2_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] = mmDCORE2_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_MME_0_0] = mmDCORE2_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_MME_0_1] = mmDCORE2_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_MME_0_2] = mmDCORE2_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_MME_0_3] = mmDCORE2_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_0_0] = mmDCORE2_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_0_1] = mmDCORE2_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_0_2] = mmDCORE2_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] = mmDCORE2_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_1_0] = mmDCORE2_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_1_1] = mmDCORE2_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_1_2] = mmDCORE2_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] = mmDCORE2_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_2_0] = mmDCORE2_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_2_1] = mmDCORE2_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_2_2] = mmDCORE2_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] = mmDCORE2_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_3_0] = mmDCORE2_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_3_1] = mmDCORE2_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_3_2] = mmDCORE2_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] = mmDCORE2_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_4_0] = mmDCORE2_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_4_1] = mmDCORE2_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_4_2] = mmDCORE2_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] = mmDCORE2_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_5_0] = mmDCORE2_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_5_1] = mmDCORE2_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_5_2] = mmDCORE2_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] = mmDCORE2_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0] = mmDCORE3_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1] = mmDCORE3_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2] = mmDCORE3_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] = mmDCORE3_EDMA0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0] = mmDCORE3_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1] = mmDCORE3_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2] = mmDCORE3_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] = mmDCORE3_EDMA1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_MME_0_0] = mmDCORE3_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_MME_0_1] = mmDCORE3_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_MME_0_2] = mmDCORE3_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_MME_0_3] = mmDCORE3_MME_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_0_0] = mmDCORE3_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_0_1] = mmDCORE3_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_0_2] = mmDCORE3_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] = mmDCORE3_TPC0_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_1_0] = mmDCORE3_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_1_1] = mmDCORE3_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_1_2] = mmDCORE3_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] = mmDCORE3_TPC1_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_2_0] = mmDCORE3_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_2_1] = mmDCORE3_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_2_2] = mmDCORE3_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] = mmDCORE3_TPC2_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_3_0] = mmDCORE3_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_3_1] = mmDCORE3_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_3_2] = mmDCORE3_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] = mmDCORE3_TPC3_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_4_0] = mmDCORE3_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_4_1] = mmDCORE3_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_4_2] = mmDCORE3_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] = mmDCORE3_TPC4_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_5_0] = mmDCORE3_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_5_1] = mmDCORE3_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_5_2] = mmDCORE3_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] = mmDCORE3_TPC5_QM_BASE,
 [GAUDI2_QUEUE_ID_NIC_0_0] = mmNIC0_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_0_1] = mmNIC0_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_0_2] = mmNIC0_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_0_3] = mmNIC0_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_1_0] = mmNIC0_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_1_1] = mmNIC0_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_1_2] = mmNIC0_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_1_3] = mmNIC0_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_2_0] = mmNIC1_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_2_1] = mmNIC1_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_2_2] = mmNIC1_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_2_3] = mmNIC1_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_3_0] = mmNIC1_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_3_1] = mmNIC1_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_3_2] = mmNIC1_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_3_3] = mmNIC1_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_4_0] = mmNIC2_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_4_1] = mmNIC2_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_4_2] = mmNIC2_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_4_3] = mmNIC2_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_5_0] = mmNIC2_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_5_1] = mmNIC2_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_5_2] = mmNIC2_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_5_3] = mmNIC2_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_6_0] = mmNIC3_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_6_1] = mmNIC3_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_6_2] = mmNIC3_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_6_3] = mmNIC3_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_7_0] = mmNIC3_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_7_1] = mmNIC3_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_7_2] = mmNIC3_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_7_3] = mmNIC3_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_8_0] = mmNIC4_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_8_1] = mmNIC4_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_8_2] = mmNIC4_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_8_3] = mmNIC4_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_9_0] = mmNIC4_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_9_1] = mmNIC4_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_9_2] = mmNIC4_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_9_3] = mmNIC4_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_10_0] = mmNIC5_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_10_1] = mmNIC5_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_10_2] = mmNIC5_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_10_3] = mmNIC5_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_11_0] = mmNIC5_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_11_1] = mmNIC5_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_11_2] = mmNIC5_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_11_3] = mmNIC5_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_12_0] = mmNIC6_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_12_1] = mmNIC6_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_12_2] = mmNIC6_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_12_3] = mmNIC6_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_13_0] = mmNIC6_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_13_1] = mmNIC6_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_13_2] = mmNIC6_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_13_3] = mmNIC6_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_14_0] = mmNIC7_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_14_1] = mmNIC7_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_14_2] = mmNIC7_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_14_3] = mmNIC7_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_15_0] = mmNIC7_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_15_1] = mmNIC7_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_15_2] = mmNIC7_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_15_3] = mmNIC7_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_16_0] = mmNIC8_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_16_1] = mmNIC8_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_16_2] = mmNIC8_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_16_3] = mmNIC8_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_17_0] = mmNIC8_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_17_1] = mmNIC8_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_17_2] = mmNIC8_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_17_3] = mmNIC8_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_18_0] = mmNIC9_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_18_1] = mmNIC9_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_18_2] = mmNIC9_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_18_3] = mmNIC9_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_19_0] = mmNIC9_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_19_1] = mmNIC9_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_19_2] = mmNIC9_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_19_3] = mmNIC9_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_20_0] = mmNIC10_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_20_1] = mmNIC10_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_20_2] = mmNIC10_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_20_3] = mmNIC10_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_21_0] = mmNIC10_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_21_1] = mmNIC10_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_21_2] = mmNIC10_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_21_3] = mmNIC10_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_22_0] = mmNIC11_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_22_1] = mmNIC11_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_22_2] = mmNIC11_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_22_3] = mmNIC11_QM0_BASE,
 [GAUDI2_QUEUE_ID_NIC_23_0] = mmNIC11_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_23_1] = mmNIC11_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_23_2] = mmNIC11_QM1_BASE,
 [GAUDI2_QUEUE_ID_NIC_23_3] = mmNIC11_QM1_BASE,
 [GAUDI2_QUEUE_ID_ROT_0_0] = mmROT0_QM_BASE,
 [GAUDI2_QUEUE_ID_ROT_0_1] = mmROT0_QM_BASE,
 [GAUDI2_QUEUE_ID_ROT_0_2] = mmROT0_QM_BASE,
 [GAUDI2_QUEUE_ID_ROT_0_3] = mmROT0_QM_BASE,
 [GAUDI2_QUEUE_ID_ROT_1_0] = mmROT1_QM_BASE,
 [GAUDI2_QUEUE_ID_ROT_1_1] = mmROT1_QM_BASE,
 [GAUDI2_QUEUE_ID_ROT_1_2] = mmROT1_QM_BASE,
 [GAUDI2_QUEUE_ID_ROT_1_3] = mmROT1_QM_BASE
};

static const u32 gaudi2_arc_blocks_bases[NUM_ARC_CPUS] = {
 [CPU_ID_SCHED_ARC0] = mmARC_FARM_ARC0_AUX_BASE,
 [CPU_ID_SCHED_ARC1] = mmARC_FARM_ARC1_AUX_BASE,
 [CPU_ID_SCHED_ARC2] = mmARC_FARM_ARC2_AUX_BASE,
 [CPU_ID_SCHED_ARC3] = mmARC_FARM_ARC3_AUX_BASE,
 [CPU_ID_SCHED_ARC4] = mmDCORE1_MME_QM_ARC_AUX_BASE,
 [CPU_ID_SCHED_ARC5] = mmDCORE3_MME_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC0] = mmDCORE0_TPC0_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC1] = mmDCORE0_TPC1_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC2] = mmDCORE0_TPC2_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC3] = mmDCORE0_TPC3_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC4] = mmDCORE0_TPC4_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC5] = mmDCORE0_TPC5_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC6] = mmDCORE1_TPC0_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC7] = mmDCORE1_TPC1_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC8] = mmDCORE1_TPC2_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC9] = mmDCORE1_TPC3_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC10] = mmDCORE1_TPC4_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC11] = mmDCORE1_TPC5_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC12] = mmDCORE2_TPC0_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC13] = mmDCORE2_TPC1_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC14] = mmDCORE2_TPC2_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC15] = mmDCORE2_TPC3_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC16] = mmDCORE2_TPC4_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC17] = mmDCORE2_TPC5_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC18] = mmDCORE3_TPC0_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC19] = mmDCORE3_TPC1_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC20] = mmDCORE3_TPC2_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC21] = mmDCORE3_TPC3_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC22] = mmDCORE3_TPC4_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC23] = mmDCORE3_TPC5_QM_ARC_AUX_BASE,
 [CPU_ID_TPC_QMAN_ARC24] = mmDCORE0_TPC6_QM_ARC_AUX_BASE,
 [CPU_ID_MME_QMAN_ARC0] = mmDCORE0_MME_QM_ARC_AUX_BASE,
 [CPU_ID_MME_QMAN_ARC1] = mmDCORE2_MME_QM_ARC_AUX_BASE,
 [CPU_ID_EDMA_QMAN_ARC0] = mmDCORE0_EDMA0_QM_ARC_AUX_BASE,
 [CPU_ID_EDMA_QMAN_ARC1] = mmDCORE0_EDMA1_QM_ARC_AUX_BASE,
 [CPU_ID_EDMA_QMAN_ARC2] = mmDCORE1_EDMA0_QM_ARC_AUX_BASE,
 [CPU_ID_EDMA_QMAN_ARC3] = mmDCORE1_EDMA1_QM_ARC_AUX_BASE,
 [CPU_ID_EDMA_QMAN_ARC4] = mmDCORE2_EDMA0_QM_ARC_AUX_BASE,
 [CPU_ID_EDMA_QMAN_ARC5] = mmDCORE2_EDMA1_QM_ARC_AUX_BASE,
 [CPU_ID_EDMA_QMAN_ARC6] = mmDCORE3_EDMA0_QM_ARC_AUX_BASE,
 [CPU_ID_EDMA_QMAN_ARC7] = mmDCORE3_EDMA1_QM_ARC_AUX_BASE,
 [CPU_ID_PDMA_QMAN_ARC0] = mmPDMA0_QM_ARC_AUX_BASE,
 [CPU_ID_PDMA_QMAN_ARC1] = mmPDMA1_QM_ARC_AUX_BASE,
 [CPU_ID_ROT_QMAN_ARC0] = mmROT0_QM_ARC_AUX_BASE,
 [CPU_ID_ROT_QMAN_ARC1] = mmROT1_QM_ARC_AUX_BASE,
 [CPU_ID_NIC_QMAN_ARC0] = mmNIC0_QM_ARC_AUX0_BASE,
 [CPU_ID_NIC_QMAN_ARC1] = mmNIC0_QM_ARC_AUX1_BASE,
 [CPU_ID_NIC_QMAN_ARC2] = mmNIC1_QM_ARC_AUX0_BASE,
 [CPU_ID_NIC_QMAN_ARC3] = mmNIC1_QM_ARC_AUX1_BASE,
 [CPU_ID_NIC_QMAN_ARC4] = mmNIC2_QM_ARC_AUX0_BASE,
--> --------------------

--> maximum size reached

--> --------------------