Quelle  gaudi2_security.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0

/*
 * Copyright 2020-2022 HabanaLabs, Ltd.
 * All Rights Reserved.
 */

#include "gaudi2P.h"
#include "../include/gaudi2/asic_reg/gaudi2_regs.h"

#define UNSET_GLBL_SEC_BIT(array, b) ((array)[((b) / 32)] |= (1 << ((b) % 32)))

#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK
#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK
#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK
#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK
#define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK
#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD \
  PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK
#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR \
  PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK
#define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR \
  PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK

/* LBW RR */
#define SFT_NUM_OF_LBW_RTR  1
#define SFT_LBW_RTR_OFFSET  0
#define RR_LBW_LONG_MASK  0x7FFFFFFull
#define RR_LBW_SHORT_MASK  0x7FFF000ull

/* HBW RR */
#define SFT_NUM_OF_HBW_RTR  2
#define RR_HBW_SHORT_LO_MASK  0xFFFFFFFF000ull
#define RR_HBW_SHORT_HI_MASK  0xF00000000000ull
#define RR_HBW_LONG_LO_MASK  0xFFFFFFFF000ull
#define RR_HBW_LONG_HI_MASK  0xFFFFF00000000000ull

struct rr_config {
 u64 min;
 u64 max;
 u32 index;
 u8 type;
};

struct gaudi2_atypical_bp_blocks {
 u32 mm_block_base_addr;
 u32 block_size;
 u32 glbl_sec_offset;
 u32 glbl_sec_length;
};

static const struct gaudi2_atypical_bp_blocks gaudi2_pb_dcr0_sm_objs = {
 mmDCORE0_SYNC_MNGR_OBJS_BASE,
 128 * 1024,
 SM_OBJS_PROT_BITS_OFFS,
 640
};

static const u32 gaudi2_pb_sft0[] = {
 mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE,
 mmSFT0_HBW_RTR_IF0_RTR_H3_BASE,
 mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,
 mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE,
 mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE,
 mmSFT0_HBW_RTR_IF1_RTR_H3_BASE,
 mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE,
 mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE,
 mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE,
 mmSFT0_LBW_RTR_IF_RTR_H3_BASE,
 mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE,
 mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE,
 mmSFT0_BASE,
};

static const u32 gaudi2_pb_dcr0_hif[] = {
 mmDCORE0_HIF0_BASE,
};

static const u32 gaudi2_pb_dcr0_rtr0[] = {
 mmDCORE0_RTR0_CTRL_BASE,
 mmDCORE0_RTR0_H3_BASE,
 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE,
 mmDCORE0_RTR0_ADD_DEC_HBW_BASE,
 mmDCORE0_RTR0_BASE,
 mmDCORE0_RTR0_DBG_ADDR_BASE,
};

static const u32 gaudi2_pb_dcr0_hmmu0[] = {
 mmDCORE0_HMMU0_MMU_BASE,
 mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE,
 mmDCORE0_HMMU0_SCRAMB_OUT_BASE,
 mmDCORE0_HMMU0_STLB_BASE,
};

static const u32 gaudi2_pb_cpu_if[] = {
 mmCPU_IF_BASE,
};

static const u32 gaudi2_pb_cpu[] = {
 mmCPU_CA53_CFG_BASE,
 mmCPU_MSTR_IF_RR_SHRD_HBW_BASE,
};

static const u32 gaudi2_pb_kdma[] = {
 mmARC_FARM_KDMA_BASE,
 mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE,
};

static const u32 gaudi2_pb_pdma0[] = {
 mmPDMA0_CORE_BASE,
 mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
 mmPDMA0_QM_BASE,
};

static const u32 gaudi2_pb_pdma0_arc[] = {
 mmPDMA0_QM_ARC_AUX_BASE,
};

static const struct range gaudi2_pb_pdma0_arc_unsecured_regs[] = {
 {mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK},
 {mmPDMA0_QM_ARC_AUX_CLUSTER_NUM, mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
 {mmPDMA0_QM_ARC_AUX_ARC_RST_REQ, mmPDMA0_QM_ARC_AUX_CID_OFFSET_7},
 {mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
 {mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
 {mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
 {mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
 {mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
 {mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
};

static const u32 gaudi2_pb_pdma0_unsecured_regs[] = {
 mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,
 mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI,
 mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO,
 mmPDMA0_CORE_CTX_WR_COMP_WDATA,
 mmPDMA0_CORE_CTX_SRC_BASE_LO,
 mmPDMA0_CORE_CTX_SRC_BASE_HI,
 mmPDMA0_CORE_CTX_DST_BASE_LO,
 mmPDMA0_CORE_CTX_DST_BASE_HI,
 mmPDMA0_CORE_CTX_SRC_TSIZE_0,
 mmPDMA0_CORE_CTX_SRC_TSIZE_1,
 mmPDMA0_CORE_CTX_SRC_TSIZE_2,
 mmPDMA0_CORE_CTX_SRC_TSIZE_3,
 mmPDMA0_CORE_CTX_SRC_TSIZE_4,
 mmPDMA0_CORE_CTX_SRC_STRIDE_1,
 mmPDMA0_CORE_CTX_SRC_STRIDE_2,
 mmPDMA0_CORE_CTX_SRC_STRIDE_3,
 mmPDMA0_CORE_CTX_SRC_STRIDE_4,
 mmPDMA0_CORE_CTX_SRC_OFFSET_LO,
 mmPDMA0_CORE_CTX_SRC_OFFSET_HI,
 mmPDMA0_CORE_CTX_DST_TSIZE_0,
 mmPDMA0_CORE_CTX_DST_TSIZE_1,
 mmPDMA0_CORE_CTX_DST_TSIZE_2,
 mmPDMA0_CORE_CTX_DST_TSIZE_3,
 mmPDMA0_CORE_CTX_DST_TSIZE_4,
 mmPDMA0_CORE_CTX_DST_STRIDE_1,
 mmPDMA0_CORE_CTX_DST_STRIDE_2,
 mmPDMA0_CORE_CTX_DST_STRIDE_3,
 mmPDMA0_CORE_CTX_DST_STRIDE_4,
 mmPDMA0_CORE_CTX_DST_OFFSET_LO,
 mmPDMA0_CORE_CTX_DST_OFFSET_HI,
 mmPDMA0_CORE_CTX_COMMIT,
 mmPDMA0_CORE_CTX_CTRL,
 mmPDMA0_CORE_CTX_TE_NUMROWS,
 mmPDMA0_CORE_CTX_IDX,
 mmPDMA0_CORE_CTX_IDX_INC,
 mmPDMA0_QM_CQ_CFG0_0,
 mmPDMA0_QM_CQ_CFG0_1,
 mmPDMA0_QM_CQ_CFG0_2,
 mmPDMA0_QM_CQ_CFG0_3,
 mmPDMA0_QM_CQ_CFG0_4,
 mmPDMA0_QM_CP_FENCE0_RDATA_0,
 mmPDMA0_QM_CP_FENCE0_RDATA_1,
 mmPDMA0_QM_CP_FENCE0_RDATA_2,
 mmPDMA0_QM_CP_FENCE0_RDATA_3,
 mmPDMA0_QM_CP_FENCE0_RDATA_4,
 mmPDMA0_QM_CP_FENCE1_RDATA_0,
 mmPDMA0_QM_CP_FENCE1_RDATA_1,
 mmPDMA0_QM_CP_FENCE1_RDATA_2,
 mmPDMA0_QM_CP_FENCE1_RDATA_3,
 mmPDMA0_QM_CP_FENCE1_RDATA_4,
 mmPDMA0_QM_CP_FENCE2_RDATA_0,
 mmPDMA0_QM_CP_FENCE2_RDATA_1,
 mmPDMA0_QM_CP_FENCE2_RDATA_2,
 mmPDMA0_QM_CP_FENCE2_RDATA_3,
 mmPDMA0_QM_CP_FENCE2_RDATA_4,
 mmPDMA0_QM_CP_FENCE3_RDATA_0,
 mmPDMA0_QM_CP_FENCE3_RDATA_1,
 mmPDMA0_QM_CP_FENCE3_RDATA_2,
 mmPDMA0_QM_CP_FENCE3_RDATA_3,
 mmPDMA0_QM_CP_FENCE3_RDATA_4,
 mmPDMA0_QM_CP_FENCE0_CNT_0,
 mmPDMA0_QM_CP_FENCE0_CNT_1,
 mmPDMA0_QM_CP_FENCE0_CNT_2,
 mmPDMA0_QM_CP_FENCE0_CNT_3,
 mmPDMA0_QM_CP_FENCE0_CNT_4,
 mmPDMA0_QM_CP_FENCE1_CNT_0,
 mmPDMA0_QM_CP_FENCE1_CNT_1,
 mmPDMA0_QM_CP_FENCE1_CNT_2,
 mmPDMA0_QM_CP_FENCE1_CNT_3,
 mmPDMA0_QM_CP_FENCE1_CNT_4,
 mmPDMA0_QM_CP_FENCE2_CNT_0,
 mmPDMA0_QM_CP_FENCE2_CNT_1,
 mmPDMA0_QM_CP_FENCE2_CNT_2,
 mmPDMA0_QM_CP_FENCE2_CNT_3,
 mmPDMA0_QM_CP_FENCE2_CNT_4,
 mmPDMA0_QM_CP_FENCE3_CNT_0,
 mmPDMA0_QM_CP_FENCE3_CNT_1,
 mmPDMA0_QM_CP_FENCE3_CNT_2,
 mmPDMA0_QM_CP_FENCE3_CNT_3,
 mmPDMA0_QM_CP_FENCE3_CNT_4,
 mmPDMA0_QM_CQ_PTR_LO_0,
 mmPDMA0_QM_CQ_PTR_HI_0,
 mmPDMA0_QM_CQ_TSIZE_0,
 mmPDMA0_QM_CQ_CTL_0,
 mmPDMA0_QM_CQ_PTR_LO_1,
 mmPDMA0_QM_CQ_PTR_HI_1,
 mmPDMA0_QM_CQ_TSIZE_1,
 mmPDMA0_QM_CQ_CTL_1,
 mmPDMA0_QM_CQ_PTR_LO_2,
 mmPDMA0_QM_CQ_PTR_HI_2,
 mmPDMA0_QM_CQ_TSIZE_2,
 mmPDMA0_QM_CQ_CTL_2,
 mmPDMA0_QM_CQ_PTR_LO_3,
 mmPDMA0_QM_CQ_PTR_HI_3,
 mmPDMA0_QM_CQ_TSIZE_3,
 mmPDMA0_QM_CQ_CTL_3,
 mmPDMA0_QM_CQ_PTR_LO_4,
 mmPDMA0_QM_CQ_PTR_HI_4,
 mmPDMA0_QM_CQ_TSIZE_4,
 mmPDMA0_QM_CQ_CTL_4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,
 mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
 mmPDMA0_QM_ARC_CQ_PTR_LO,
 mmPDMA0_QM_ARC_CQ_PTR_LO_STS,
 mmPDMA0_QM_ARC_CQ_PTR_HI,
 mmPDMA0_QM_ARC_CQ_PTR_HI_STS,
 mmPDMA0_QM_ARB_CFG_0,
 mmPDMA0_QM_ARB_MST_QUIET_PER,
 mmPDMA0_QM_ARB_CHOICE_Q_PUSH,
 mmPDMA0_QM_ARB_WRR_WEIGHT_0,
 mmPDMA0_QM_ARB_WRR_WEIGHT_1,
 mmPDMA0_QM_ARB_WRR_WEIGHT_2,
 mmPDMA0_QM_ARB_WRR_WEIGHT_3,
 mmPDMA0_QM_ARB_BASE_LO,
 mmPDMA0_QM_ARB_BASE_HI,
 mmPDMA0_QM_ARB_MST_SLAVE_EN,
 mmPDMA0_QM_ARB_MST_SLAVE_EN_1,
 mmPDMA0_QM_ARB_MST_CRED_INC,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
 mmPDMA0_QM_ARB_SLV_ID,
 mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
 mmPDMA0_QM_ARC_CQ_CFG0,
 mmPDMA0_QM_CQ_IFIFO_CI_0,
 mmPDMA0_QM_CQ_IFIFO_CI_1,
 mmPDMA0_QM_CQ_IFIFO_CI_2,
 mmPDMA0_QM_CQ_IFIFO_CI_3,
 mmPDMA0_QM_CQ_IFIFO_CI_4,
 mmPDMA0_QM_ARC_CQ_IFIFO_CI,
 mmPDMA0_QM_CQ_CTL_CI_0,
 mmPDMA0_QM_CQ_CTL_CI_1,
 mmPDMA0_QM_CQ_CTL_CI_2,
 mmPDMA0_QM_CQ_CTL_CI_3,
 mmPDMA0_QM_CQ_CTL_CI_4,
 mmPDMA0_QM_ARC_CQ_CTL_CI,
 mmPDMA0_QM_ARC_CQ_TSIZE,
 mmPDMA0_QM_ARC_CQ_CTL,
 mmPDMA0_QM_CP_SWITCH_WD_SET,
 mmPDMA0_QM_CP_EXT_SWITCH,
 mmPDMA0_QM_CP_PRED_0,
 mmPDMA0_QM_CP_PRED_1,
 mmPDMA0_QM_CP_PRED_2,
 mmPDMA0_QM_CP_PRED_3,
 mmPDMA0_QM_CP_PRED_4,
 mmPDMA0_QM_CP_PRED_UPEN_0,
 mmPDMA0_QM_CP_PRED_UPEN_1,
 mmPDMA0_QM_CP_PRED_UPEN_2,
 mmPDMA0_QM_CP_PRED_UPEN_3,
 mmPDMA0_QM_CP_PRED_UPEN_4,
 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,
 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,
 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,
 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,
 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,
 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,
 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,
 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,
 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,
 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,
 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,
 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,
 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,
 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,
 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,
 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,
 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,
 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,
 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,
 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,
 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,
 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,
 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,
 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,
 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,
 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,
 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,
 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,
 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,
 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,
 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,
 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,
 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,
 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,
 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,
 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,
 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,
 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,
 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,
 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,
 mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
 mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,
 mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO,
 mmPDMA0_QM_CQ_CTL_MSG_BASE_LO
};

static const u32 gaudi2_pb_dcr0_edma0[] = {
 mmDCORE0_EDMA0_CORE_BASE,
 mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
 mmDCORE0_EDMA0_QM_BASE,
};

static const u32 gaudi2_pb_dcr0_edma0_arc[] = {
 mmDCORE0_EDMA0_QM_ARC_AUX_BASE,
};

static const struct range gaudi2_pb_dcr0_edma0_arc_unsecured_regs[] = {
 {mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK},
 {mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
 {mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7},
 {mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
 {mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN,
  mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
 {mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN,
  mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
 {mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
  mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
 {mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
  mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
 {mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
  mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
};

static const u32 gaudi2_pb_dcr0_edma0_unsecured_regs[] = {
 mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,
 mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI,
 mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO,
 mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA,
 mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO,
 mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI,
 mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO,
 mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI,
 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0,
 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1,
 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2,
 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3,
 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4,
 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1,
 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2,
 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3,
 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4,
 mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO,
 mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI,
 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0,
 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1,
 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2,
 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3,
 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4,
 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1,
 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2,
 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3,
 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4,
 mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO,
 mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI,
 mmDCORE0_EDMA0_CORE_CTX_COMMIT,
 mmDCORE0_EDMA0_CORE_CTX_CTRL,
 mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS,
 mmDCORE0_EDMA0_CORE_CTX_IDX,
 mmDCORE0_EDMA0_CORE_CTX_IDX_INC,
 mmDCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND,
 mmDCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG,
 mmDCORE0_EDMA0_QM_CQ_CFG0_0,
 mmDCORE0_EDMA0_QM_CQ_CFG0_1,
 mmDCORE0_EDMA0_QM_CQ_CFG0_2,
 mmDCORE0_EDMA0_QM_CQ_CFG0_3,
 mmDCORE0_EDMA0_QM_CQ_CFG0_4,
 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0,
 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1,
 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2,
 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3,
 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4,
 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0,
 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1,
 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2,
 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3,
 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4,
 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0,
 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1,
 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2,
 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3,
 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4,
 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0,
 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1,
 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2,
 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3,
 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4,
 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0,
 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1,
 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2,
 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3,
 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4,
 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0,
 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1,
 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2,
 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3,
 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4,
 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0,
 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1,
 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2,
 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3,
 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4,
 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0,
 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1,
 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2,
 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3,
 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4,
 mmDCORE0_EDMA0_QM_CQ_PTR_LO_0,
 mmDCORE0_EDMA0_QM_CQ_PTR_HI_0,
 mmDCORE0_EDMA0_QM_CQ_TSIZE_0,
 mmDCORE0_EDMA0_QM_CQ_CTL_0,
 mmDCORE0_EDMA0_QM_CQ_PTR_LO_1,
 mmDCORE0_EDMA0_QM_CQ_PTR_HI_1,
 mmDCORE0_EDMA0_QM_CQ_TSIZE_1,
 mmDCORE0_EDMA0_QM_CQ_CTL_1,
 mmDCORE0_EDMA0_QM_CQ_PTR_LO_2,
 mmDCORE0_EDMA0_QM_CQ_PTR_HI_2,
 mmDCORE0_EDMA0_QM_CQ_TSIZE_2,
 mmDCORE0_EDMA0_QM_CQ_CTL_2,
 mmDCORE0_EDMA0_QM_CQ_PTR_LO_3,
 mmDCORE0_EDMA0_QM_CQ_PTR_HI_3,
 mmDCORE0_EDMA0_QM_CQ_TSIZE_3,
 mmDCORE0_EDMA0_QM_CQ_CTL_3,
 mmDCORE0_EDMA0_QM_CQ_PTR_LO_4,
 mmDCORE0_EDMA0_QM_CQ_PTR_HI_4,
 mmDCORE0_EDMA0_QM_CQ_TSIZE_4,
 mmDCORE0_EDMA0_QM_CQ_CTL_4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,
 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO,
 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS,
 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI,
 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS,
 mmDCORE0_EDMA0_QM_ARB_CFG_0,
 mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER,
 mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH,
 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0,
 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1,
 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2,
 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3,
 mmDCORE0_EDMA0_QM_ARB_BASE_LO,
 mmDCORE0_EDMA0_QM_ARB_BASE_HI,
 mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN,
 mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1,
 mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
 mmDCORE0_EDMA0_QM_ARB_SLV_ID,
 mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
 mmDCORE0_EDMA0_QM_ARC_CQ_CFG0,
 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0,
 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1,
 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2,
 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3,
 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4,
 mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI,
 mmDCORE0_EDMA0_QM_CQ_CTL_CI_0,
 mmDCORE0_EDMA0_QM_CQ_CTL_CI_1,
 mmDCORE0_EDMA0_QM_CQ_CTL_CI_2,
 mmDCORE0_EDMA0_QM_CQ_CTL_CI_3,
 mmDCORE0_EDMA0_QM_CQ_CTL_CI_4,
 mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI,
 mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE,
 mmDCORE0_EDMA0_QM_ARC_CQ_CTL,
 mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET,
 mmDCORE0_EDMA0_QM_CP_EXT_SWITCH,
 mmDCORE0_EDMA0_QM_CP_PRED_0,
 mmDCORE0_EDMA0_QM_CP_PRED_1,
 mmDCORE0_EDMA0_QM_CP_PRED_2,
 mmDCORE0_EDMA0_QM_CP_PRED_3,
 mmDCORE0_EDMA0_QM_CP_PRED_4,
 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0,
 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1,
 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2,
 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3,
 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,
 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,
 mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
 mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,
 mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO,
 mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO
};

static const u32 gaudi2_pb_dcr0_mme_sbte[] = {
 mmDCORE0_MME_SBTE0_BASE,
 mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE,
};

static const u32 gaudi2_pb_dcr0_mme_qm[] = {
 mmDCORE0_MME_QM_BASE,
};

static const u32 gaudi2_pb_dcr0_mme_eng[] = {
 mmDCORE0_MME_ACC_BASE,
 mmDCORE0_MME_CTRL_HI_BASE,
 mmDCORE0_MME_CTRL_LO_BASE,
 mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE,
 mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE,
 mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE,
};

static const u32 gaudi2_pb_dcr0_mme_arc[] = {
 mmDCORE0_MME_QM_ARC_AUX_BASE,
 mmDCORE0_MME_QM_ARC_DUP_ENG_BASE,
};

static const struct range gaudi2_pb_dcr0_mme_arc_unsecured_regs[] = {
 {mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK},
 {mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT},
 {mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7},
 {mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
 {mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
 {mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
 {mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
  mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
 {mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
  mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
 {mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
  mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
 {mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0,
  mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63},
 {mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER,
  mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD},
};

static const u32 gaudi2_pb_dcr0_mme_qm_unsecured_regs[] = {
 mmDCORE0_MME_QM_CQ_CFG0_0,
 mmDCORE0_MME_QM_CQ_CFG0_1,
 mmDCORE0_MME_QM_CQ_CFG0_2,
 mmDCORE0_MME_QM_CQ_CFG0_3,
 mmDCORE0_MME_QM_CQ_CFG0_4,
 mmDCORE0_MME_QM_CP_FENCE0_RDATA_0,
 mmDCORE0_MME_QM_CP_FENCE0_RDATA_1,
 mmDCORE0_MME_QM_CP_FENCE0_RDATA_2,
 mmDCORE0_MME_QM_CP_FENCE0_RDATA_3,
 mmDCORE0_MME_QM_CP_FENCE0_RDATA_4,
 mmDCORE0_MME_QM_CP_FENCE1_RDATA_0,
 mmDCORE0_MME_QM_CP_FENCE1_RDATA_1,
 mmDCORE0_MME_QM_CP_FENCE1_RDATA_2,
 mmDCORE0_MME_QM_CP_FENCE1_RDATA_3,
 mmDCORE0_MME_QM_CP_FENCE1_RDATA_4,
 mmDCORE0_MME_QM_CP_FENCE2_RDATA_0,
 mmDCORE0_MME_QM_CP_FENCE2_RDATA_1,
 mmDCORE0_MME_QM_CP_FENCE2_RDATA_2,
 mmDCORE0_MME_QM_CP_FENCE2_RDATA_3,
 mmDCORE0_MME_QM_CP_FENCE2_RDATA_4,
 mmDCORE0_MME_QM_CP_FENCE3_RDATA_0,
 mmDCORE0_MME_QM_CP_FENCE3_RDATA_1,
 mmDCORE0_MME_QM_CP_FENCE3_RDATA_2,
 mmDCORE0_MME_QM_CP_FENCE3_RDATA_3,
 mmDCORE0_MME_QM_CP_FENCE3_RDATA_4,
 mmDCORE0_MME_QM_CP_FENCE0_CNT_0,
 mmDCORE0_MME_QM_CP_FENCE0_CNT_1,
 mmDCORE0_MME_QM_CP_FENCE0_CNT_2,
 mmDCORE0_MME_QM_CP_FENCE0_CNT_3,
 mmDCORE0_MME_QM_CP_FENCE0_CNT_4,
 mmDCORE0_MME_QM_CP_FENCE1_CNT_0,
 mmDCORE0_MME_QM_CP_FENCE1_CNT_1,
 mmDCORE0_MME_QM_CP_FENCE1_CNT_2,
 mmDCORE0_MME_QM_CP_FENCE1_CNT_3,
 mmDCORE0_MME_QM_CP_FENCE1_CNT_4,
 mmDCORE0_MME_QM_CP_FENCE2_CNT_0,
 mmDCORE0_MME_QM_CP_FENCE2_CNT_1,
 mmDCORE0_MME_QM_CP_FENCE2_CNT_2,
 mmDCORE0_MME_QM_CP_FENCE2_CNT_3,
 mmDCORE0_MME_QM_CP_FENCE2_CNT_4,
 mmDCORE0_MME_QM_CP_FENCE3_CNT_0,
 mmDCORE0_MME_QM_CP_FENCE3_CNT_1,
 mmDCORE0_MME_QM_CP_FENCE3_CNT_2,
 mmDCORE0_MME_QM_CP_FENCE3_CNT_3,
 mmDCORE0_MME_QM_CP_FENCE3_CNT_4,
 mmDCORE0_MME_QM_CQ_PTR_LO_0,
 mmDCORE0_MME_QM_CQ_PTR_HI_0,
 mmDCORE0_MME_QM_CQ_TSIZE_0,
 mmDCORE0_MME_QM_CQ_CTL_0,
 mmDCORE0_MME_QM_CQ_PTR_LO_1,
 mmDCORE0_MME_QM_CQ_PTR_HI_1,
 mmDCORE0_MME_QM_CQ_TSIZE_1,
 mmDCORE0_MME_QM_CQ_CTL_1,
 mmDCORE0_MME_QM_CQ_PTR_LO_2,
 mmDCORE0_MME_QM_CQ_PTR_HI_2,
 mmDCORE0_MME_QM_CQ_TSIZE_2,
 mmDCORE0_MME_QM_CQ_CTL_2,
 mmDCORE0_MME_QM_CQ_PTR_LO_3,
 mmDCORE0_MME_QM_CQ_PTR_HI_3,
 mmDCORE0_MME_QM_CQ_TSIZE_3,
 mmDCORE0_MME_QM_CQ_CTL_3,
 mmDCORE0_MME_QM_CQ_PTR_LO_4,
 mmDCORE0_MME_QM_CQ_PTR_HI_4,
 mmDCORE0_MME_QM_CQ_TSIZE_4,
 mmDCORE0_MME_QM_CQ_CTL_4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE,
 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
 mmDCORE0_MME_QM_ARC_CQ_PTR_LO,
 mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS,
 mmDCORE0_MME_QM_ARC_CQ_PTR_HI,
 mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS,
 mmDCORE0_MME_QM_ARB_CFG_0,
 mmDCORE0_MME_QM_ARB_MST_QUIET_PER,
 mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH,
 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0,
 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1,
 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2,
 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3,
 mmDCORE0_MME_QM_ARB_BASE_LO,
 mmDCORE0_MME_QM_ARB_BASE_HI,
 mmDCORE0_MME_QM_ARB_MST_SLAVE_EN,
 mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1,
 mmDCORE0_MME_QM_ARB_MST_CRED_INC,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62,
 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63,
 mmDCORE0_MME_QM_ARB_SLV_ID,
 mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST,
 mmDCORE0_MME_QM_ARC_CQ_CFG0,
 mmDCORE0_MME_QM_CQ_IFIFO_CI_0,
 mmDCORE0_MME_QM_CQ_IFIFO_CI_1,
 mmDCORE0_MME_QM_CQ_IFIFO_CI_2,
 mmDCORE0_MME_QM_CQ_IFIFO_CI_3,
 mmDCORE0_MME_QM_CQ_IFIFO_CI_4,
 mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI,
 mmDCORE0_MME_QM_CQ_CTL_CI_0,
 mmDCORE0_MME_QM_CQ_CTL_CI_1,
 mmDCORE0_MME_QM_CQ_CTL_CI_2,
 mmDCORE0_MME_QM_CQ_CTL_CI_3,
 mmDCORE0_MME_QM_CQ_CTL_CI_4,
 mmDCORE0_MME_QM_ARC_CQ_CTL_CI,
 mmDCORE0_MME_QM_ARC_CQ_TSIZE,
 mmDCORE0_MME_QM_ARC_CQ_CTL,
 mmDCORE0_MME_QM_CP_SWITCH_WD_SET,
 mmDCORE0_MME_QM_CP_EXT_SWITCH,
 mmDCORE0_MME_QM_CP_PRED_0,
 mmDCORE0_MME_QM_CP_PRED_1,
 mmDCORE0_MME_QM_CP_PRED_2,
 mmDCORE0_MME_QM_CP_PRED_3,
 mmDCORE0_MME_QM_CP_PRED_4,
 mmDCORE0_MME_QM_CP_PRED_UPEN_0,
 mmDCORE0_MME_QM_CP_PRED_UPEN_1,
 mmDCORE0_MME_QM_CP_PRED_UPEN_2,
 mmDCORE0_MME_QM_CP_PRED_UPEN_3,
 mmDCORE0_MME_QM_CP_PRED_UPEN_4,
 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0,
 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1,
 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2,
 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3,
 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4,
 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0,
 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1,
 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2,
 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3,
 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4,
 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0,
 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1,
 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2,
 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3,
 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4,
 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0,
 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1,
 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2,
 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3,
 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4,
 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0,
 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1,
 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2,
 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3,
 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4,
 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0,
 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1,
 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2,
 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3,
 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4,
 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0,
 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1,
 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2,
 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3,
 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4,
 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0,
 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1,
 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2,
 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3,
 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4,
 mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
 mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO,
 mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO,
 mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO
};

static const u32 gaudi2_pb_dcr0_mme_eng_unsecured_regs[] = {
 mmDCORE0_MME_CTRL_LO_CMD,
 mmDCORE0_MME_CTRL_LO_AGU,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW,
 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH,
 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW,
 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH,
 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW,
 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH,
 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW,
 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH,
 mmDCORE0_MME_CTRL_LO_ARCH_STATUS,
 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0,
 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0,
 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0,
 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1,
 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1,
 mmDCORE0_MME_CTRL_LO_ARCH_A_SS,
 mmDCORE0_MME_CTRL_LO_ARCH_B_SS,
 mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3,
 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4,
 mmDCORE0_MME_ACC_AP_LFSR_POLY,
 mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA,
 mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL,
 mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA,
 mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY,
 mmDCORE0_MME_ACC_WBC_SRC_BP,
};

static const u32 gaudi2_pb_dcr0_tpc0[] = {
 mmDCORE0_TPC0_QM_BASE,
 mmDCORE0_TPC0_CFG_BASE,
 mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE,
};

static const u32 gaudi2_pb_dcr0_tpc0_arc[] = {
 mmDCORE0_TPC0_QM_ARC_AUX_BASE,
};

static const struct range gaudi2_pb_dcr0_tpc0_arc_unsecured_regs[] = {
 {mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK},
 {mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT},
 {mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7},
 {mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
 {mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
 {mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
 {mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
  mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
 {mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
  mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
 {mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
  mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
};

static const u32 gaudi2_pb_dcr0_tpc0_unsecured_regs[] = {
 mmDCORE0_TPC0_QM_CQ_CFG0_0,
 mmDCORE0_TPC0_QM_CQ_CFG0_1,
 mmDCORE0_TPC0_QM_CQ_CFG0_2,
 mmDCORE0_TPC0_QM_CQ_CFG0_3,
 mmDCORE0_TPC0_QM_CQ_CFG0_4,
 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0,
 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1,
 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2,
 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3,
 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4,
 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0,
 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1,
 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2,
 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3,
 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4,
 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0,
 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1,
 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2,
 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3,
 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4,
 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0,
 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1,
 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2,
 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3,
 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4,
 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0,
 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1,
 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2,
 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3,
 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4,
 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0,
 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1,
 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2,
 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3,
 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4,
 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0,
 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1,
 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2,
 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3,
 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4,
 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0,
 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1,
 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2,
 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3,
 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4,
 mmDCORE0_TPC0_QM_CQ_PTR_LO_0,
 mmDCORE0_TPC0_QM_CQ_PTR_HI_0,
 mmDCORE0_TPC0_QM_CQ_TSIZE_0,
 mmDCORE0_TPC0_QM_CQ_CTL_0,
 mmDCORE0_TPC0_QM_CQ_PTR_LO_1,
 mmDCORE0_TPC0_QM_CQ_PTR_HI_1,
 mmDCORE0_TPC0_QM_CQ_TSIZE_1,
 mmDCORE0_TPC0_QM_CQ_CTL_1,
 mmDCORE0_TPC0_QM_CQ_PTR_LO_2,
 mmDCORE0_TPC0_QM_CQ_PTR_HI_2,
 mmDCORE0_TPC0_QM_CQ_TSIZE_2,
 mmDCORE0_TPC0_QM_CQ_CTL_2,
 mmDCORE0_TPC0_QM_CQ_PTR_LO_3,
 mmDCORE0_TPC0_QM_CQ_PTR_HI_3,
 mmDCORE0_TPC0_QM_CQ_TSIZE_3,
 mmDCORE0_TPC0_QM_CQ_CTL_3,
 mmDCORE0_TPC0_QM_CQ_PTR_LO_4,
 mmDCORE0_TPC0_QM_CQ_PTR_HI_4,
 mmDCORE0_TPC0_QM_CQ_TSIZE_4,
 mmDCORE0_TPC0_QM_CQ_CTL_4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE,
 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
 mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO,
 mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS,
 mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI,
 mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS,
 mmDCORE0_TPC0_QM_ARB_CFG_0,
 mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER,
 mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH,
 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0,
 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1,
 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2,
 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3,
 mmDCORE0_TPC0_QM_ARB_BASE_LO,
 mmDCORE0_TPC0_QM_ARB_BASE_HI,
 mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN,
 mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1,
 mmDCORE0_TPC0_QM_ARB_MST_CRED_INC,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
 mmDCORE0_TPC0_QM_ARB_SLV_ID,
 mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
 mmDCORE0_TPC0_QM_ARC_CQ_CFG0,
 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0,
 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1,
 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2,
 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3,
 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4,
 mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI,
 mmDCORE0_TPC0_QM_CQ_CTL_CI_0,
 mmDCORE0_TPC0_QM_CQ_CTL_CI_1,
 mmDCORE0_TPC0_QM_CQ_CTL_CI_2,
 mmDCORE0_TPC0_QM_CQ_CTL_CI_3,
 mmDCORE0_TPC0_QM_CQ_CTL_CI_4,
 mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI,
 mmDCORE0_TPC0_QM_ARC_CQ_TSIZE,
 mmDCORE0_TPC0_QM_ARC_CQ_CTL,
 mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET,
 mmDCORE0_TPC0_QM_CP_EXT_SWITCH,
 mmDCORE0_TPC0_QM_CP_PRED_0,
 mmDCORE0_TPC0_QM_CP_PRED_1,
 mmDCORE0_TPC0_QM_CP_PRED_2,
 mmDCORE0_TPC0_QM_CP_PRED_3,
 mmDCORE0_TPC0_QM_CP_PRED_4,
 mmDCORE0_TPC0_QM_CP_PRED_UPEN_0,
 mmDCORE0_TPC0_QM_CP_PRED_UPEN_1,
 mmDCORE0_TPC0_QM_CP_PRED_UPEN_2,
 mmDCORE0_TPC0_QM_CP_PRED_UPEN_3,
 mmDCORE0_TPC0_QM_CP_PRED_UPEN_4,
 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0,
 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1,
 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2,
 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3,
 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4,
 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0,
 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1,
 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2,
 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3,
 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4,
 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0,
 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1,
 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2,
 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3,
 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4,
 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0,
 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1,
 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2,
 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3,
 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4,
 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0,
 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1,
 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2,
 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3,
 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4,
 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0,
 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1,
 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2,
 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3,
 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4,
 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0,
 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1,
 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2,
 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3,
 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4,
 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0,
 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1,
 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2,
 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3,
 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4,
 mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
 mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO,
 mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO,
 mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO,
 mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE,
 mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR,
 mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW,
 mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH,
 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0,
 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0,
 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1,
 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1,
 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2,
 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2,
 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3,
 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3,
 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4,
 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4,
 mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG,
 mmDCORE0_TPC0_CFG_QM_KERNEL_ID,
 mmDCORE0_TPC0_CFG_QM_POWER_LOOP,
 mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_0,
 mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_1,
 mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_2,
 mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_3,
 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO,
 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI,
 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO,
 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI,
 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO,
 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI,
 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO,
 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI,
 mmDCORE0_TPC0_CFG_FP8_143_BIAS,
 mmDCORE0_TPC0_CFG_ROUND_CSR,
 mmDCORE0_TPC0_CFG_CONV_ROUND_CSR,
 mmDCORE0_TPC0_CFG_SEMAPHORE,
 mmDCORE0_TPC0_CFG_LFSR_POLYNOM,
 mmDCORE0_TPC0_CFG_STATUS,
 mmDCORE0_TPC0_CFG_TPC_CMD,
 mmDCORE0_TPC0_CFG_TPC_EXECUTE,
 mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD,
 mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW,
 mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH,
 mmDCORE0_TPC0_CFG_RD_RATE_LIMIT,
 mmDCORE0_TPC0_CFG_WR_RATE_LIMIT,
 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO,
 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI,
 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO,
 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI,
 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO,
 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI,
 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO,
 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI,
 mmDCORE0_TPC0_CFG_KERNEL_KERNEL_CONFIG,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_0,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_1,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_2,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_3,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_4,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_5,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_6,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_7,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_8,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_9,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_10,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_11,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_12,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_13,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_14,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_15,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_16,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_17,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_18,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_19,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_20,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_21,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_22,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_23,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_24,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_25,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_26,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_27,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_28,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_29,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_30,
 mmDCORE0_TPC0_CFG_KERNEL_SRF_31,
 mmDCORE0_TPC0_CFG_TPC_SB_L0CD,
 mmDCORE0_TPC0_CFG_TPC_COUNT,
 mmDCORE0_TPC0_CFG_TPC_ID,
 mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC,
 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0,
 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1,
 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2,
 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3,
 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4,
 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0,
 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1,
 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2,
 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3
};

static const u32 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs[] = {
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,
 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,
};

--> --------------------

--> maximum size reached

--> --------------------