status = i2c_nuvoton_read_buf(client, TPM_STS, 1, &data); if (status <= 0) {
dev_err(&chip->dev, "%s() error return %d\n", __func__,
status);
data = TPM_STS_ERR_VAL;
}
return data;
}
/* write byte to TPM_STS register */ static s32 i2c_nuvoton_write_status(struct i2c_client *client, u8 data)
{
s32 status; int i;
/* this causes the current command to be aborted */ for (i = 0, status = -1; i < TPM_I2C_RETRY_COUNT && status < 0; i++) {
status = i2c_nuvoton_write_buf(client, TPM_STS, 1, &data); if (status < 0)
usleep_range(TPM_I2C_BUS_DELAY, TPM_I2C_BUS_DELAY
+ TPM_I2C_DELAY_RANGE);
} return status;
}
/* this causes the current command to be aborted */
status = i2c_nuvoton_write_status(client, TPM_STS_COMMAND_READY); if (status < 0)
dev_err(&chip->dev, "%s() fail to write TPM_STS.commandReady\n", __func__);
}
/* read burstCount field from TPM_STS register
* return -1 on fail to read */ staticint i2c_nuvoton_get_burstcount(struct i2c_client *client, struct tpm_chip *chip)
{ unsignedlong stop = jiffies + chip->timeout_d;
s32 status; int burst_count = -1;
u8 data;
/* wait for burstcount to be non-zero */ do { /* in I2C burstCount is 1 byte */
status = i2c_nuvoton_read_buf(client, TPM_BURST_COUNT, 1,
&data); if (status > 0 && data > 0) {
burst_count = min_t(u8, TPM_I2C_MAX_BUF_SIZE, data); break;
}
usleep_range(TPM_I2C_BUS_DELAY, TPM_I2C_BUS_DELAY
+ TPM_I2C_DELAY_RANGE);
} while (time_before(jiffies, stop));
return burst_count;
}
/* * WPCT301/NPCT501/NPCT6XX SINT# supports only dataAvail * any call to this function which is not waiting for dataAvail will * set queue to NULL to avoid waiting for interrupt
*/ staticbool i2c_nuvoton_check_status(struct tpm_chip *chip, u8 mask, u8 value)
{
u8 status = i2c_nuvoton_read_status(chip); return (status != TPM_STS_ERR_VAL) && ((status & mask) == value);
}
enable_irq(priv->irq);
rc = wait_event_interruptible_timeout(*queue,
cur_intrs != priv->intrs,
timeout); if (rc > 0) return 0; /* At this point we know that the SINT pin is asserted, so we
* do not need to do i2c_nuvoton_check_status */
} else { unsignedlong ten_msec, stop; bool status_valid;
/* check current status */
status_valid = i2c_nuvoton_check_status(chip, mask, value); if (status_valid) return 0;
/* use polling to wait for the event */
ten_msec = jiffies + usecs_to_jiffies(TPM_I2C_RETRY_DELAY_LONG);
stop = jiffies + timeout; do { if (time_before(jiffies, ten_msec))
usleep_range(TPM_I2C_RETRY_DELAY_SHORT,
TPM_I2C_RETRY_DELAY_SHORT
+ TPM_I2C_DELAY_RANGE); else
usleep_range(TPM_I2C_RETRY_DELAY_LONG,
TPM_I2C_RETRY_DELAY_LONG
+ TPM_I2C_DELAY_RANGE);
status_valid = i2c_nuvoton_check_status(chip, mask,
value); if (status_valid) return 0;
} while (time_before(jiffies, stop));
}
dev_err(&chip->dev, "%s(%02x, %02x) -> timeout\n", __func__, mask,
value); return -ETIMEDOUT;
}
/* wait for dataAvail field to be set in the TPM_STS register */ staticint i2c_nuvoton_wait_for_data_avail(struct tpm_chip *chip, u32 timeout,
wait_queue_head_t *queue)
{ return i2c_nuvoton_wait_for_stat(chip,
TPM_STS_DATA_AVAIL | TPM_STS_VALID,
TPM_STS_DATA_AVAIL | TPM_STS_VALID,
timeout, queue);
}
if (count < TPM_HEADER_SIZE) {
i2c_nuvoton_ready(chip); /* return to idle */
dev_err(dev, "%s() count < header size\n", __func__); return -EIO;
} for (retries = 0; retries < TPM_I2C_RETRIES; retries++) { if (retries > 0) { /* if this is not the first trial, set responseRetry */
i2c_nuvoton_write_status(client,
TPM_STS_RESPONSE_RETRY);
} /* * read first available (> 10 bytes), including: * tag, paramsize, and result
*/
status = i2c_nuvoton_wait_for_data_avail(
chip, chip->timeout_c, &priv->read_queue); if (status != 0) {
dev_err(dev, "%s() timeout on dataAvail\n", __func__);
size = -ETIMEDOUT; continue;
}
burst_count = i2c_nuvoton_get_burstcount(client, chip); if (burst_count < 0) {
dev_err(dev, "%s() fail to get burstCount\n", __func__);
size = -EIO; continue;
}
size = i2c_nuvoton_recv_data(client, chip, buf,
burst_count); if (size < TPM_HEADER_SIZE) {
dev_err(dev, "%s() fail to read header\n", __func__);
size = -EIO; continue;
} /* * convert number of expected bytes field from big endian 32 bit * to machine native
*/
expected = be32_to_cpu(*(__be32 *) (buf + 2)); if (expected > count || expected < size) {
dev_err(dev, "%s() expected > count\n", __func__);
size = -EIO; continue;
}
rc = i2c_nuvoton_recv_data(client, chip, &buf[size],
expected - size);
size += rc; if (rc < 0 || size < expected) {
dev_err(dev, "%s() fail to read remainder of result\n",
__func__);
size = -EIO; continue;
} if (i2c_nuvoton_wait_for_stat(
chip, TPM_STS_VALID | TPM_STS_DATA_AVAIL,
TPM_STS_VALID, chip->timeout_c,
NULL)) {
dev_err(dev, "%s() error left over data\n", __func__);
size = -ETIMEDOUT; continue;
} break;
}
i2c_nuvoton_ready(chip);
dev_dbg(&chip->dev, "%s() -> %d\n", __func__, size); return size;
}
/* * Send TPM command. * * If interrupts are used (signaled by an irq set in the vendor structure) * tpm.c can skip polling for the data to be available as the interrupt is * waited for here
*/ staticint i2c_nuvoton_send(struct tpm_chip *chip, u8 *buf, size_t bufsiz,
size_t len)
{ struct priv_data *priv = dev_get_drvdata(&chip->dev); struct device *dev = chip->dev.parent; struct i2c_client *client = to_i2c_client(dev);
u32 ordinal; unsignedlong duration;
size_t count = 0; int burst_count, bytes2write, retries, rc = -EIO;
/* The only purpose for the handler is to signal to any waiting threads that * the interrupt is currently being asserted. The driver does not do any * processing triggered by interrupts, and the chip provides no way to mask at * the source (plus that would be slow over I2C). Run the IRQ as a one-shot,
* this means it cannot be shared. */ static irqreturn_t i2c_nuvoton_int_handler(int dummy, void *dev_id)
{ struct tpm_chip *chip = dev_id; struct priv_data *priv = dev_get_drvdata(&chip->dev);
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) return -ENODEV;
rc = i2c_nuvoton_read_buf(client, TPM_VID_DID_RID, 4, (u8 *)&temp); if (rc < 0) return rc;
/* check WPCT301 values - ignore RID */ if (memcmp(&temp, vid_did_rid_value, sizeof(vid_did_rid_value))) { /* * f/w rev 2.81 has an issue where the VID_DID_RID is not * reporting the right value. so give it another chance at * offset 0x20 (FIFO_W).
*/
rc = i2c_nuvoton_read_buf(client, TPM_DATA_FIFO_W, 4,
(u8 *) (&temp)); if (rc < 0) return rc;
/* * I2C intfcaps (interrupt capabilitieis) in the chip are hard coded to: * TPM_INTF_INT_LEVEL_LOW | TPM_INTF_DATA_AVAIL_INT * The IRQ should be set in the i2c_board_info (which is done
* automatically in of_i2c_register_devices, for device tree users */
priv->irq = client->irq; if (client->irq) {
dev_dbg(dev, "%s() priv->irq\n", __func__);
rc = devm_request_irq(dev, client->irq,
i2c_nuvoton_int_handler,
IRQF_TRIGGER_LOW,
dev_name(&chip->dev),
chip); if (rc) {
dev_err(dev, "%s() Unable to request irq: %d for use\n",
__func__, priv->irq);
priv->irq = 0;
} else {
chip->flags |= TPM_CHIP_FLAG_IRQ; /* Clear any pending interrupt */
i2c_nuvoton_ready(chip); /* - wait for TPM_STS==0xA0 (stsValid, commandReady) */
rc = i2c_nuvoton_wait_for_stat(chip,
TPM_STS_COMMAND_READY,
TPM_STS_COMMAND_READY,
chip->timeout_b,
NULL); if (rc == 0) { /* * TIS is in ready state * write dummy byte to enter reception state * TPM_DATA_FIFO_W <- rc (0)
*/
rc = i2c_nuvoton_write_buf(client,
TPM_DATA_FIFO_W,
1, (u8 *) (&rc)); if (rc < 0) return rc; /* TPM_STS <- 0x40 (commandReady) */
i2c_nuvoton_ready(chip);
} else { /* * timeout_b reached - command was * aborted. TIS should now be in idle state - * only TPM_STS_VALID should be set
*/ if (i2c_nuvoton_read_status(chip) !=
TPM_STS_VALID) return -EIO;
}
}
}
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