/* * DOC: basic fixed multiplier and divider clock that cannot gate * * Traits of this clock: * prepare - clk_prepare only ensures that parents are prepared * enable - clk_enable only ensures that parents are enabled * rate - rate is fixed. clk->rate = parent->rate / div * mult * parent - fixed parent. No clk_set_parent support
*/
staticint clk_factor_set_rate(struct clk_hw *hw, unsignedlong rate, unsignedlong parent_rate)
{ /* * We must report success but we can do so unconditionally because * clk_factor_round_rate returns values that ensure this call is a * nop.
*/
/* * We can not use clk_hw_unregister_fixed_factor, since it will kfree() * the hw, resulting in double free. Just unregister the hw and let * devres code kfree() it.
*/
clk_hw_unregister(&fix->hw);
}
hw = &fix->hw; if (dev)
ret = clk_hw_register(dev, hw); else
ret = of_clk_hw_register(np, hw); if (ret) { if (devm)
devres_free(fix); else
kfree(fix);
hw = ERR_PTR(ret);
} elseif (devm)
devres_add(dev, fix);
return hw;
}
/** * devm_clk_hw_register_fixed_factor_index - Register a fixed factor clock with * parent from DT index * @dev: device that is registering this clock * @name: name of this clock * @index: index of phandle in @dev 'clocks' property * @flags: fixed factor flags * @mult: multiplier * @div: divider * * Return: Pointer to fixed factor clk_hw structure that was registered or * an error pointer.
*/ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, constchar *name, unsignedint index, unsignedlong flags, unsignedint mult, unsignedint div)
{ conststruct clk_parent_data pdata = { .index = index };
if (of_property_read_u32(node, "clock-div", &div)) {
pr_err("%s Fixed factor clock <%pOFn> must have a clock-div property\n",
__func__, node); return ERR_PTR(-EIO);
}
if (of_property_read_u32(node, "clock-mult", &mult)) {
pr_err("%s Fixed factor clock <%pOFn> must have a clock-mult property\n",
__func__, node); return ERR_PTR(-EIO);
}
hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL,
&pdata, 0, mult, div, 0, 0, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be * attempted again from probe function.
*/
of_node_clear_flag(node, OF_POPULATED); return ERR_CAST(hw);
}
ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); if (ret) {
clk_hw_unregister_fixed_factor(hw); return ERR_PTR(ret);
}
return hw;
}
/** * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock * @node: device node for the clock
*/ void __init of_fixed_factor_clk_setup(struct device_node *node)
{
_of_fixed_factor_clk_setup(node);
}
CLK_OF_DECLARE(fixed_factor_clk, "fixed-factor-clock",
of_fixed_factor_clk_setup);
/* * This function is not executed when of_fixed_factor_clk_setup * succeeded.
*/
clk = _of_fixed_factor_clk_setup(pdev->dev.of_node); if (IS_ERR(clk)) return PTR_ERR(clk);
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