Quelle gcc-msm8953.c Sprache: C

// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2021, The Linux Foundation. All rights reserved.

#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>

#include <dt-bindings/clock/qcom,gcc-msm8953.h>

#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"

enum {
P_XO,
P_SLEEP_CLK,
P_GPLL0,
P_GPLL0_DIV2,
P_GPLL2,
P_GPLL3,
P_GPLL4,
P_GPLL6,
P_GPLL6_DIV2,
P_DSI0PLL,
P_DSI0PLL_BYTE,
P_DSI1PLL,
P_DSI1PLL_BYTE,
};

static struct clk_alpha_pll gpll0_early = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
  .enable_reg = 0x45000,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gpll0_early",
   .parent_data = &(const struct clk_parent_data) {
    .fw_name = "xo",
   },
   .num_parents = 1,
   .ops = &clk_alpha_pll_fixed_ops,
  },
},
};

static struct clk_fixed_factor gpll0_early_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
  .name = "gpll0_early_div",
  .parent_hws = (const struct clk_hw*[]){
   &gpll0_early.clkr.hw,
  },
  .num_parents = 1,
  .ops = &clk_fixed_factor_ops,
},
};

static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
  .name = "gpll0",
  .parent_hws = (const struct clk_hw*[]){
   &gpll0_early.clkr.hw,
  },
  .num_parents = 1,
  .ops = &clk_alpha_pll_postdiv_ro_ops,
},
};

static struct clk_alpha_pll gpll2_early = {
.offset = 0x4a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
  .enable_reg = 0x45000,
  .enable_mask = BIT(2),
  .hw.init = &(struct clk_init_data){
   .name = "gpll2_early",
   .parent_data = &(const struct clk_parent_data) {
    .fw_name = "xo",
   },
   .num_parents = 1,
   .ops = &clk_alpha_pll_fixed_ops,
  },
},
};

static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x4a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
  .name = "gpll2",
  .parent_hws = (const struct clk_hw*[]){
   &gpll2_early.clkr.hw,
  },
  .num_parents = 1,
  .ops = &clk_alpha_pll_postdiv_ro_ops,
},
};

static const struct pll_vco gpll3_p_vco[] = {
{ 1000000000, 2000000000, 0 },
};

static const struct alpha_pll_config gpll3_early_config = {
.l = 63,
.config_ctl_val = 0x4001055b,
.early_output_mask = 0,
.post_div_mask = GENMASK(11, 8),
.post_div_val = BIT(8),
};

static struct clk_alpha_pll gpll3_early = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = gpll3_p_vco,
.num_vco = ARRAY_SIZE(gpll3_p_vco),
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
  .hw.init = &(struct clk_init_data){
   .name = "gpll3_early",
   .parent_data = &(const struct clk_parent_data) {
    .fw_name = "xo",
   },
   .num_parents = 1,
   .ops = &clk_alpha_pll_ops,
  },
},
};

static struct clk_alpha_pll_postdiv gpll3 = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
  .name = "gpll3",
  .parent_hws = (const struct clk_hw*[]){
   &gpll3_early.clkr.hw,
  },
  .num_parents = 1,
  .ops = &clk_alpha_pll_postdiv_ops,
  .flags = CLK_SET_RATE_PARENT,
},
};

static struct clk_alpha_pll gpll4_early = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
  .enable_reg = 0x45000,
  .enable_mask = BIT(5),
  .hw.init = &(struct clk_init_data){
   .name = "gpll4_early",
   .parent_data = &(const struct clk_parent_data) {
    .fw_name = "xo",
   },
   .num_parents = 1,
   .ops = &clk_alpha_pll_fixed_ops,
  },
},
};

static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
  .name = "gpll4",
  .parent_hws = (const struct clk_hw*[]){
   &gpll4_early.clkr.hw,
  },
  .num_parents = 1,
  .ops = &clk_alpha_pll_postdiv_ro_ops,
},
};

static struct clk_alpha_pll gpll6_early = {
.offset = 0x37000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
  .enable_reg = 0x45000,
  .enable_mask = BIT(7),
  .hw.init = &(struct clk_init_data){
   .name = "gpll6_early",
   .parent_data = &(const struct clk_parent_data) {
    .fw_name = "xo",
   },
   .num_parents = 1,
   .ops = &clk_alpha_pll_fixed_ops,
  },
},
};

static struct clk_fixed_factor gpll6_early_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
  .name = "gpll6_early_div",
  .parent_hws = (const struct clk_hw*[]){
   &gpll6_early.clkr.hw,
  },
  .num_parents = 1,
  .ops = &clk_fixed_factor_ops,
},
};

static struct clk_alpha_pll_postdiv gpll6 = {
.offset = 0x37000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
  .name = "gpll6",
  .parent_hws = (const struct clk_hw*[]){
   &gpll6_early.clkr.hw,
  },
  .num_parents = 1,
  .ops = &clk_alpha_pll_postdiv_ro_ops,
},
};

static const struct parent_map gcc_xo_gpll0_gpll0div2_2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_DIV2, 2 },
};

static const struct parent_map gcc_xo_gpll0_gpll0div2_4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_DIV2, 4 },
};

static const struct clk_parent_data gcc_xo_gpll0_gpll0div2_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};

static const struct parent_map gcc_apc_droop_detector_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 2 },
};

static const struct clk_parent_data gcc_apc_droop_detector_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};

static const struct freq_tbl ftbl_apc_droop_detector_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(576000000, P_GPLL4, 2, 0, 0),
{ }
};

static struct clk_rcg2 apc0_droop_detector_clk_src = {
.cmd_rcgr = 0x78008,
.hid_width = 5,
.freq_tbl = ftbl_apc_droop_detector_clk_src,
.parent_map = gcc_apc_droop_detector_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "apc0_droop_detector_clk_src",
  .parent_data = gcc_apc_droop_detector_data,
  .num_parents = ARRAY_SIZE(gcc_apc_droop_detector_data),
  .ops = &clk_rcg2_ops,
}
};
static struct clk_rcg2 apc1_droop_detector_clk_src = {
.cmd_rcgr = 0x79008,
.hid_width = 5,
.freq_tbl = ftbl_apc_droop_detector_clk_src,
.parent_map = gcc_apc_droop_detector_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "apc1_droop_detector_clk_src",
  .parent_data = gcc_apc_droop_detector_data,
  .num_parents = ARRAY_SIZE(gcc_apc_droop_detector_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_DIV2, 16, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
{ }
};

static struct clk_rcg2 apss_ahb_clk_src = {
.cmd_rcgr = 0x46000,
.hid_width = 5,
.freq_tbl = ftbl_apss_ahb_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "apss_ahb_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_DIV2, 16, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};

static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0200c,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp1_qup1_i2c_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x03000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp1_qup2_i2c_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x04000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp1_qup3_i2c_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x05000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp1_qup4_i2c_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0c00c,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp2_qup1_i2c_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x0d000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp2_qup2_i2c_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x0f000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp2_qup3_i2c_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x18000,
.hid_width = 5,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp2_qup4_i2c_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(12500000, P_GPLL0_DIV2, 16, 1, 2),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};

static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x02024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp1_qup1_spi_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x03014,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp1_qup2_spi_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x04024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp1_qup3_spi_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x05024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp1_qup4_spi_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x0c024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp2_qup1_spi_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x0d014,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp2_qup2_spi_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x0f024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp2_qup3_spi_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x18024,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_blsp_spi_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp2_qup4_spi_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
F(16000000, P_GPLL0_DIV2, 5, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 1, 3, 100),
F(25000000, P_GPLL0, 16, 1, 2),
F(32000000, P_GPLL0, 1, 1, 25),
F(40000000, P_GPLL0, 1, 1, 20),
F(46400000, P_GPLL0, 1, 29, 500),
F(48000000, P_GPLL0, 1, 3, 50),
F(51200000, P_GPLL0, 1, 8, 125),
F(56000000, P_GPLL0, 1, 7, 100),
F(58982400, P_GPLL0, 1, 1152, 15625),
F(60000000, P_GPLL0, 1, 3, 40),
F(64000000, P_GPLL0, 1, 2, 25),
{ }
};

static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x02044,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp1_uart1_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x03034,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp1_uart2_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.cmd_rcgr = 0x0c044,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp2_uart1_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.cmd_rcgr = 0x0d034,
.hid_width = 5,
.mnd_width = 16,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "blsp2_uart2_apps_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_byte0_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 1 },
{ P_DSI1PLL_BYTE, 3 },
};

static const struct parent_map gcc_byte1_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 3 },
{ P_DSI1PLL_BYTE, 1 },
};

static const struct clk_parent_data gcc_byte_data[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
};

static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x4d044,
.hid_width = 5,
.parent_map = gcc_byte0_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "byte0_clk_src",
  .parent_data = gcc_byte_data,
  .num_parents = ARRAY_SIZE(gcc_byte_data),
  .ops = &clk_byte2_ops,
  .flags = CLK_SET_RATE_PARENT,
}
};

static struct clk_rcg2 byte1_clk_src = {
.cmd_rcgr = 0x4d0b0,
.hid_width = 5,
.parent_map = gcc_byte1_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "byte1_clk_src",
  .parent_data = gcc_byte_data,
  .num_parents = ARRAY_SIZE(gcc_byte_data),
  .ops = &clk_byte2_ops,
  .flags = CLK_SET_RATE_PARENT,
}
};

static const struct parent_map gcc_gp_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 4 },
{ P_SLEEP_CLK, 6 },
};

static const struct clk_parent_data gcc_gp_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_early_div.hw },
{ .fw_name = "sleep", .name = "sleep" },
};

static const struct freq_tbl ftbl_camss_gp_clk_src[] = {
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
{ }
};

static struct clk_rcg2 camss_gp0_clk_src = {
.cmd_rcgr = 0x54000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_camss_gp_clk_src,
.parent_map = gcc_gp_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "camss_gp0_clk_src",
  .parent_data = gcc_gp_data,
  .num_parents = ARRAY_SIZE(gcc_gp_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 camss_gp1_clk_src = {
.cmd_rcgr = 0x55000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_camss_gp_clk_src,
.parent_map = gcc_gp_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "camss_gp1_clk_src",
  .parent_data = gcc_gp_data,
  .num_parents = ARRAY_SIZE(gcc_gp_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {
F(40000000, P_GPLL0_DIV2, 10, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
{ }
};

static struct clk_rcg2 camss_top_ahb_clk_src = {
.cmd_rcgr = 0x5a000,
.hid_width = 5,
.freq_tbl = ftbl_camss_top_ahb_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "camss_top_ahb_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_cci_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 2 },
{ P_GPLL0_DIV2, 3 },
{ P_SLEEP_CLK, 6 },
};

static const struct clk_parent_data gcc_cci_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_early_div.hw },
{ .fw_name = "sleep", .name = "sleep" },
};

static const struct freq_tbl ftbl_cci_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0_DIV2, 1, 3, 32),
{ }
};

static struct clk_rcg2 cci_clk_src = {
.cmd_rcgr = 0x51000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_cci_clk_src,
.parent_map = gcc_cci_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "cci_clk_src",
  .parent_data = gcc_cci_data,
  .num_parents = ARRAY_SIZE(gcc_cci_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_cpp_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 3 },
{ P_GPLL2, 4 },
{ P_GPLL0_DIV2, 5 },
};

static const struct clk_parent_data gcc_cpp_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};

static const struct freq_tbl ftbl_cpp_clk_src[] = {
F(100000000, P_GPLL0_DIV2, 4, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(465000000, P_GPLL2, 2, 0, 0),
{ }
};

static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x58018,
.hid_width = 5,
.freq_tbl = ftbl_cpp_clk_src,
.parent_map = gcc_cpp_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "cpp_clk_src",
  .parent_data = gcc_cpp_data,
  .num_parents = ARRAY_SIZE(gcc_cpp_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct freq_tbl ftbl_crypto_clk_src[] = {
F(40000000, P_GPLL0_DIV2, 10, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
{ }
};

static struct clk_rcg2 crypto_clk_src = {
.cmd_rcgr = 0x16004,
.hid_width = 5,
.freq_tbl = ftbl_crypto_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "crypto_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_csi0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 4 },
{ P_GPLL0_DIV2, 5 },
};

static const struct parent_map gcc_csi12_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 5 },
{ P_GPLL0_DIV2, 4 },
};

static const struct clk_parent_data gcc_csi_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};

static const struct freq_tbl ftbl_csi_clk_src[] = {
F(100000000, P_GPLL0_DIV2, 4, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(465000000, P_GPLL2, 2, 0, 0),
{ }
};

static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x4e020,
.hid_width = 5,
.freq_tbl = ftbl_csi_clk_src,
.parent_map = gcc_csi0_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "csi0_clk_src",
  .parent_data = gcc_csi_data,
  .num_parents = ARRAY_SIZE(gcc_csi_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x4f020,
.hid_width = 5,
.freq_tbl = ftbl_csi_clk_src,
.parent_map = gcc_csi12_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "csi1_clk_src",
  .parent_data = gcc_csi_data,
  .num_parents = ARRAY_SIZE(gcc_csi_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 csi2_clk_src = {
.cmd_rcgr = 0x3c020,
.hid_width = 5,
.freq_tbl = ftbl_csi_clk_src,
.parent_map = gcc_csi12_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "csi2_clk_src",
  .parent_data = gcc_csi_data,
  .num_parents = ARRAY_SIZE(gcc_csi_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_csip_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 3 },
{ P_GPLL2, 4 },
{ P_GPLL0_DIV2, 5 },
};

static const struct clk_parent_data gcc_csip_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};

static const struct freq_tbl ftbl_csi_p_clk_src[] = {
F(66670000, P_GPLL0_DIV2, 6, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
{ }
};

static struct clk_rcg2 csi0p_clk_src = {
.cmd_rcgr = 0x58084,
.hid_width = 5,
.freq_tbl = ftbl_csi_p_clk_src,
.parent_map = gcc_csip_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "csi0p_clk_src",
  .parent_data = gcc_csip_data,
  .num_parents = ARRAY_SIZE(gcc_csip_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 csi1p_clk_src = {
.cmd_rcgr = 0x58094,
.hid_width = 5,
.freq_tbl = ftbl_csi_p_clk_src,
.parent_map = gcc_csip_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "csi1p_clk_src",
  .parent_data = gcc_csip_data,
  .num_parents = ARRAY_SIZE(gcc_csip_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 csi2p_clk_src = {
.cmd_rcgr = 0x580a4,
.hid_width = 5,
.freq_tbl = ftbl_csi_p_clk_src,
.parent_map = gcc_csip_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "csi2p_clk_src",
  .parent_data = gcc_csip_data,
  .num_parents = ARRAY_SIZE(gcc_csip_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = {
F(100000000, P_GPLL0_DIV2, 4, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
{ }
};

static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x4e000,
.hid_width = 5,
.freq_tbl = ftbl_csi_phytimer_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "csi0phytimer_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 csi1phytimer_clk_src = {
.cmd_rcgr = 0x4f000,
.hid_width = 5,
.freq_tbl = ftbl_csi_phytimer_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "csi1phytimer_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 csi2phytimer_clk_src = {
.cmd_rcgr = 0x4f05c,
.hid_width = 5,
.freq_tbl = ftbl_csi_phytimer_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "csi2phytimer_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_esc_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 3 },
};

static const struct clk_parent_data gcc_esc_vsync_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
};

static const struct freq_tbl ftbl_esc0_1_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};

static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x4d05c,
.hid_width = 5,
.freq_tbl = ftbl_esc0_1_clk_src,
.parent_map = gcc_esc_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "esc0_clk_src",
  .parent_data = gcc_esc_vsync_data,
  .num_parents = ARRAY_SIZE(gcc_esc_vsync_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 esc1_clk_src = {
.cmd_rcgr = 0x4d0a8,
.hid_width = 5,
.freq_tbl = ftbl_esc0_1_clk_src,
.parent_map = gcc_esc_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "esc1_clk_src",
  .parent_data = gcc_esc_vsync_data,
  .num_parents = ARRAY_SIZE(gcc_esc_vsync_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_gfx3d_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL3, 2 },
{ P_GPLL6, 3 },
{ P_GPLL4, 4 },
{ P_GPLL0_DIV2, 5 },
{ P_GPLL6_DIV2, 6 },
};

static const struct clk_parent_data gcc_gfx3d_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll3.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_early_div.hw },
{ .hw = &gpll6_early_div.hw },
};

static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(80000000, P_GPLL0_DIV2, 5, 0, 0),
F(100000000, P_GPLL0_DIV2, 4, 0, 0),
F(133330000, P_GPLL0_DIV2, 3, 0, 0),
F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
F(200000000, P_GPLL0_DIV2, 2, 0, 0),
F(266670000, P_GPLL0, 3.0, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(460800000, P_GPLL4, 2.5, 0, 0),
F(510000000, P_GPLL3, 2, 0, 0),
F(560000000, P_GPLL3, 2, 0, 0),
F(600000000, P_GPLL3, 2, 0, 0),
F(650000000, P_GPLL3, 2, 0, 0),
F(685000000, P_GPLL3, 2, 0, 0),
F(725000000, P_GPLL3, 2, 0, 0),
{ }
};

static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x59000,
.hid_width = 5,
.freq_tbl = ftbl_gfx3d_clk_src,
.parent_map = gcc_gfx3d_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "gfx3d_clk_src",
  .parent_data = gcc_gfx3d_data,
  .num_parents = ARRAY_SIZE(gcc_gfx3d_data),
  .ops = &clk_rcg2_floor_ops,
  .flags = CLK_SET_RATE_PARENT,
}
};

static const struct freq_tbl ftbl_gp_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};

static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x08004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gp_clk_src,
.parent_map = gcc_gp_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "gp1_clk_src",
  .parent_data = gcc_gp_data,
  .num_parents = ARRAY_SIZE(gcc_gp_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x09004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gp_clk_src,
.parent_map = gcc_gp_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "gp2_clk_src",
  .parent_data = gcc_gp_data,
  .num_parents = ARRAY_SIZE(gcc_gp_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x0a004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_gp_clk_src,
.parent_map = gcc_gp_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "gp3_clk_src",
  .parent_data = gcc_gp_data,
  .num_parents = ARRAY_SIZE(gcc_gp_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_jpeg0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 4 },
{ P_GPLL2, 5 },
};

static const struct clk_parent_data gcc_jpeg0_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_early_div.hw },
{ .hw = &gpll2.clkr.hw },
};

static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
F(66670000, P_GPLL0_DIV2, 6, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
{ }
};

static struct clk_rcg2 jpeg0_clk_src = {
.cmd_rcgr = 0x57000,
.hid_width = 5,
.freq_tbl = ftbl_jpeg0_clk_src,
.parent_map = gcc_jpeg0_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "jpeg0_clk_src",
  .parent_data = gcc_jpeg0_data,
  .num_parents = ARRAY_SIZE(gcc_jpeg0_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_mclk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 4 },
{ P_GPLL6_DIV2, 5 },
{ P_SLEEP_CLK, 6 },
};

static const struct clk_parent_data gcc_mclk_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_early_div.hw },
{ .hw = &gpll6_early_div.hw },
{ .fw_name = "sleep", .name = "sleep" },
};

static const struct freq_tbl ftbl_mclk_clk_src[] = {
F(19200000, P_GPLL6, 5, 4, 45),
F(24000000, P_GPLL6_DIV2, 1, 2, 45),
F(26000000, P_GPLL0, 1, 4, 123),
F(33330000, P_GPLL0_DIV2, 12, 0, 0),
F(36610000, P_GPLL6, 1, 2, 59),
F(66667000, P_GPLL0, 12, 0, 0),
{ }
};

static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x52000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_mclk_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "mclk0_clk_src",
  .parent_data = gcc_mclk_data,
  .num_parents = ARRAY_SIZE(gcc_mclk_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x53000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_mclk_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "mclk1_clk_src",
  .parent_data = gcc_mclk_data,
  .num_parents = ARRAY_SIZE(gcc_mclk_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 mclk2_clk_src = {
.cmd_rcgr = 0x5c000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_mclk_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "mclk2_clk_src",
  .parent_data = gcc_mclk_data,
  .num_parents = ARRAY_SIZE(gcc_mclk_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 mclk3_clk_src = {
.cmd_rcgr = 0x5e000,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_mclk_clk_src,
.parent_map = gcc_mclk_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "mclk3_clk_src",
  .parent_data = gcc_mclk_data,
  .num_parents = ARRAY_SIZE(gcc_mclk_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_mdp_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 3 },
{ P_GPLL0_DIV2, 4 },
};

static const struct clk_parent_data gcc_mdp_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};

static const struct freq_tbl ftbl_mdp_clk_src[] = {
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(80000000, P_GPLL0_DIV2, 5, 0, 0),
F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};

static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x4d014,
.hid_width = 5,
.freq_tbl = ftbl_mdp_clk_src,
.parent_map = gcc_mdp_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "mdp_clk_src",
  .parent_data = gcc_mdp_data,
  .num_parents = ARRAY_SIZE(gcc_mdp_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_pclk0_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 3 },
};

static const struct parent_map gcc_pclk1_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 3 },
{ P_DSI1PLL, 1 },
};

static const struct clk_parent_data gcc_pclk_data[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
{ .fw_name = "dsi1pll", .name = "dsi1pll" },
};

static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x4d000,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_pclk0_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "pclk0_clk_src",
  .parent_data = gcc_pclk_data,
  .num_parents = ARRAY_SIZE(gcc_pclk_data),
  .ops = &clk_pixel_ops,
  .flags = CLK_SET_RATE_PARENT,
}
};

static struct clk_rcg2 pclk1_clk_src = {
.cmd_rcgr = 0x4d0b8,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_pclk1_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "pclk1_clk_src",
  .parent_data = gcc_pclk_data,
  .num_parents = ARRAY_SIZE(gcc_pclk_data),
  .ops = &clk_pixel_ops,
  .flags = CLK_SET_RATE_PARENT,
}
};

static const struct freq_tbl ftbl_pdm2_clk_src[] = {
F(32000000, P_GPLL0_DIV2, 12.5, 0, 0),
F(64000000, P_GPLL0, 12.5, 0, 0),
{ }
};

static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x44010,
.hid_width = 5,
.freq_tbl = ftbl_pdm2_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "pdm2_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct freq_tbl ftbl_rbcpr_gfx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};

static struct clk_rcg2 rbcpr_gfx_clk_src = {
.cmd_rcgr = 0x3a00c,
.hid_width = 5,
.freq_tbl = ftbl_rbcpr_gfx_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "rbcpr_gfx_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_sdcc1_ice_core_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 4 },
};

static const struct clk_parent_data gcc_sdcc1_ice_core_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};

static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
F(80000000, P_GPLL0_DIV2, 5, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(270000000, P_GPLL6, 4, 0, 0),
{ }
};

static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x5d000,
.hid_width = 5,
.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
.parent_map = gcc_sdcc1_ice_core_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "sdcc1_ice_core_clk_src",
  .parent_data = gcc_sdcc1_ice_core_data,
  .num_parents = ARRAY_SIZE(gcc_sdcc1_ice_core_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_sdcc_apps_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 2 },
{ P_GPLL0_DIV2, 4 },
};

static const struct clk_parent_data gcc_sdcc_apss_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};

static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_DIV2, 5, 1, 4),
F(25000000, P_GPLL0_DIV2, 16, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(177770000, P_GPLL0, 4.5, 0, 0),
F(192000000, P_GPLL4, 6, 0, 0),
F(384000000, P_GPLL4, 3, 0, 0),
{ }
};

static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_sdcc1_apps_clk_src,
.parent_map = gcc_sdcc_apps_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "sdcc1_apps_clk_src",
  .parent_data = gcc_sdcc_apss_data,
  .num_parents = ARRAY_SIZE(gcc_sdcc_apss_data),
  .ops = &clk_rcg2_floor_ops,
}
};

static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_DIV2, 5, 1, 4),
F(25000000, P_GPLL0_DIV2, 16, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(177770000, P_GPLL0, 4.5, 0, 0),
F(192000000, P_GPLL4, 6, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};

static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x43004,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_sdcc2_apps_clk_src,
.parent_map = gcc_sdcc_apps_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "sdcc2_apps_clk_src",
  .parent_data = gcc_sdcc_apss_data,
  .num_parents = ARRAY_SIZE(gcc_sdcc_apss_data),
  .ops = &clk_rcg2_floor_ops,
}
};

static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
F(80000000, P_GPLL0_DIV2, 5, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
{ }
};

static struct clk_rcg2 usb30_master_clk_src = {
.cmd_rcgr = 0x3f00c,
.hid_width = 5,
.freq_tbl = ftbl_usb30_master_clk_src,
.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "usb30_master_clk_src",
  .parent_data = gcc_xo_gpll0_gpll0div2_data,
  .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_usb30_mock_utmi_map[] = {
{ P_XO, 0 },
{ P_GPLL6, 1 },
{ P_GPLL6_DIV2, 2 },
{ P_GPLL0, 3 },
{ P_GPLL0_DIV2, 4 },
};

static const struct clk_parent_data gcc_usb30_mock_utmi_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll6_early_div.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};

static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(60000000, P_GPLL6_DIV2, 9, 1, 1),
{ }
};

static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0x3f020,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
.parent_map = gcc_usb30_mock_utmi_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "usb30_mock_utmi_clk_src",
  .parent_data = gcc_usb30_mock_utmi_data,
  .num_parents = ARRAY_SIZE(gcc_usb30_mock_utmi_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_usb3_aux_map[] = {
{ P_XO, 0 },
{ P_SLEEP_CLK, 6 },
};

static const struct clk_parent_data gcc_usb3_aux_data[] = {
{ .fw_name = "xo" },
{ .fw_name = "sleep", .name = "sleep" },
};

static const struct freq_tbl ftbl_usb3_aux_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};

static struct clk_rcg2 usb3_aux_clk_src = {
.cmd_rcgr = 0x3f05c,
.hid_width = 5,
.mnd_width = 8,
.freq_tbl = ftbl_usb3_aux_clk_src,
.parent_map = gcc_usb3_aux_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "usb3_aux_clk_src",
  .parent_data = gcc_usb3_aux_data,
  .num_parents = ARRAY_SIZE(gcc_usb3_aux_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_vcodec0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL2, 3 },
{ P_GPLL0_DIV2, 4 },
};

static const struct clk_parent_data gcc_vcodec0_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};

static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
F(114290000, P_GPLL0_DIV2, 3.5, 0, 0),
F(228570000, P_GPLL0, 3.5, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(360000000, P_GPLL6, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(465000000, P_GPLL2, 2, 0, 0),
F(540000000, P_GPLL6, 2, 0, 0),
{ }
};

static struct clk_rcg2 vcodec0_clk_src = {
.cmd_rcgr = 0x4c000,
.hid_width = 5,
.freq_tbl = ftbl_vcodec0_clk_src,
.parent_map = gcc_vcodec0_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "vcodec0_clk_src",
  .parent_data = gcc_vcodec0_data,
  .num_parents = ARRAY_SIZE(gcc_vcodec0_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_vfe_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL4, 3 },
{ P_GPLL2, 4 },
{ P_GPLL0_DIV2, 5 },
};

static const struct clk_parent_data gcc_vfe_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};

static const struct freq_tbl ftbl_vfe_clk_src[] = {
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(100000000, P_GPLL0_DIV2, 4, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(465000000, P_GPLL2, 2, 0, 0),
{ }
};

static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x58000,
.hid_width = 5,
.freq_tbl = ftbl_vfe_clk_src,
.parent_map = gcc_vfe_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "vfe0_clk_src",
  .parent_data = gcc_vfe_data,
  .num_parents = ARRAY_SIZE(gcc_vfe_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_rcg2 vfe1_clk_src = {
.cmd_rcgr = 0x58054,
.hid_width = 5,
.freq_tbl = ftbl_vfe_clk_src,
.parent_map = gcc_vfe_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "vfe1_clk_src",
  .parent_data = gcc_vfe_data,
  .num_parents = ARRAY_SIZE(gcc_vfe_data),
  .ops = &clk_rcg2_ops,
}
};

static const struct parent_map gcc_vsync_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 2 },
};

static const struct freq_tbl ftbl_vsync_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};

static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x4d02c,
.hid_width = 5,
.freq_tbl = ftbl_vsync_clk_src,
.parent_map = gcc_vsync_map,
.clkr.hw.init = &(struct clk_init_data) {
  .name = "vsync_clk_src",
  .parent_data = gcc_esc_vsync_data,
  .num_parents = ARRAY_SIZE(gcc_esc_vsync_data),
  .ops = &clk_rcg2_ops,
}
};

static struct clk_branch gcc_apc0_droop_detector_gpll0_clk = {
.halt_reg = 0x78004,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x78004,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_apc0_droop_detector_gpll0_clk",
   .parent_hws = (const struct clk_hw*[]){
    &apc0_droop_detector_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_apc1_droop_detector_gpll0_clk = {
.halt_reg = 0x79004,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x79004,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_apc1_droop_detector_gpll0_clk",
   .parent_hws = (const struct clk_hw*[]){
    &apc1_droop_detector_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_apss_ahb_clk = {
.halt_reg = 0x4601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
  .enable_reg = 0x45004,
  .enable_mask = BIT(14),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_apss_ahb_clk",
   .parent_hws = (const struct clk_hw*[]){
    &apss_ahb_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_apss_axi_clk = {
.halt_reg = 0x46020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
  .enable_reg = 0x45004,
  .enable_mask = BIT(13),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_apss_axi_clk",
   .ops = &clk_branch2_ops,
  }
}
};

static struct clk_branch gcc_apss_tcu_async_clk = {
.halt_reg = 0x12018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
  .enable_reg = 0x4500c,
  .enable_mask = BIT(1),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_apss_tcu_async_clk",
   .ops = &clk_branch2_ops,
  }
}
};

static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x59034,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x59034,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_bimc_gfx_clk",
   .ops = &clk_branch2_ops,
  }
}
};

static struct clk_branch gcc_bimc_gpu_clk = {
.halt_reg = 0x59030,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x59030,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_bimc_gpu_clk",
   .ops = &clk_branch2_ops,
  }
}
};

static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
  .enable_reg = 0x45004,
  .enable_mask = BIT(10),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp1_ahb_clk",
   .ops = &clk_branch2_ops,
  }
}
};

static struct clk_branch gcc_blsp2_ahb_clk = {
.halt_reg = 0x0b008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
  .enable_reg = 0x45004,
  .enable_mask = BIT(20),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp2_ahb_clk",
   .ops = &clk_branch2_ops,
  }
}
};

static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x02008,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x02008,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp1_qup1_i2c_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x03010,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x03010,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp1_qup2_i2c_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x04020,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x04020,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp1_qup3_i2c_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x05020,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x05020,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp1_qup4_i2c_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
.halt_reg = 0x0c008,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0c008,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp2_qup1_i2c_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
.halt_reg = 0x0d010,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0d010,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp2_qup2_i2c_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
.halt_reg = 0x0f020,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0f020,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp2_qup3_i2c_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
.halt_reg = 0x18020,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x18020,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp2_qup4_i2c_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x02004,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x02004,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp1_qup1_spi_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp1_qup1_spi_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x0300c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0300c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp1_qup2_spi_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp1_qup2_spi_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x0401c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0401c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp1_qup3_spi_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp1_qup3_spi_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x0501c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0501c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp1_qup4_spi_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp1_qup4_spi_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
.halt_reg = 0x0c004,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0c004,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp2_qup1_spi_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp2_qup1_spi_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
.halt_reg = 0x0d00c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0d00c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp2_qup2_spi_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp2_qup2_spi_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
.halt_reg = 0x0f01c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0f01c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp2_qup3_spi_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp2_qup3_spi_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
.halt_reg = 0x1801c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x1801c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp2_qup4_spi_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp2_qup4_spi_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0203c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0203c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp1_uart1_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp1_uart1_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0302c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0302c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp1_uart2_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp1_uart2_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp2_uart1_apps_clk = {
.halt_reg = 0x0c03c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0c03c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp2_uart1_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp2_uart1_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_blsp2_uart2_apps_clk = {
.halt_reg = 0x0d02c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x0d02c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_blsp2_uart2_apps_clk",
   .parent_hws = (const struct clk_hw*[]){
    &blsp2_uart2_apps_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x1300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
  .enable_reg = 0x45004,
  .enable_mask = BIT(7),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_boot_rom_ahb_clk",
   .ops = &clk_branch2_ops,
  }
}
};

static struct clk_branch gcc_camss_ahb_clk = {
.halt_reg = 0x56004,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x56004,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_ahb_clk",
   .ops = &clk_branch2_ops,
  }
}
};

static struct clk_branch gcc_camss_cci_ahb_clk = {
.halt_reg = 0x5101c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x5101c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_cci_ahb_clk",
   .parent_hws = (const struct clk_hw*[]){
    &camss_top_ahb_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_cci_clk = {
.halt_reg = 0x51018,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x51018,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_cci_clk",
   .parent_hws = (const struct clk_hw*[]){
    &cci_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_cpp_ahb_clk = {
.halt_reg = 0x58040,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x58040,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_cpp_ahb_clk",
   .parent_hws = (const struct clk_hw*[]){
    &camss_top_ahb_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_cpp_axi_clk = {
.halt_reg = 0x58064,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x58064,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_cpp_axi_clk",
   .ops = &clk_branch2_ops,
  }
}
};

static struct clk_branch gcc_camss_cpp_clk = {
.halt_reg = 0x5803c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x5803c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_cpp_clk",
   .parent_hws = (const struct clk_hw*[]){
    &cpp_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi0_ahb_clk = {
.halt_reg = 0x4e040,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4e040,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi0_ahb_clk",
   .parent_hws = (const struct clk_hw*[]){
    &camss_top_ahb_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi1_ahb_clk = {
.halt_reg = 0x4f040,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4f040,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi1_ahb_clk",
   .parent_hws = (const struct clk_hw*[]){
    &camss_top_ahb_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi2_ahb_clk = {
.halt_reg = 0x3c040,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x3c040,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi2_ahb_clk",
   .parent_hws = (const struct clk_hw*[]){
    &camss_top_ahb_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi0_clk = {
.halt_reg = 0x4e03c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4e03c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi0_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi0_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi1_clk = {
.halt_reg = 0x4f03c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4f03c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi1_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi1_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi2_clk = {
.halt_reg = 0x3c03c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x3c03c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi2_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi2_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi0_csiphy_3p_clk = {
.halt_reg = 0x58090,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x58090,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi0_csiphy_3p_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi0p_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi1_csiphy_3p_clk = {
.halt_reg = 0x580a0,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x580a0,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi1_csiphy_3p_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi1p_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi2_csiphy_3p_clk = {
.halt_reg = 0x580b0,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x580b0,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi2_csiphy_3p_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi2p_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi0phy_clk = {
.halt_reg = 0x4e048,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4e048,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi0phy_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi0_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi1phy_clk = {
.halt_reg = 0x4f048,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4f048,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi1phy_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi1_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi2phy_clk = {
.halt_reg = 0x3c048,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x3c048,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi2phy_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi2_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi0phytimer_clk = {
.halt_reg = 0x4e01c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4e01c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi0phytimer_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi0phytimer_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi1phytimer_clk = {
.halt_reg = 0x4f01c,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4f01c,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi1phytimer_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi1phytimer_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi2phytimer_clk = {
.halt_reg = 0x4f068,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4f068,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi2phytimer_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi2phytimer_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi0pix_clk = {
.halt_reg = 0x4e058,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4e058,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi0pix_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi0_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi1pix_clk = {
.halt_reg = 0x4f058,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4f058,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi1pix_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi1_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi2pix_clk = {
.halt_reg = 0x3c058,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x3c058,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi2pix_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi2_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi0rdi_clk = {
.halt_reg = 0x4e050,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4e050,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi0rdi_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi0_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

static struct clk_branch gcc_camss_csi1rdi_clk = {
.halt_reg = 0x4f050,
.halt_check = BRANCH_HALT,
.clkr = {
  .enable_reg = 0x4f050,
  .enable_mask = BIT(0),
  .hw.init = &(struct clk_init_data) {
   .name = "gcc_camss_csi1rdi_clk",
   .parent_hws = (const struct clk_hw*[]){
    &csi1_clk_src.clkr.hw,
   },
   .num_parents = 1,
   .ops = &clk_branch2_ops,
   .flags = CLK_SET_RATE_PARENT,
  }
}
};

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--> maximum size reached

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Messung V0.5

¤ Dauer der Verarbeitung: 0.23 Sekunden (vorverarbeitet) ¤

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Cephes Mathematical Library

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