Quellcodebibliothek Statistik Leitseite products/sources/formale Sprachen/C/Linux/drivers/clk/samsung/   (Open Source Betriebssystem Version 6.17.9©)  Datei vom 24.10.2025 mit Größe 188 kB image not shown  

Quelle  clk-exynos2200.c   Sprache: C

 
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2025 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
 * Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
 *
 * Common Clock Framework support for Exynos2200 SoC.
 */

#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>

#include <dt-bindings/clock/samsung,exynos2200-cmu.h>

#include "clk.h"
#include "clk-exynos-arm64.h"

/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP   (CLK_DOUT_TCXO_DIV4 + 1)
#define CLKS_NR_ALIVE   (CLK_DOUT_ALIVE_DSP_NOC + 1)
#define CLKS_NR_PERIS   (CLK_DOUT_PERIS_DDD_CTRL + 1)
#define CLKS_NR_CMGP   (CLK_DOUT_CMGP_USI6 + 1)
#define CLKS_NR_HSI0   (CLK_DOUT_DIV_CLK_HSI0_EUSB + 1)
#define CLKS_NR_PERIC0   (CLK_DOUT_PERIC0_USI04 + 1)
#define CLKS_NR_PERIC1   (CLK_DOUT_PERIC1_USI10 + 1)
#define CLKS_NR_PERIC2   (CLK_DOUT_PERIC2_USI11 + 1)
#define CLKS_NR_UFS   (CLK_MOUT_UFS_UFS_EMBD_USER + 1)
#define CLKS_NR_VTS   (CLK_DOUT_CLKVTS_SERIAL_LIF_CORE + 1)

/* ---- CMU_TOP ------------------------------------------------------------ */

/* Register Offset definitions for CMU_TOP (0x1a320000) */
#define PLL_LOCKTIME_PLL_MMC    0x0
#define PLL_LOCKTIME_PLL_SHARED0   0x4
#define PLL_LOCKTIME_PLL_SHARED1   0x8
#define PLL_LOCKTIME_PLL_SHARED2   0xc
#define PLL_LOCKTIME_PLL_SHARED3   0x10
#define PLL_LOCKTIME_PLL_SHARED4   0x14
#define PLL_LOCKTIME_PLL_SHARED_MIF   0x18
#define PLL_CON3_PLL_MMC    0x10c
#define PLL_CON8_PLL_MMC    0x120
#define PLL_CON3_PLL_SHARED0    0x14c
#define PLL_CON8_PLL_SHARED0    0x160
#define PLL_CON3_PLL_SHARED1    0x18c
#define PLL_CON8_PLL_SHARED1    0x1a0
#define PLL_CON3_PLL_SHARED2    0x1cc
#define PLL_CON8_PLL_SHARED2    0x1e0
#define PLL_CON3_PLL_SHARED3    0x20c
#define PLL_CON8_PLL_SHARED3    0x220
#define PLL_CON3_PLL_SHARED4    0x24c
#define PLL_CON8_PLL_SHARED4    0x260
#define PLL_CON3_PLL_SHARED_MIF    0x28c
#define PLL_CON8_PLL_SHARED_MIF    0x2a0
#define PLL_CON0_MUX_CP_MPLL_CLK_D2_USER  0x600
#define PLL_CON1_MUX_CP_MPLL_CLK_D2_USER  0x604
#define PLL_CON0_MUX_CP_MPLL_CLK_USER   0x610
#define PLL_CON1_MUX_CP_MPLL_CLK_USER   0x614
#define CLK_CON_MUX_CLKCMU_AUD_AUDIF0   0x1000
#define CLK_CON_MUX_CLKCMU_AUD_AUDIF1   0x1004
#define CLK_CON_MUX_CLKCMU_AUD_CPU   0x1008
#define CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC  0x100c
#define CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH  0x1010
#define CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH  0x1014
#define CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH  0x1018
#define CLK_CON_MUX_CLKCMU_DNC_NOC   0x101c
#define CLK_CON_MUX_CLKCMU_DPUB_NOC   0x1020
#define CLK_CON_MUX_CLKCMU_DPUF_NOC   0x1024
#define CLK_CON_MUX_CLKCMU_DSP_NOC   0x102c
#define CLK_CON_MUX_CLKCMU_DSU_SWITCH   0x1030
#define CLK_CON_MUX_CLKCMU_G3D_SWITCH   0x1034
#define CLK_CON_MUX_CLKCMU_GNPU_NOC   0x103c
#define CLK_CON_MUX_CLKCMU_UFS_MMC_CARD   0x1040
#define CLK_CON_MUX_CLKCMU_M2M_NOC   0x1044
#define CLK_CON_MUX_CLKCMU_NOCL0_NOC   0x1048
#define CLK_CON_MUX_CLKCMU_NOCL1A_NOC   0x104c
#define CLK_CON_MUX_CLKCMU_NOCL1B_NOC0   0x1050
#define CLK_CON_MUX_CLKCMU_NOCL1C_NOC   0x1054
#define CLK_CON_MUX_CLKCMU_SDMA_NOC   0x1058
#define CLK_CON_MUX_CP_HISPEEDY_CLK   0x105c
#define CLK_CON_MUX_CP_SHARED0_CLK   0x1060
#define CLK_CON_MUX_CP_SHARED2_CLK   0x1064
#define CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC  0x1068
#define CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0  0x106c
#define CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1  0x1070
#define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU   0x1074
#define CLK_CON_MUX_MUX_CLKCMU_AUD_NOC   0x1078
#define CLK_CON_MUX_MUX_CLKCMU_BRP_NOC   0x107c
#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0   0x1080
#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1   0x1084
#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2   0x1088
#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3   0x108c
#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4   0x1090
#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5   0x1094
#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6   0x1098
#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7   0x109c
#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST  0x10a0
#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM  0x10a4
#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU  0x10a8
#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF  0x10ac
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC  0x10b0
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP  0x10b4
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH  0x10b8
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH  0x10bc
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH  0x10c0
#define CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY  0x10c4
#define CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC   0x10c8
#define CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU  0x10cc
#define CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC  0x10d0
#define CLK_CON_MUX_MUX_CLKCMU_DNC_NOC   0x10d4
#define CLK_CON_MUX_MUX_CLKCMU_DPUB   0x10d8
#define CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT   0x10dc
#define CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM  0x10e0
#define CLK_CON_MUX_MUX_CLKCMU_DPUF   0x10e4
#define CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT   0x10e8
#define CLK_CON_MUX_MUX_CLKCMU_DSP_NOC   0x10f8
#define CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH  0x10fc
#define CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP   0x1100
#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH  0x1104
#define CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC   0x110c
#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC  0x1114
#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC  0x1118
#define CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC   0x111c
#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD  0x1120
#define CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD  0x1124
#define CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC   0x1128
#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE  0x112c
#define CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD  0x1130
#define CLK_CON_MUX_MUX_CLKCMU_LME_LME   0x1134
#define CLK_CON_MUX_MUX_CLKCMU_LME_NOC   0x1138
#define CLK_CON_MUX_MUX_CLKCMU_M2M_NOC   0x1140
#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC  0x1148
#define CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC   0x114c
#define CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0  0x1150
#define CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD   0x1154
#define CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1  0x1158
#define CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP   0x115c
#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH  0x1160
#define CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC  0x1164
#define CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC  0x1168
#define CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0  0x116c
#define CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1  0x1170
#define CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC  0x1174
#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0  0x1178
#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1  0x117c
#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC  0x1180
#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0  0x1184
#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1  0x1188
#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC  0x118c
#define CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0  0x1190
#define CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1  0x1194
#define CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC  0x1198
#define CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC  0x119c
#define CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC  0x11a0
#define CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC   0x11a8
#define CLK_CON_MUX_MUX_CLKCMU_SSP_NOC   0x11ac
#define CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC   0x11b0
#define CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC   0x11b4
#define CLK_CON_MUX_MUX_CMU_CMUREF   0x11b8
#define CLK_CON_MUX_MUX_CP_HISPEEDY_CLK   0x11bc
#define CLK_CON_MUX_MUX_CP_SHARED0_CLK   0x11c0
#define CLK_CON_MUX_MUX_CP_SHARED1_CLK   0x11c4
#define CLK_CON_MUX_MUX_CP_SHARED2_CLK   0x11c8
#define CLK_CON_MUX_CLKCMU_M2M_FRC   0x11cc
#define CLK_CON_MUX_CLKCMU_MCSC_MCSC   0x11d0
#define CLK_CON_MUX_CLKCMU_MCSC_NOC   0x11d4
#define CLK_CON_MUX_MUX_CLKCMU_M2M_FRC   0x11d8
#define CLK_CON_MUX_MUX_CLKCMU_UFS_NOC   0x11dc
#define CLK_CON_DIV_CLKCMU_ALIVE_NOC   0x1800
#define CLK_CON_DIV_CLKCMU_AUD_NOC   0x1804
#define CLK_CON_DIV_CLKCMU_BRP_NOC   0x1808
#define CLK_CON_DIV_CLKCMU_CMU_BOOST   0x180c
#define CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM  0x1810
#define CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU  0x1814
#define CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF  0x1818
#define CLK_CON_DIV_CLKCMU_CPUCL0_NOCP   0x181c
#define CLK_CON_DIV_CLKCMU_CSIS_DCPHY   0x1820
#define CLK_CON_DIV_CLKCMU_CSIS_NOC   0x1824
#define CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU   0x1828
#define CLK_CON_DIV_CLKCMU_CSTAT_NOC   0x182c
#define CLK_CON_DIV_CLKCMU_DPUB_DSIM   0x1830
#define CLK_CON_DIV_CLKCMU_LME_LME   0x1834
#define CLK_CON_DIV_CLKCMU_G3D_NOCP   0x1838
#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC   0x1840
#define CLK_CON_DIV_CLKCMU_HSI0_DPOSC   0x1844
#define CLK_CON_DIV_CLKCMU_HSI0_NOC   0x1848
#define CLK_CON_DIV_CLKCMU_HSI0_USB32DRD  0x184c
#define CLK_CON_DIV_CLKCMU_HSI1_NOC   0x1850
#define CLK_CON_DIV_CLKCMU_HSI1_PCIE   0x1854
#define CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD   0x1858
#define CLK_CON_DIV_CLKCMU_LME_NOC   0x1860
#define CLK_CON_DIV_CLKCMU_MFC0_MFC0   0x1874
#define CLK_CON_DIV_CLKCMU_MFC0_WFD   0x1878
#define CLK_CON_DIV_CLKCMU_MFC1_MFC1   0x187c
#define CLK_CON_DIV_CLKCMU_MIF_NOCP   0x1880
#define CLK_CON_DIV_CLKCMU_NOCL1B_NOC1   0x1884
#define CLK_CON_DIV_CLKCMU_PERIC0_IP0   0x1888
#define CLK_CON_DIV_CLKCMU_PERIC0_IP1   0x188c
#define CLK_CON_DIV_CLKCMU_PERIC0_NOC   0x1890
#define CLK_CON_DIV_CLKCMU_PERIC1_IP0   0x1894
#define CLK_CON_DIV_CLKCMU_PERIC1_IP1   0x1898
#define CLK_CON_DIV_CLKCMU_PERIC1_NOC   0x189c
#define CLK_CON_DIV_CLKCMU_PERIC2_IP0   0x18a0
#define CLK_CON_DIV_CLKCMU_PERIC2_IP1   0x18a4
#define CLK_CON_DIV_CLKCMU_PERIC2_NOC   0x18a8
#define CLK_CON_DIV_CLKCMU_PERIS_GIC   0x18ac
#define CLK_CON_DIV_CLKCMU_PERIS_NOC   0x18b0
#define CLK_CON_DIV_CLKCMU_SSP_NOC   0x18b8
#define CLK_CON_DIV_CLKCMU_VTS_DMIC   0x18bc
#define CLK_CON_DIV_CLKCMU_YUVP_NOC   0x18c0
#define CLK_CON_DIV_CP_SHARED1_CLK   0x18c4
#define CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0  0x18c8
#define CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM  0x18cc
#define CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1  0x18d0
#define CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM  0x18d4
#define CLK_CON_DIV_DIV_CLKCMU_AUD_CPU   0x18d8
#define CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM  0x18dc
#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0   0x18e0
#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1   0x18e4
#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2   0x18e8
#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3   0x18ec
#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4   0x18f0
#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5   0x18f4
#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6   0x18f8
#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7   0x18fc
#define CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC  0x1900
#define CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM 0x1904
#define CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH  0x1908
#define CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM  0x190c
#define CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH  0x1910
#define CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM  0x1914
#define CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH  0x1918
#define CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM  0x191c
#define CLK_CON_DIV_DIV_CLKCMU_DNC_NOC   0x1920
#define CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM  0x1924
#define CLK_CON_DIV_DIV_CLKCMU_DPUB   0x1928
#define CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT   0x192c
#define CLK_CON_DIV_DIV_CLKCMU_DPUF   0x1930
#define CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT   0x1934
#define CLK_CON_DIV_DIV_CLKCMU_DSP_NOC   0x1940
#define CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM  0x1944
#define CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH  0x1948
#define CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM  0x194c
#define CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH  0x1950
#define CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM  0x1954
#define CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC   0x1960
#define CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM  0x1964
#define CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD  0x1968
#define CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM  0x196c
#define CLK_CON_DIV_DIV_CLKCMU_M2M_NOC   0x1970
#define CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM  0x1974
#define CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC  0x1978
#define CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM  0x197c
#define CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC  0x1980
#define CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM  0x1984
#define CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0  0x1988
#define CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM  0x198c
#define CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC  0x1990
#define CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM  0x1994
#define CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC   0x1998
#define CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM  0x199c
#define CLK_CON_DIV_DIV_CP_HISPEEDY_CLK   0x19a0
#define CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM  0x19a4
#define CLK_CON_DIV_DIV_CP_SHARED0_CLK   0x19a8
#define CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM  0x19ac
#define CLK_CON_DIV_DIV_CP_SHARED2_CLK   0x19b0
#define CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM  0x19b4
#define CLK_CON_DIV_CLKCMU_UFS_NOC   0x19b8
#define CLK_CON_DIV_DIV_CLKCMU_M2M_FRC   0x19bc
#define CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM  0x19c0
#define CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC  0x19c4
#define CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM  0x19c8
#define CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC   0x19cc
#define CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM  0x19d0
#define CLK_CON_GAT_CLKCMU_MIF01_SWITCH   0x2000
#define CLK_CON_GAT_CLKCMU_MIF23_SWITCH   0x2004
#define CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC  0x200c
#define CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0  0x2010
#define CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM  0x2014
#define CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1  0x2018
#define CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM  0x201c
#define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU   0x2020
#define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM  0x2024
#define CLK_CON_GAT_GATE_CLKCMU_AUD_NOC   0x2028
#define CLK_CON_GAT_GATE_CLKCMU_BRP_NOC   0x202c
#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0  0x2030
#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1  0x2034
#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2  0x2038
#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3  0x203c
#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4  0x2040
#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5  0x2044
#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6  0x2048
#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7  0x204c
#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST  0x2050
#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM  0x2054
#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU  0x2058
#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF 0x205c
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC  0x2060
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM 0x2064
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP  0x2068
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH  0x206c
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM 0x2070
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH  0x2074
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM 0x2078
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH  0x207c
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM 0x2080
#define CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY  0x2084
#define CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC  0x2088
#define CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU  0x208c
#define CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC  0x2090
#define CLK_CON_GAT_GATE_CLKCMU_DNC_NOC   0x2094
#define CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM  0x2098
#define CLK_CON_GAT_GATE_CLKCMU_DPUB   0x209c
#define CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT  0x20a0
#define CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM  0x20a4
#define CLK_CON_GAT_GATE_CLKCMU_DPUF   0x20a8
#define CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT  0x20ac
#define CLK_CON_GAT_GATE_CLKCMU_DSP_NOC   0x20bc
#define CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM  0x20c0
#define CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH  0x20c4
#define CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM  0x20c8
#define CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP  0x20cc
#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH  0x20d0
#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM  0x20d4
#define CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC  0x20e0
#define CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM  0x20e4
#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC  0x20ec
#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC  0x20f0
#define CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC  0x20f4
#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD  0x20f8
#define CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD  0x20fc
#define CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM  0x2100
#define CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC  0x2104
#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE  0x2108
#define CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD  0x210c
#define CLK_CON_GAT_GATE_CLKCMU_LME_LME   0x2110
#define CLK_CON_GAT_GATE_CLKCMU_LME_NOC   0x2114
#define CLK_CON_GAT_GATE_CLKCMU_M2M_NOC   0x2118
#define CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM  0x211c
#define CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0  0x212c
#define CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD  0x2130
#define CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1  0x2134
#define CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP  0x2138
#define CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC  0x213c
#define CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM  0x2140
#define CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC  0x2144
#define CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM  0x2148
#define CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0  0x214c
#define CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM  0x2150
#define CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1  0x2154
#define CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC  0x2158
#define CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM  0x215c
#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0  0x2160
#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1  0x2164
#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC  0x2168
#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0  0x216c
#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1  0x2170
#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC  0x2174
#define CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0  0x2178
#define CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1  0x217c
#define CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC  0x2180
#define CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC  0x2184
#define CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC  0x2188
#define CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC  0x2190
#define CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM  0x2194
#define CLK_CON_GAT_GATE_CLKCMU_SSP_NOC   0x2198
#define CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC  0x219c
#define CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC  0x21a0
#define CLK_CON_GAT_GATE_CP_HISPEEDY_CLK  0x21a4
#define CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM  0x21a8
#define CLK_CON_GAT_GATE_CP_SHARED0_CLK   0x21ac
#define CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM  0x21b0
#define CLK_CON_GAT_GATE_CP_SHARED1_CLK   0x21b4
#define CLK_CON_GAT_GATE_CP_SHARED2_CLK   0x21b8
#define CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM  0x21bc
#define CLK_CON_GAT_GATE_CLKCMU_UFS_NOC   0x21c0
#define CLK_CON_GAT_GATE_CLKCMU_M2M_FRC   0x21c4
#define CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM  0x21c8
#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC  0x21cc
#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM  0x21d0
#define CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC  0x21d4
#define CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM  0x21d8

static const unsigned long top_clk_regs[] __initconst = {
 PLL_LOCKTIME_PLL_MMC,
 PLL_LOCKTIME_PLL_SHARED0,
 PLL_LOCKTIME_PLL_SHARED1,
 PLL_LOCKTIME_PLL_SHARED2,
 PLL_LOCKTIME_PLL_SHARED3,
 PLL_LOCKTIME_PLL_SHARED4,
 PLL_LOCKTIME_PLL_SHARED_MIF,
 PLL_CON3_PLL_MMC,
 PLL_CON8_PLL_MMC,
 PLL_CON3_PLL_SHARED0,
 PLL_CON8_PLL_SHARED0,
 PLL_CON3_PLL_SHARED1,
 PLL_CON8_PLL_SHARED1,
 PLL_CON3_PLL_SHARED2,
 PLL_CON8_PLL_SHARED2,
 PLL_CON3_PLL_SHARED3,
 PLL_CON8_PLL_SHARED3,
 PLL_CON3_PLL_SHARED4,
 PLL_CON8_PLL_SHARED4,
 PLL_CON3_PLL_SHARED_MIF,
 PLL_CON8_PLL_SHARED_MIF,
 PLL_CON0_MUX_CP_MPLL_CLK_D2_USER,
 PLL_CON1_MUX_CP_MPLL_CLK_D2_USER,
 PLL_CON0_MUX_CP_MPLL_CLK_USER,
 PLL_CON1_MUX_CP_MPLL_CLK_USER,
 CLK_CON_MUX_CLKCMU_AUD_AUDIF0,
 CLK_CON_MUX_CLKCMU_AUD_AUDIF1,
 CLK_CON_MUX_CLKCMU_AUD_CPU,
 CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC,
 CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH,
 CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH,
 CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH,
 CLK_CON_MUX_CLKCMU_DNC_NOC,
 CLK_CON_MUX_CLKCMU_DPUB_NOC,
 CLK_CON_MUX_CLKCMU_DPUF_NOC,
 CLK_CON_MUX_CLKCMU_DSP_NOC,
 CLK_CON_MUX_CLKCMU_DSU_SWITCH,
 CLK_CON_MUX_CLKCMU_G3D_SWITCH,
 CLK_CON_MUX_CLKCMU_GNPU_NOC,
 CLK_CON_MUX_CLKCMU_UFS_MMC_CARD,
 CLK_CON_MUX_CLKCMU_M2M_NOC,
 CLK_CON_MUX_CLKCMU_NOCL0_NOC,
 CLK_CON_MUX_CLKCMU_NOCL1A_NOC,
 CLK_CON_MUX_CLKCMU_NOCL1B_NOC0,
 CLK_CON_MUX_CLKCMU_NOCL1C_NOC,
 CLK_CON_MUX_CLKCMU_SDMA_NOC,
 CLK_CON_MUX_CP_HISPEEDY_CLK,
 CLK_CON_MUX_CP_SHARED0_CLK,
 CLK_CON_MUX_CP_SHARED2_CLK,
 CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC,
 CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0,
 CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1,
 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
 CLK_CON_MUX_MUX_CLKCMU_AUD_NOC,
 CLK_CON_MUX_MUX_CLKCMU_BRP_NOC,
 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM,
 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU,
 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF,
 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC,
 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP,
 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
 CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY,
 CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC,
 CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU,
 CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC,
 CLK_CON_MUX_MUX_CLKCMU_DNC_NOC,
 CLK_CON_MUX_MUX_CLKCMU_DPUB,
 CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT,
 CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM,
 CLK_CON_MUX_MUX_CLKCMU_DPUF,
 CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT,
 CLK_CON_MUX_MUX_CLKCMU_DSP_NOC,
 CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH,
 CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP,
 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
 CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC,
 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC,
 CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC,
 CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD,
 CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD,
 CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC,
 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
 CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD,
 CLK_CON_MUX_MUX_CLKCMU_LME_LME,
 CLK_CON_MUX_MUX_CLKCMU_LME_NOC,
 CLK_CON_MUX_MUX_CLKCMU_M2M_NOC,
 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
 CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC,
 CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0,
 CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD,
 CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1,
 CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP,
 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
 CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC,
 CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC,
 CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0,
 CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1,
 CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC,
 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0,
 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1,
 CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC,
 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0,
 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1,
 CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC,
 CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0,
 CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1,
 CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC,
 CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC,
 CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC,
 CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC,
 CLK_CON_MUX_MUX_CLKCMU_SSP_NOC,
 CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC,
 CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC,
 CLK_CON_MUX_MUX_CMU_CMUREF,
 CLK_CON_MUX_MUX_CP_HISPEEDY_CLK,
 CLK_CON_MUX_MUX_CP_SHARED0_CLK,
 CLK_CON_MUX_MUX_CP_SHARED1_CLK,
 CLK_CON_MUX_MUX_CP_SHARED2_CLK,
 CLK_CON_MUX_CLKCMU_M2M_FRC,
 CLK_CON_MUX_CLKCMU_MCSC_MCSC,
 CLK_CON_MUX_CLKCMU_MCSC_NOC,
 CLK_CON_MUX_MUX_CLKCMU_M2M_FRC,
 CLK_CON_MUX_MUX_CLKCMU_UFS_NOC,
 CLK_CON_DIV_CLKCMU_ALIVE_NOC,
 CLK_CON_DIV_CLKCMU_AUD_NOC,
 CLK_CON_DIV_CLKCMU_BRP_NOC,
 CLK_CON_DIV_CLKCMU_CMU_BOOST,
 CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM,
 CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU,
 CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF,
 CLK_CON_DIV_CLKCMU_CPUCL0_NOCP,
 CLK_CON_DIV_CLKCMU_CSIS_DCPHY,
 CLK_CON_DIV_CLKCMU_CSIS_NOC,
 CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU,
 CLK_CON_DIV_CLKCMU_CSTAT_NOC,
 CLK_CON_DIV_CLKCMU_DPUB_DSIM,
 CLK_CON_DIV_CLKCMU_LME_LME,
 CLK_CON_DIV_CLKCMU_G3D_NOCP,
 CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
 CLK_CON_DIV_CLKCMU_HSI0_DPOSC,
 CLK_CON_DIV_CLKCMU_HSI0_NOC,
 CLK_CON_DIV_CLKCMU_HSI0_USB32DRD,
 CLK_CON_DIV_CLKCMU_HSI1_NOC,
 CLK_CON_DIV_CLKCMU_HSI1_PCIE,
 CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD,
 CLK_CON_DIV_CLKCMU_LME_NOC,
 CLK_CON_DIV_CLKCMU_MFC0_MFC0,
 CLK_CON_DIV_CLKCMU_MFC0_WFD,
 CLK_CON_DIV_CLKCMU_MFC1_MFC1,
 CLK_CON_DIV_CLKCMU_MIF_NOCP,
 CLK_CON_DIV_CLKCMU_NOCL1B_NOC1,
 CLK_CON_DIV_CLKCMU_PERIC0_IP0,
 CLK_CON_DIV_CLKCMU_PERIC0_IP1,
 CLK_CON_DIV_CLKCMU_PERIC0_NOC,
 CLK_CON_DIV_CLKCMU_PERIC1_IP0,
 CLK_CON_DIV_CLKCMU_PERIC1_IP1,
 CLK_CON_DIV_CLKCMU_PERIC1_NOC,
 CLK_CON_DIV_CLKCMU_PERIC2_IP0,
 CLK_CON_DIV_CLKCMU_PERIC2_IP1,
 CLK_CON_DIV_CLKCMU_PERIC2_NOC,
 CLK_CON_DIV_CLKCMU_PERIS_GIC,
 CLK_CON_DIV_CLKCMU_PERIS_NOC,
 CLK_CON_DIV_CLKCMU_SSP_NOC,
 CLK_CON_DIV_CLKCMU_VTS_DMIC,
 CLK_CON_DIV_CLKCMU_YUVP_NOC,
 CLK_CON_DIV_CP_SHARED1_CLK,
 CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0,
 CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM,
 CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1,
 CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM,
 CLK_CON_DIV_DIV_CLKCMU_AUD_CPU,
 CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM,
 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0,
 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1,
 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2,
 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3,
 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4,
 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5,
 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6,
 CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7,
 CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC,
 CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM,
 CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH,
 CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM,
 CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH,
 CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM,
 CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH,
 CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM,
 CLK_CON_DIV_DIV_CLKCMU_DNC_NOC,
 CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM,
 CLK_CON_DIV_DIV_CLKCMU_DPUB,
 CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT,
 CLK_CON_DIV_DIV_CLKCMU_DPUF,
 CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT,
 CLK_CON_DIV_DIV_CLKCMU_DSP_NOC,
 CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM,
 CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH,
 CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM,
 CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH,
 CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM,
 CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC,
 CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM,
 CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD,
 CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM,
 CLK_CON_DIV_DIV_CLKCMU_M2M_NOC,
 CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM,
 CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC,
 CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM,
 CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC,
 CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM,
 CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0,
 CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM,
 CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC,
 CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM,
 CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC,
 CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM,
 CLK_CON_DIV_DIV_CP_HISPEEDY_CLK,
 CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM,
 CLK_CON_DIV_DIV_CP_SHARED0_CLK,
 CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM,
 CLK_CON_DIV_DIV_CP_SHARED2_CLK,
 CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM,
 CLK_CON_DIV_CLKCMU_UFS_NOC,
 CLK_CON_DIV_DIV_CLKCMU_M2M_FRC,
 CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM,
 CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC,
 CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM,
 CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC,
 CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM,
 CLK_CON_GAT_CLKCMU_MIF01_SWITCH,
 CLK_CON_GAT_CLKCMU_MIF23_SWITCH,
 CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC,
 CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0,
 CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM,
 CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1,
 CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM,
 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM,
 CLK_CON_GAT_GATE_CLKCMU_AUD_NOC,
 CLK_CON_GAT_GATE_CLKCMU_BRP_NOC,
 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM,
 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU,
 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF,
 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC,
 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM,
 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP,
 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM,
 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM,
 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM,
 CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY,
 CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC,
 CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU,
 CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC,
 CLK_CON_GAT_GATE_CLKCMU_DNC_NOC,
 CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM,
 CLK_CON_GAT_GATE_CLKCMU_DPUB,
 CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT,
 CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM,
 CLK_CON_GAT_GATE_CLKCMU_DPUF,
 CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT,
 CLK_CON_GAT_GATE_CLKCMU_DSP_NOC,
 CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM,
 CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH,
 CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM,
 CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP,
 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM,
 CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC,
 CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM,
 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC,
 CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC,
 CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD,
 CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD,
 CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM,
 CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC,
 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
 CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD,
 CLK_CON_GAT_GATE_CLKCMU_LME_LME,
 CLK_CON_GAT_GATE_CLKCMU_LME_NOC,
 CLK_CON_GAT_GATE_CLKCMU_M2M_NOC,
 CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM,
 CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0,
 CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD,
 CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1,
 CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP,
 CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC,
 CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM,
 CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC,
 CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM,
 CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0,
 CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM,
 CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1,
 CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC,
 CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM,
 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0,
 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1,
 CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC,
 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0,
 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1,
 CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC,
 CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0,
 CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1,
 CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC,
 CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC,
 CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC,
 CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC,
 CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM,
 CLK_CON_GAT_GATE_CLKCMU_SSP_NOC,
 CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC,
 CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC,
 CLK_CON_GAT_GATE_CP_HISPEEDY_CLK,
 CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM,
 CLK_CON_GAT_GATE_CP_SHARED0_CLK,
 CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM,
 CLK_CON_GAT_GATE_CP_SHARED1_CLK,
 CLK_CON_GAT_GATE_CP_SHARED2_CLK,
 CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM,
 CLK_CON_GAT_GATE_CLKCMU_UFS_NOC,
 CLK_CON_GAT_GATE_CLKCMU_M2M_FRC,
 CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM,
 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM,
 CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC,
 CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM,
};

/* List of parent clocks for Muxes in CMU_TOP */
PNAME(mout_cmu_cp_mpll_clk_d2_user_parents) = { "oscclk" };
PNAME(mout_cmu_cp_mpll_clk_user_parents) = { "oscclk" };
PNAME(mout_cmu_aud_audif0_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "mout_cmu_cp_mpll_clk_d2_user",
          "oscclk", "oscclk",
          "oscclk" };
PNAME(mout_cmu_aud_audif1_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "mout_cmu_cp_mpll_clk_d2_user",
          "oscclk", "oscclk",
          "oscclk" };
PNAME(mout_cmu_aud_cpu_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "mout_cmu_cp_mpll_clk_d2_user" };
PNAME(mout_cmu_cpucl0_dbg_noc_p)  = { "dout_shared2_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2" };
PNAME(mout_cmu_cpucl0_switch_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "oscclk", "oscclk" };
PNAME(mout_cmu_cpucl1_switch_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "oscclk", "oscclk" };
PNAME(mout_cmu_cpucl2_switch_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "oscclk", "oscclk" };
PNAME(mout_cmu_dnc_noc_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "oscclk" };
PNAME(mout_cmu_dpub_noc_p)   = { "dout_cmu_div_dpub",
          "dout_cmu_div_dpub_alt"};
PNAME(mout_cmu_dpuf_noc_p)   = { "dout_cmu_div_dpuf",
          "dout_cmu_div_dpuf_alt" };
PNAME(mout_cmu_dsp_noc_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "oscclk" };
PNAME(mout_cmu_dsu_switch_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "oscclk", "oscclk" };
PNAME(mout_cmu_g3d_switch_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2" };
PNAME(mout_cmu_gnpu_noc_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "oscclk" };
PNAME(mout_cmu_ufs_mmc_card_p)   = { "oscclk",
          "dout_shared2_div1",
          "dout_mmc_div1",
          "dout_shared0_div2" };
PNAME(mout_cmu_m2m_noc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_nocl0_noc_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "mout_cmu_cp_mpll_clk_d2_user",
          "dout_shared_mif_div2" };
PNAME(mout_cmu_nocl1a_noc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_nocl1b_noc0_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_nocl1c_noc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_sdma_noc_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "oscclk" };
PNAME(mout_cmu_cp_hispeedy_clk_p)  = { "dout_shared2_div1",
          "dout_shared3_div1" };
PNAME(mout_cmu_cp_shared0_clk_p)  = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1" };
PNAME(mout_cmu_cp_shared2_clk_p)  = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared1_div2" };
PNAME(mout_cmu_mux_alive_noc_p)   = { "dout_shared0_div2",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_aud_audif0_p)  = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "mout_cmu_cp_mpll_clk_d2_user",
          "oscclk", "oscclk",
          "oscclk" };
PNAME(mout_cmu_mux_aud_audif1_p)  = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "mout_cmu_cp_mpll_clk_d2_user",
          "oscclk", "oscclk",
          "oscclk" };
PNAME(mout_cmu_mux_aud_cpu_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "mout_cmu_cp_mpll_clk_d2_user" };
PNAME(mout_cmu_mux_aud_noc_p)   = { "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "mout_cmu_cp_mpll_clk_d2_user",
          "oscclk", "oscclk" };
PNAME(mout_cmu_mux_brp_noc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_cis_clk0_p)   = { "oscclk",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_cis_clk1_p)   = { "oscclk",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_cis_clk2_p)   = { "oscclk",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_cis_clk3_p)   = { "oscclk",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_cis_clk4_p)   = { "oscclk",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_cis_clk5_p)   = { "oscclk",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_cis_clk6_p)   = { "oscclk",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_cis_clk7_p)   = { "oscclk",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_cmu_boost_p)   = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_cmu_boost_cam_p)  = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_cmu_boost_cpu_p)  = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_cmu_boost_mif_p)  = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_cpucl0_dbg_noc_p)  = { "dout_shared2_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2" };
PNAME(mout_cmu_mux_cpucl0_nocp_p)  = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_cpucl0_switch_p)  = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "oscclk", "oscclk" };
PNAME(mout_cmu_mux_cpucl1_switch_p)  = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "oscclk", "oscclk" };
PNAME(mout_cmu_mux_cpucl2_switch_p)  = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "oscclk", "oscclk" };
PNAME(mout_cmu_mux_csis_dcphy_p)  = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_csis_noc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_csis_ois_mcu_p)  = { "dout_shared0_div2",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_cstat_noc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_dnc_noc_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "oscclk" };
PNAME(mout_cmu_mux_dpub_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "oscclk", "oscclk" };
PNAME(mout_cmu_mux_dpub_alt_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "oscclk", "oscclk" };
PNAME(mout_cmu_mux_dpub_dsim_p)   = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2" };
PNAME(mout_cmu_mux_dpuf_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "oscclk", "oscclk" };
PNAME(mout_cmu_mux_dpuf_alt_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "oscclk", "oscclk" };
PNAME(mout_cmu_mux_dsp_noc_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "oscclk" };
PNAME(mout_cmu_mux_dsu_switch_p)  = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "oscclk", "oscclk" };
PNAME(mout_cmu_mux_g3d_nocp_p)   = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_g3d_switch_p)  = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_gnpu_noc_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "oscclk" };
PNAME(mout_cmu_mux_hsi0_dpgtc_p)  = { "oscclk",
          "dout_shared0_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_hsi0_dposc_p)  = { "oscclk",
          "dout_shared2_div1" };
PNAME(mout_cmu_mux_hsi0_noc_p)   = { "dout_shared0_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_hsi0_usb32drd_p)  = { "oscclk",
          "dout_shared0_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_ufs_mmc_card_p)  = { "oscclk",
          "dout_shared2_div1",
          "dout_mmc_div1",
          "dout_shared0_div2" };
PNAME(mout_cmu_mux_hsi1_noc_p)   = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_hsi1_pcie_p)   = { "oscclk",
          "dout_shared2_div1" };
PNAME(mout_cmu_mux_ufs_ufs_embd_p)  = { "oscclk",
          "dout_shared0_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_lme_lme_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_lme_noc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_m2m_noc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_mcsc_mcsc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_mcsc_noc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_mfc0_mfc0_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_mfc0_wfd_p)   = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "dout_shared4_div2",
          "oscclk", "oscclk",
          "oscclk" };
PNAME(mout_cmu_mux_mfc1_mfc1_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_mif_nocp_p)   = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_mif_switch_p)  = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "mout_cmu_cp_mpll_clk_user",
          "dout_shared_mif_div1" };
PNAME(mout_cmu_mux_nocl0_noc_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "mout_cmu_cp_mpll_clk_d2_user",
          "dout_shared_mif_div2" };
PNAME(mout_cmu_mux_nocl1a_noc_p)  = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_nocl1b_noc0_p)  = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_nocl1b_noc1_p)  = { "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_nocl1c_noc_p)  = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_peric0_ip0_p)  = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_peric0_ip1_p)  = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_peric0_noc_p)  = { "dout_shared0_div2",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_peric1_ip0_p)  = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_peric1_ip1_p)  = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_peric1_noc_p)  = { "dout_shared0_div2",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_peric2_ip0_p)  = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_peric2_ip1_p)  = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_peric2_noc_p)  = { "dout_shared0_div2",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_peris_gic_p)   = { "dout_shared0_div2",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_peris_noc_p)   = { "dout_shared0_div2",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_sdma_noc_p)   = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "oscclk" };
PNAME(mout_cmu_mux_ssp_noc_p)   = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };
PNAME(mout_cmu_mux_vts_dmic_p)   = { "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2" };
PNAME(mout_cmu_mux_yuvp_noc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_cmu_cmuref_p)  = { "oscclk",
          "dout_cmu_boost" };
PNAME(mout_cmu_mux_cp_hispeedy_clk_p)  = { "dout_shared2_div1",
          "dout_shared3_div1" };
PNAME(mout_cmu_mux_cp_shared0_clk_p)  = { "dout_shared0_div1",
          "dout_shared1_div1",
          "dout_shared2_div1",
          "dout_shared3_div1" };
PNAME(mout_cmu_mux_cp_shared1_clk_p)  = { "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2" };
PNAME(mout_cmu_mux_cp_shared2_clk_p)  = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared1_div2" };
PNAME(mout_cmu_m2m_frc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mcsc_mcsc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mcsc_noc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_m2m_frc_p)   = { "dout_shared2_div1",
          "dout_shared3_div1",
          "dout_shared4_div1",
          "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared3_div2",
          "oscclk" };
PNAME(mout_cmu_mux_ufs_noc_p)   = { "dout_shared0_div2",
          "dout_shared1_div2",
          "dout_shared2_div2",
          "dout_shared4_div2" };

static const struct samsung_pll_clock top_pll_clks[] __initconst = {
 PLL(pll_4311, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
     PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
 PLL(pll_4311, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
     PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
 PLL(pll_4311, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
     PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
 PLL(pll_4311, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
     PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
 PLL(pll_4311, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
     PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
 PLL(pll_4311, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
     PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
 PLL(pll_4311, CLK_FOUT_SHARED_MIF_PLL, "fout_shared_mif_pll", "oscclk",
     PLL_LOCKTIME_PLL_SHARED_MIF, PLL_CON3_PLL_SHARED_MIF, NULL),
};

static const struct samsung_mux_clock top_mux_clks[] __initconst = {
 MUX(CLK_MOUT_CMU_CP_MPLL_CLK_D2_USER, "mout_cmu_cp_mpll_clk_d2_user",
     mout_cmu_cp_mpll_clk_d2_user_parents,
     PLL_CON0_MUX_CP_MPLL_CLK_D2_USER, 4, 1),
 MUX(CLK_MOUT_CMU_CP_MPLL_CLK_USER, "mout_cmu_cp_mpll_clk_user",
     mout_cmu_cp_mpll_clk_user_parents, PLL_CON0_MUX_CP_MPLL_CLK_USER,
     4, 1),
 MUX(CLK_MOUT_CMU_AUD_AUDIF0, "mout_cmu_aud_audif0",
     mout_cmu_aud_audif0_p, CLK_CON_MUX_CLKCMU_AUD_AUDIF0, 0, 3),
 MUX(CLK_MOUT_CMU_AUD_AUDIF1, "mout_cmu_aud_audif1",
     mout_cmu_aud_audif1_p, CLK_CON_MUX_CLKCMU_AUD_AUDIF1, 0, 3),
 MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu", mout_cmu_aud_cpu_p,
     CLK_CON_MUX_CLKCMU_AUD_CPU, 0, 3),
 MUX(CLK_MOUT_CMU_CPUCL0_DBG_NOC, "mout_cmu_cpucl0_dbg_noc",
     mout_cmu_cpucl0_dbg_noc_p, CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC,
     0, 2),
 MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch",
     mout_cmu_cpucl0_switch_p, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH, 0, 3),
 MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch",
     mout_cmu_cpucl1_switch_p, CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH, 0, 3),
 MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch",
     mout_cmu_cpucl2_switch_p, CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH, 0, 3),
 MUX(CLK_MOUT_CMU_DNC_NOC, "mout_cmu_dnc_noc", mout_cmu_dnc_noc_p,
     CLK_CON_MUX_CLKCMU_DNC_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_DPUB_NOC, "mout_cmu_dpub_noc", mout_cmu_dpub_noc_p,
     CLK_CON_MUX_CLKCMU_DPUB_NOC, 0, 1),
 MUX(CLK_MOUT_CMU_DPUF_NOC, "mout_cmu_dpuf_noc", mout_cmu_dpuf_noc_p,
     CLK_CON_MUX_CLKCMU_DPUF_NOC, 0, 1),
 MUX(CLK_MOUT_CMU_DSP_NOC, "mout_cmu_dsp_noc", mout_cmu_dsp_noc_p,
     CLK_CON_MUX_CLKCMU_DSP_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_DSU_SWITCH, "mout_cmu_dsu_switch",
     mout_cmu_dsu_switch_p, CLK_CON_MUX_CLKCMU_DSU_SWITCH, 0, 3),
 MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch",
     mout_cmu_g3d_switch_p, CLK_CON_MUX_CLKCMU_G3D_SWITCH, 0, 3),
 MUX(CLK_MOUT_CMU_GNPU_NOC, "mout_cmu_gnpu_noc", mout_cmu_gnpu_noc_p,
     CLK_CON_MUX_CLKCMU_GNPU_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_UFS_MMC_CARD, "mout_cmu_ufs_mmc_card",
     mout_cmu_ufs_mmc_card_p, CLK_CON_MUX_CLKCMU_UFS_MMC_CARD, 0, 2),
 MUX(CLK_MOUT_CMU_M2M_NOC, "mout_cmu_m2m_noc", mout_cmu_m2m_noc_p,
     CLK_CON_MUX_CLKCMU_M2M_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_NOCL0_NOC, "mout_cmu_nocl0_noc", mout_cmu_nocl0_noc_p,
     CLK_CON_MUX_CLKCMU_NOCL0_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_NOCL1A_NOC, "mout_cmu_nocl1a_noc",
     mout_cmu_nocl1a_noc_p, CLK_CON_MUX_CLKCMU_NOCL1A_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_NOCL1B_NOC0, "mout_cmu_nocl1b_noc0",
     mout_cmu_nocl1b_noc0_p, CLK_CON_MUX_CLKCMU_NOCL1B_NOC0, 0, 3),
 MUX(CLK_MOUT_CMU_NOCL1C_NOC, "mout_cmu_nocl1c_noc",
     mout_cmu_nocl1c_noc_p, CLK_CON_MUX_CLKCMU_NOCL1C_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_SDMA_NOC, "mout_cmu_sdma_noc", mout_cmu_sdma_noc_p,
     CLK_CON_MUX_CLKCMU_SDMA_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_CP_HISPEEDY_CLK, "mout_cmu_cp_hispeedy_clk",
     mout_cmu_cp_hispeedy_clk_p, CLK_CON_MUX_CP_HISPEEDY_CLK, 0, 1),
 MUX(CLK_MOUT_CMU_CP_SHARED0_CLK, "mout_cmu_cp_shared0_clk",
     mout_cmu_cp_shared0_clk_p, CLK_CON_MUX_CP_SHARED0_CLK, 0, 2),
 MUX(CLK_MOUT_CMU_CP_SHARED2_CLK, "mout_cmu_cp_shared2_clk",
     mout_cmu_cp_shared2_clk_p, CLK_CON_MUX_CP_SHARED2_CLK, 0, 2),
 MUX(CLK_MOUT_CMU_MUX_ALIVE_NOC, "mout_cmu_mux_alive_noc",
     mout_cmu_mux_alive_noc_p, CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC, 0, 1),
 MUX(CLK_MOUT_CMU_MUX_AUD_AUDIF0, "mout_cmu_mux_aud_audif0",
     mout_cmu_mux_aud_audif0_p, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0,
     0, 3),
 MUX(CLK_MOUT_CMU_MUX_AUD_AUDIF1, "mout_cmu_mux_aud_audif1",
     mout_cmu_mux_aud_audif1_p, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1,
     0, 3),
 MUX(CLK_MOUT_CMU_MUX_AUD_CPU, "mout_cmu_mux_aud_cpu",
     mout_cmu_mux_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_AUD_NOC, "mout_cmu_mux_aud_noc",
     mout_cmu_mux_aud_noc_p, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_BRP_NOC, "mout_cmu_mux_brp_noc",
     mout_cmu_mux_brp_noc_p, CLK_CON_MUX_MUX_CLKCMU_BRP_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_CIS_CLK0, "mout_cmu_mux_cis_clk0",
     mout_cmu_mux_cis_clk0_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 1),
 MUX(CLK_MOUT_CMU_MUX_CIS_CLK1, "mout_cmu_mux_cis_clk1",
     mout_cmu_mux_cis_clk1_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 1),
 MUX(CLK_MOUT_CMU_MUX_CIS_CLK2, "mout_cmu_mux_cis_clk2",
     mout_cmu_mux_cis_clk2_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 1),
 MUX(CLK_MOUT_CMU_MUX_CIS_CLK3, "mout_cmu_mux_cis_clk3",
     mout_cmu_mux_cis_clk3_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 1),
 MUX(CLK_MOUT_CMU_MUX_CIS_CLK4, "mout_cmu_mux_cis_clk4",
     mout_cmu_mux_cis_clk4_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 1),
 MUX(CLK_MOUT_CMU_MUX_CIS_CLK5, "mout_cmu_mux_cis_clk5",
     mout_cmu_mux_cis_clk5_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 1),
 MUX(CLK_MOUT_CMU_MUX_CIS_CLK6, "mout_cmu_mux_cis_clk6",
     mout_cmu_mux_cis_clk6_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 1),
 MUX(CLK_MOUT_CMU_MUX_CIS_CLK7, "mout_cmu_mux_cis_clk7",
     mout_cmu_mux_cis_clk7_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 1),
 MUX(CLK_MOUT_CMU_MUX_CMU_BOOST, "mout_cmu_mux_cmu_boost",
     mout_cmu_mux_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
 MUX(CLK_MOUT_CMU_MUX_CMU_BOOST_CAM, "mout_cmu_mux_cmu_boost_cam",
     mout_cmu_mux_cmu_boost_cam_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_CMU_BOOST_CPU, "mout_cmu_mux_cmu_boost_cpu",
     mout_cmu_mux_cmu_boost_cpu_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_CMU_BOOST_MIF, "mout_cmu_mux_cmu_boost_mif",
     mout_cmu_mux_cmu_boost_mif_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_CPUCL0_DBG_NOC, "mout_cmu_mux_cpucl0_dbg_noc",
     mout_cmu_mux_cpucl0_dbg_noc_p,
     CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC, 0, 2),
 MUX(CLK_MOUT_CMU_MUX_CPUCL0_NOCP, "mout_cmu_mux_cpucl0_nocp",
     mout_cmu_mux_cpucl0_nocp_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_CPUCL0_SWITCH, "mout_cmu_mux_cpucl0_switch",
     mout_cmu_mux_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
     0, 3),
 MUX(CLK_MOUT_CMU_MUX_CPUCL1_SWITCH, "mout_cmu_mux_cpucl1_switch",
     mout_cmu_mux_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
     0, 3),
 MUX(CLK_MOUT_CMU_MUX_CPUCL2_SWITCH, "mout_cmu_mux_cpucl2_switch",
     mout_cmu_mux_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
     0, 3),
 MUX(CLK_MOUT_CMU_MUX_CSIS_DCPHY, "mout_cmu_mux_csis_dcphy",
     mout_cmu_mux_csis_dcphy_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_CSIS_NOC, "mout_cmu_mux_csis_noc",
     mout_cmu_mux_csis_noc_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_CSIS_OIS_MCU, "mout_cmu_mux_csis_ois_mcu",
     mout_cmu_mux_csis_ois_mcu_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU,
     0, 1),
 MUX(CLK_MOUT_CMU_MUX_CSTAT_NOC, "mout_cmu_mux_cstat_noc",
     mout_cmu_mux_cstat_noc_p, CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_DNC_NOC, "mout_cmu_mux_dnc_noc",
     mout_cmu_mux_dnc_noc_p, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_DPUB, "mout_cmu_mux_dpub", mout_cmu_mux_dpub_p,
     CLK_CON_MUX_MUX_CLKCMU_DPUB, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_DPUB_ALT, "mout_cmu_mux_dpub_alt",
     mout_cmu_mux_dpub_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_DPUB_DSIM, "mout_cmu_mux_dpub_dsim",
     mout_cmu_mux_dpub_dsim_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 0, 2),
 MUX(CLK_MOUT_CMU_MUX_DPUF, "mout_cmu_mux_dpuf", mout_cmu_mux_dpuf_p,
     CLK_CON_MUX_MUX_CLKCMU_DPUF, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_DPUF_ALT, "mout_cmu_mux_dpuf_alt",
     mout_cmu_mux_dpuf_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_DSP_NOC, "mout_cmu_mux_dsp_noc",
     mout_cmu_mux_dsp_noc_p, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_DSU_SWITCH, "mout_cmu_mux_dsu_switch",
     mout_cmu_mux_dsu_switch_p, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH,
     0, 3),
 MUX(CLK_MOUT_CMU_MUX_G3D_NOCP, "mout_cmu_mux_g3d_nocp",
     mout_cmu_mux_g3d_nocp_p, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 0, 2),
 MUX(CLK_MOUT_CMU_MUX_G3D_SWITCH, "mout_cmu_mux_g3d_switch",
     mout_cmu_mux_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
     0, 3),
 MUX(CLK_MOUT_CMU_MUX_GNPU_NOC, "mout_cmu_mux_gnpu_noc",
     mout_cmu_mux_gnpu_noc_p, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_HSI0_DPGTC, "mout_cmu_mux_hsi0_dpgtc",
     mout_cmu_mux_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_HSI0_DPOSC, "mout_cmu_mux_hsi0_dposc",
     mout_cmu_mux_hsi0_dposc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC,
     0, 1),
 MUX(CLK_MOUT_CMU_MUX_HSI0_NOC, "mout_cmu_mux_hsi0_noc",
     mout_cmu_mux_hsi0_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0, 2),
 MUX(CLK_MOUT_CMU_MUX_HSI0_USB32DRD, "mout_cmu_mux_hsi0_usb32drd",
     mout_cmu_mux_hsi0_usb32drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_UFS_MMC_CARD, "mout_cmu_mux_ufs_mmc_card",
     mout_cmu_mux_ufs_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_HSI1_NOC, "mout_cmu_mux_hsi1_noc",
     mout_cmu_mux_hsi1_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC, 0, 2),
 MUX(CLK_MOUT_CMU_MUX_HSI1_PCIE, "mout_cmu_mux_hsi1_pcie",
     mout_cmu_mux_hsi1_pcie_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1),
 MUX(CLK_MOUT_CMU_MUX_UFS_UFS_EMBD, "mout_cmu_mux_ufs_ufs_embd",
     mout_cmu_mux_ufs_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_LME_LME, "mout_cmu_mux_lme_lme",
     mout_cmu_mux_lme_lme_p, CLK_CON_MUX_MUX_CLKCMU_LME_LME, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_LME_NOC, "mout_cmu_mux_lme_noc",
     mout_cmu_mux_lme_noc_p, CLK_CON_MUX_MUX_CLKCMU_LME_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_M2M_NOC, "mout_cmu_mux_m2m_noc",
     mout_cmu_mux_m2m_noc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_MCSC_MCSC, "mout_cmu_mux_mcsc_mcsc",
     mout_cmu_mux_mcsc_mcsc_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_MCSC_NOC, "mout_cmu_mux_mcsc_noc",
     mout_cmu_mux_mcsc_noc_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_MFC0_MFC0, "mout_cmu_mux_mfc0_mfc0",
     mout_cmu_mux_mfc0_mfc0_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_MFC0_WFD, "mout_cmu_mux_mfc0_wfd",
     mout_cmu_mux_mfc0_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_MFC1_MFC1, "mout_cmu_mux_mfc1_mfc1",
     mout_cmu_mux_mfc1_mfc1_p, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_MIF_NOCP, "mout_cmu_mux_mif_nocp",
     mout_cmu_mux_mif_nocp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0, 2),
 MUX(CLK_MOUT_CMU_MUX_MIF_SWITCH, "mout_cmu_mux_mif_switch",
     mout_cmu_mux_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
     0, 3),
 MUX(CLK_MOUT_CMU_MUX_NOCL0_NOC, "mout_cmu_mux_nocl0_noc",
     mout_cmu_mux_nocl0_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0, 3),
 MUX(CLK_MOUT_CMU_MUX_NOCL1A_NOC, "mout_cmu_mux_nocl1a_noc",
     mout_cmu_mux_nocl1a_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC,
     0, 3),
 MUX(CLK_MOUT_CMU_MUX_NOCL1B_NOC0, "mout_cmu_mux_nocl1b_noc0",
     mout_cmu_mux_nocl1b_noc0_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0,
     0, 3),
 MUX(CLK_MOUT_CMU_MUX_NOCL1B_NOC1, "mout_cmu_mux_nocl1b_noc1",
     mout_cmu_mux_nocl1b_noc1_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_NOCL1C_NOC, "mout_cmu_mux_nocl1c_noc",
     mout_cmu_mux_nocl1c_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC,
     0, 3),
 MUX(CLK_MOUT_CMU_MUX_PERIC0_IP0, "mout_cmu_mux_peric0_ip0",
     mout_cmu_mux_peric0_ip0_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_PERIC0_IP1, "mout_cmu_mux_peric0_ip1",
     mout_cmu_mux_peric0_ip1_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_PERIC0_NOC, "mout_cmu_mux_peric0_noc",
     mout_cmu_mux_peric0_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC,
     0, 1),
 MUX(CLK_MOUT_CMU_MUX_PERIC1_IP0, "mout_cmu_mux_peric1_ip0",
     mout_cmu_mux_peric1_ip0_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_PERIC1_IP1, "mout_cmu_mux_peric1_ip1",
     mout_cmu_mux_peric1_ip1_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_PERIC1_NOC, "mout_cmu_mux_peric1_noc",
     mout_cmu_mux_peric1_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC,
     0, 1),
 MUX(CLK_MOUT_CMU_MUX_PERIC2_IP0, "mout_cmu_mux_peric2_ip0",
     mout_cmu_mux_peric2_ip0_p, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_PERIC2_IP1, "mout_cmu_mux_peric2_ip1",
     mout_cmu_mux_peric2_ip1_p, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1,
     0, 2),
 MUX(CLK_MOUT_CMU_MUX_PERIC2_NOC, "mout_cmu_mux_peric2_noc",
     mout_cmu_mux_peric2_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC,
     0, 1),
 MUX(CLK_MOUT_CMU_MUX_PERIS_GIC, "mout_cmu_mux_peris_gic",
--> --------------------

--> maximum size reached

--> --------------------

Messung V0.5
C=98 H=99 G=98

¤ Dauer der Verarbeitung: 0.19 Sekunden  ¤

*© Formatika GbR, Deutschland




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Bemerkung:

Die farbliche Syntaxdarstellung und die Messung sind noch experimentell.