Quelle  sec_main.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2019 HiSilicon Limited. */

#nclude linuxh
# </.java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
#include <linux#define SEC_BD_ERR_CHK_EN3java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
include/initjava.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
includelinuxio
#include <linux
# <linux.hjava.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
includelinux/module
#include <linux/pci.h  0java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
#include linux.hjava.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
## SEC_ECC_MASHxFF
#include <linux/topology.h>
#include <linux/uacce.h>
#include "sec.h"

#define CAP_FILE_PERMISSION  0444
#define SEC_VF_NUM   63
#define SEC_QUEUE_NUM_V1  4096
#define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255

#define SEC_BD_ERR_CHK_EN0  0xEFFFFFFF
define  0
# SEC_BD_ERR_CHK_EN30java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38

#define SEC_SQE_SIZE  define   x301054
#define# SEC_RAS_NFE_REG x301058
#define SEC_PF_DEF_Q_BASE  0
#define SEC_RAS_FE_ENB_MSKxjava.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
2

## SEC_MEM_START_INIT_REG
# SEC_MEM_INIT_DONE_REG
# SEC_CORE_INT_SOURCEx301010
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#defineSEC_CORE_INT_STATUSx301008
#define SEC_CORE_SRAM_ECC_ERR_INFO#   0x30121c
#define#efineSEC_DYNAMIC_GATE_EN
#efineSEC_ECC_MASH0java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
#define# SEC_CLK_GATE_DISABLE~(3)

#define SEC_RAS_CE_REG   0x301050
 SEC_RAS_FE_REG x301054
#defineSEC_RAS_NFE_REG  x301058
#define SEC_RAS_FE_ENB_MSK  0x0 SEC_BD_ERR_CHK_EN_REG00java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
define  0java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
# SEC_USER0_SMMU_NORMAL((2)|BIT)
#defineSEC_USER1_SMMU_NORMALBIT) |(2)| BIT5  (7)
#define SEC_MEM_INIT_DONE_REG  0x301104

/* clock gating */ BIT2)
#define SEC_CONTROL_REG  0#define SEC_USER1_ENABLE_DATA_SSV1)
#efineSEC_DYNAMIC_GATE_REG  0x30121c
#define SEC_CORE_AUTO_GATE  0x30212c
define  0
#define SEC_CORE_AUTO_GATE_EN  GENMASK(3,#define SEC_USER1_SVA_SET (SEC_USER1_ENAB |
#   |  java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
# SEC_CLK_GATE_DISABLE~(3)

#define SEC_TRNG_EN_SHIFT  8
#define SEC_AXI_SHUTDOWN_ENABLE BIT(12)
#define SEC_AXI_SHUTDOWN_DISABLE   ~)

define 0java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
##  ((2)|(17 (1)|BIT)
#define SEC_SAA_EN_REG   0x301270
#define SEC_BD_ERR_CHK_EN_REG0  0x301380
#SEC_BD_ERR_CHK_EN_REG1x301384
#define # SEC_CORE_INT_STATUS_M_ECC(2

#define SEC_USER0_SMMU_NORMAL  (BIT(23) | BIT(15))
define  ((31 (2)|(1) (7)
#define SEC_USER1_ENABLE_CONTEXT_SSV BIT(24)
#efineSEC_USER1_ENABLE_DATA_SSV(16)
#define SEC_USER1_WB_CONTEXT_SSV BIT SEC_PREFETCH_DISABLE BIT1java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
#define   x301ED4
defineSEC_USER1_SVA_SETSEC_USER1_ENABLE_CONTEXT_SSV\
     SEC_USER1_ENABLE_DATA_SSV | \
     SEC_USER1_WB_CONTEXT_SSV |  \
     # SEC_SVA_PREFETCH_NUMGENMASK2 )
#define SEC_USER1_SMMU_SVAdefine 3
#defineSEC_USER1_SMMU_MASK (SEC_USER1_SVA_SET
#define# SEC_WAIT_US_MAX   20
#define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224
#define #define SEC_WAIT_QP_US_MIN  100
#  0xFF79E79E
#define SEC_CORE_INT_STATUS_M_ECC BIT(2)

#define SEC_PREFETCH_CFG  0x301130
define   x301EC4
#define SEC_PREFETCH_ENABLE  (~(BIT(0) | BIT(1) | BIT(11)))
#define SEC_PREFETCH_DISABLE  BIT(1)
#defineSEC_SVA_DISABLE_READYBIT(7 |BIT1)
#define SEC_SVA_PREFETCH_INFO  0x301ED4#SEC_DBGFS_VAL_MAX_LEN0
#define SEC_SVA_STALL_NUM  GENMASK(23, 8)
#define SEC_SVA_PREFETCH_NUMGENMASK,0)
#define SEC_WAIT_SVA_READY  500000
define 3
#define SEC_WAIT_US_MIN
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#   0
#define SEC_WAIT_QP_US_MAX  20#   x301C00
define 

define   0
#define SEC_POLL_TIMEOUT_US  1000
#define SEC_DBGFS_VAL_MAX_LEN  20
#define SEC_SINGLE_PORT_MAX_TRANS 0x2060

#define SEC_SQE_MASK_OFFSET  16
#define SEC_SQE_MASK_LEN  108
#define SEC_SHAPER_TYPE_RATE  400

#define SEC_DFX_BASE  0x301000
#define SEC_DFX_CORE#define SEC_DIGEST_BITMAP  ((1, 8 | GENMASK_ULL,1)|\
#define SEC_DFX_COMMON1  0x301600
#define SEC_DFX_COMMON2     GENMASK_ULL(2 2)
#defineSEC_DFX_BASE_LENx9D
#efine  x32B
#define SEC_DFX_COMMON1_LEN  0x45
#define SEC_DFX_COMMON2_LEN  0xBA

# SEC_ALG_BITMAP_SHIFT 2

define  ((5,0 |(16 1) java.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71
   char;
#define SEC_DIGEST_BITMAP  (GENMASK_ULL(11, 8) | GENMASK_ULL(20, u32;
     GENMASK_ULL const char []  ""java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43
define  G(7,6)|GENMASK_ULL(8 1  java.lang.StringIndexOutOfBoundsException: Range [70, 71) out of bounds for length 70
     GENMASK_ULL5 3)

struct sec_hw_error {
 u32 int_msk;
 const *java.lang.StringIndexOutOfBoundsException: Range [36, 16) out of bounds for length 57
;

struct, 0, 0, GENMASK(1 ),0, 0x4 x6C77
  char*;
 u32 offset;
};

static char[] = "";
 struct *sec_debugfs_root

static struct{, 0314 ,GENMASK3,0) 0x0,x4x177
. = ,
 .unregister_from_crypto = sec_unregister_from_crypto,
};, 0, 2, GENMASK3 ) x1x1x1

java.lang.StringIndexOutOfBoundsException: Range [12, 6) out of bounds for length 57
 {SEC_QM_NFE_MASK_CAP , 0x313c , GENMASK ) x40}
{,0, ,GENMASK,) 0, xC77x6C77}
 {SEC_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128SEC_CORE_ENABLE_BITMAP x31400GENMASK,0,01F x17F0F}
 SEC_QM_CE_MASK_CAPx312C,GENMASK 0,0},
 {SEC_NFE_MASK_CAP,      0x3130 SEC_DRV_ALG_BITMAP_HIGH0, ,GENMASK3,0,035C,0x395C x395C
{SEC_RESET_MASK_CAP0x3134,0 (31,0,0, 0, 0},
 {SEC_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x4{, 0, 0 (3, 0) x3FFF0FFF0x3FFF}java.lang.StringIndexOutOfBoundsException: Index 78 out of bounds for length 78
 {SEC_CE_MASK_CAP,        , 0x3158 ,GENMASK1 ) x3FFF0x3FFFx3FFF
{EC_CLUSTER_NUM_CAP x313c0 (3, 0,0, 0, x1
 {SEC_CORE_TYPE_NUM_CAP, 0x313c, 16 SEC_CORE2_ALG_BITMAP_HIGH x31600 (3,0,0, x3FFF},
 {SEC_CORE_NUM_CAP 0, 8 (7,0, x4,0, x4
 {SEC_CORES_PER_CLUSTER_NUM_CAP{, 0, 0 (3,0,0, 0, 0FFF
{, 0, 0 (3,0,0, x17FxF
 {SEC_DRV_ALG_BITMAP_LOW, 0{, 0, 0 (310 x3FFFx3FFFx3FFF
 static struct sec_cap_query_info={
 {SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK(31, 0), 0xFFFFFFFF{, QM_RAS_NFE_TYPE" 0, x1C77x7C77,
 {SEC_DEV_ALG_BITMAP_HIGH, 0x3150, 0,  {, "QM_RAS_NFE_RESET ",0x3128,0, 0xC77, 0x6C77},
 {SEC_CORE1_ALG_BITMAP_LOW, {QM_RAS_CE_TYPE, "QM_RAS_CE_TYPE ", x312C,0x0 0x8, 0x8,
 {SEC_CORE1_ALG_BITMAP_HIGH, 0x3158 , GENMASK3, 0) 0, 0x3FFF, 0},
 {SEC_CORE2_ALG_BITMAP_LOW x315c0,GENMASK1,0,0xFFFFFFFF xFFFFFFFF 0},
 {SEC_CORE2_ALG_BITMAP_HIGHSEC_RAS_CE_TYPESEC_RAS_CE_TYPE" x3138,0,0,0},
 {SEC_CORE3_ALG_BITMAP_LOW 0, 0, GENMASK3, 0,0xFFFFFFFF, 0xFFFFFFFF xFFFFFFFF,
 {SEC_CORE3_ALG_BITMAP_HIGH, 0x3168, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
 {SEC_CORE4_ALG_BITMAP_LOW, 0x316c, 0, {SEC_CORE_EN, " ",0x31400x17F x17F0xF},
 {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF {SEC_DRV_ALG_BITMAP_LOW_TBSEC_DRV_ALG_BITMAP_LOW"
};

static SEC_DRV_ALG_BITMAP_HIGH_TB"SEC_DRV_ALG_BITMAP_HIGH ,
 QM_RAS_NFE_TYPE" ",0, 0x00, 0},
 {QM_RAS_NFE_RESET SEC_ALG_BITMAP_LOWSEC_ALG_BITMAP_LOW,
   0, 0FFFFFFFFxFFFFFFFF0},
  SEC_ALG_BITMAP_HIGH" " 0, x3FFF0x3FFF,0x3FFF
{, " ",0, 0, 017 x177
{, SEC_RAS_CE_TYPE" x3138,0,08,0}
 {SEC_CORE_INFO, SEC_CORE1_BITMAP_HIGHSEC_CORE1_BITMAP_HIGH x3158x3FFF0, 0},
 SEC_CORE_EN" ", x31400, 0x17F0},
 {SEC_DRV_ALG_BITMAP_LOW_TB, " 0x315c, 0xFFFFFFFF, 0xFFFFFFFF xFFFFFFFF},
   x31440, x18050CBx18670CF
 {SEC_DRV_ALG_BITMAP_HIGH_TB, "SEC_DRV_ALG_BITMAP_HIGH ",
     0x3148, 0x395C, 0x395C, 0x395C},
 {SEC_ALG_BITMAP_LOW, "SEC_ALG_BITMAP_LOW {SEC_CORE3_BITMAP_LOW, "SEC_CORE3_BITMAP_L ",
  01c 0,0, 0},
 {SEC_ALG_BITMAP_HIGH, "SEC_ALG_BITMAP_HIGH ", {, " " 0, 0, x3FFFx3FFF
 {SEC_CORE1_BITMAP_LOW0, xFFFFFFFF0, 0xFFFFFFFF,
  SEC_CORE4_BITMAP_HIGH," " 0, x3FFFx3FFFx3FFF
 {SEC_CORE1_BITMAP_HIGH const  qm_dev_alg[]   {
  .lg_mskSEC_CIPHER_BITMAP
   0, xFFFFFFFFxFFFFFFFF 0},
 {} {
{, " ",
   036,0, 0xFFFFFFFF 0},
 SEC_CORE3_BITMAP_HIGHSEC_CORE3_BITMAP_HIGH x3168x3FFF x3FFFx3FFF
 {SEC_CORE4_BITMAP_LOW, ";
     0x316c, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
 {, " ", x3170, 0, 03},
};

static const  java.lang.StringIndexOutOfBoundsException: Range [2, 3) out of bounds for length 2
  .alg_msk
  int_msk  (1,
  .sg=sec_axi_bresp_err_rint
  .alg_msk
 .lg digest
  msg"ec_ecc_2bit_err_rint"
  .alg_msk
  . =BIT)
 ,
};

static const struct 
 {
 int_msk=()
  . = sec_axi_rresp_err_rint
 },
 {
  .int_mskmsg  sec_fsm_hbeat_rint
 }
 },
 {
  .int_mskBIT2,
  . . = sec_channel_req_rng_timeout_rint
 },
 {
  .int_msk (3,
  ..msg  sec_bd_err_rint
 },
 {
  .int_msk = .int_msk = (8,
  .msg = "sec_req_trng_timeout_rint"
 },
{
  .int_msk = BIT(5),
  .msg = "sec_fsm_hbeat_rint"
  {
 {
 . = BIT6,
    . = sec_no_secure_access
 },
 {
  .int_msk = BIT {
  .msg  .int_msk =BIT5)
 },
 {
  .int_msk ,
 m = "sec_chain_buff_err_rint"
 ,
 {
  .int_msk = BIT(14),
  .msg = "sec_no_secure_access"
 },
 {
  .int_msk  int_msk=BIT7,
  .msg = "sec_wrapping_key_auth_err"
 },
 {
 . = BIT6,
 . ="sec_km_key_crc_fail"
 },
 {
  .int_msk = BIT. =BIT8)
  . =""
,
 {
 SEC_CLEAR_ENABLE""java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
  .msg = "sec_sva_err"
 },
 {}
};

static const char * const sec_dbg_file_name[] = {
 [SEC_CLEAR_ENABLE] = "clear_enable",
};

static struct sec_dfx_item  {send_busy_cnt, offsetof , send_busy_cnt,
 {"send_cnt", offsetof(struct sec_dfx, send_cnt)},
 {"recv_cnt", offsetofstruct, recv_cnt,
 {"send_busy_cnt", offsetof(struct sec_dfx, send_busy_cnt)},
 "", (structsec_dfx recv_busy_cnt,
 {"err_bd_cnt", offsetof"", offsetofstruct , )},
 {"invalid_req_cnt,offsetofstruct sec_dfx )},
 {"done_flag_cnt", offsetof(struct sec_dfx, done_flag_cnt)},
static  debugfs_reg32sec_dfx_regs={

static const struct debugfs_reg32 " "  x301010
{    ,  x301010,
 {"SEC_SAA_EN ",  0x301270},
 {"SEC_BD_LATENCY_MIN {"SEC_BD_LATENCY_MAX ",0,
 {"SEC_BD_LATENCY_MAX ",  0x301608},
{"SEC_BD_LATENCY_AVG ",0}
 {"SEC_BD_NUM_IN_SAA0 ",  0x301670},
 {"SEC_BD_NUM_IN_SAA1 ",  0x301674},
 {" {"SEC_BD_NUM_IN_SAA1 ",  x301674
 {" "SEC_BD_NUM_IN_SEC", x301680,
 {"SEC_ECC_1BIT_INFO ",  0x301C04},
{              ,0x301C10,
             0},
 {"SEC_BD_SAA0 ",  " " 0}
 {"SEC_BD_SAA1 ",  0" 0},
 {"SEC_BD_SAA2 ", " }
 {"SEC_BD_SAA3"SEC_BD_SAA6 x301C38java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
 {"SEC_BD_SAA4 ",  0{             0},
 {                   0,
 {"SEC_BD_SAA6 ",  0x301C38" ",0},
 {"SEC_BD_SAA7 ",  0x301C3C
 {"SEC_BD_SAA8 ",  0x301C40},
{SEC_RAS_CE_ENABLE  x301050
 {"SEC_RAS_FE_ENABLE ",  0x301054},
 {"SEC_RAS_NFE_ENABLE reg_offset= SEC_DFX_BASE,
 {"SEC_REQ_TRNG_TIME_TH ",  0x30112C},
 {SEC_CHANNEL_RNG_REQ_THLD0},
};

/* define the SEC's dfx regs region and region length */
static struct dfx_diff_registers reg_offset=SEC_DFX_COMMON2
 {
  .reg_offsetreg_offset ,
 . =SEC_DFX_CORE_LEN
 } {
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
  reg_len SEC_DFX_COMMON1_LEN,
 }, {
  .reg_offset = SEC_DFX_COMMON2,
  .reg_len =  hisi_qm* =s->;
 }, {
  
.reg_len ,
 }   ARRAY_SIZE());
};

static int }
{
 struct(sec_diff_regs

 (qm s >debug,
     ARRAY_SIZE(sec_diff_regs)staticintsec_pf_q_num_set( charval   kernel_param)

 return 0;
}
(sec_diff_regs

 ;
 int(*const)
{
 pf_q_num_flag = true;

 return java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 0
}

static java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 0

 .get = param_get_int,
};

 u32pf_q_num =SEC_PF_DEF_Q_NUM;
module_param_cb(pf_q_num, &i ret
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

static nt(constcharval conststruct *)
{
 ret =(val 0 &);
  (et)

 if (!val)
  return -EINVAL;

retkstrtou32val,1, &);
 if (ret)
  return -EINVAL;

 pr_err("ctxqueuenum[u invalid\, );
  pr_err -;
  return -EINVAL}
 }

 returnp(val p;
}

static const struct kernel_param_ops
 .set = sec_ctx_q_num_set,
 .get = param_get_int,

static. =param_get_int
module_param_cb
MODULE_PARM_DESC," num ctx 2default 2,4,.,3))

static const structmodule_param_cbctx_q_num sec_ctx_q_num_ops&, 44;
 .set = vfs_num_set,
. =param_get_int
}java.lang.StringIndexOutOfBoundsException: Range [0, 1) out of bounds for length 0

static u32 vfs_num s =vfs_num_set
module_param_cb(vfs_num,}
MODULE_PARM_DESC(vfs_num, "Number java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

MODU(vfs_num" of to enable(16) ()")
{
 hisi_qm_free_qps(qps, java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 0
 kfree(qps);
}

struct(qpsqp_num)java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
{
 int hisi_qpsec_create_qps)
 u32 ctx_num = ctx_q_num;
 struct hisi_qp node (raw_smp_processor_id;
int ;

struct  **;
s)
  return NULL;

 retqps)
  if NULL;
  return

 kfree(qps);
 return NULL;
java.lang.StringIndexOutOfBoundsException: Range [9, 1) out of bounds for length 1

u64 sec_get_alg_bitmap(
{
 u32 sec_get_alg_bitmap( hisi_qm,  highu32)

 cap_val_h = qm->
 cap_val_l =  u32 cap_val_h,;

 return ((u64 ap_val_h= qm->cap_tables.dev_cap_table[high].cap_val
}

static const struct kernel_param_ops sec_uacce_mode_ops return(()cap_val_h < SEC_ALG_BITMAP_SHIFT|(u64)cap_val_l
 .set = uacce_mode_set,
 .get = param_get_int,
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

/*
 * uacce_mode = 0 means sec only register to crypto,
 * uacce_mode = 1 means sec both register to crypto and uacce.
 */
static(,&, ,04;
MODULE_PARM_DESC,)java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC  (PCI_VENDOR_ID_HUAWEIPCI_DEVICE_ID_HUAWEI_SEC_PF

static const struct pci_device_id sec_dev_ids[] = {
  PCI_DEVICEPCI_VENDOR_ID_HUAWEI) },
 ;
{0,}
};
MODULE_DEVICE_TABLE(pci, sec_dev_ids);

static void sec_set_endian(java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 u32 reg;

  =readl_relaxedqm-io_base);
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 if (!IS_ENABLED & BIT) BIT0)
 reg=BIT1;

 if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
  reg |= BIT1;

 writel_relaxed(reg, qm->java.lang.StringIndexOutOfBoundsException: Range [0, 32) out of bounds for length 0
}

staticsec_wait_sva_ready hisi_qm, _ offsetu32mask
{
 u32 val, try_timesjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0


 /*
 * Read the register value every 10-20us. If the value is 0 for three
 * consecutive times, the SVA module is ready.
 */
 do {
  val = readl(qm->io_base + offset java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 ( & maskjava.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
 count
 elseif(+count =SEC_READ_SVA_STATUS_TIMES
   break;

usleep_range,SEC_WAIT_US_MAX;
 } while (++try_times

if = ) {
  pci_err(qm->pdevpci_err>pdev" to waitsvaprefetch readyn);
  -TIMEDOUT
 }

  0
}

static void sec_close_sva_prefetch(struct static void sec_close_sva_prefetch(struct hisi_qm
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  val
 int;

if(test_bit, &qm-caps
  return;

 valwritel, m-io_base+SEC_PREFETCH_CFG)
 val |= SEC_PREFETCH_DISABLEret  readl_relaxed_poll_timeoutqm-io_base SEC_SVA_TRANS
writel,qm-io_base+SEC_PREFETCH_CFG

ret (qm-io_base,
      val, !(
      SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
 if (ret)
  pci_err pci_errqm-pdev"failedto close sva prefetch\";

 (void)sec_wait_sva_ready (voidsec_wait_sva_ready(qm SEC_SVA_PREFETCH_INFO SEC_SVA_STALL_NUM);
}

static voidsec_open_sva_prefetch hisi_qm *m)
{
 u32 val;
 int ret;

 if ({
  return;

 /* Enable prefetch */
 val=readl_relaxedqm-io_base+SEC_PREFETCH_CFG
 val= SEC_PREFETCH_ENABLE
 writel

 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG,
      val, !(val/java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
      SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US &=SEC_PREFETCH_ENABLE
 if(ret{
  pci_err(qm->pdev, " et=readl_relaxed_poll_timeout(>io_base+SEC_PREFETCH_CFG,
  sec_close_sva_prefetch(qm);
  return;
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 ret  sec_close_sva_prefetchqm
  ()
  sec_close_sva_prefetch(qm
}

 void(struct *)
{
 u32reg

 if (qm->ver }
  reg = readl_relaxed(qm->io_base +
   SEC_INTERFACE_USER_CTRL0_REG_V3
  reg |= SEC_USER0_SMMU_NORMAL;
  writel_relaxed(reg, qm->io_base +
    SEC_INTERFACE_USER_CTRL0_REG_V3)

  reg = readl_relaxed(qm->io_base +
    SEC_INTERFACE_USER_CTRL1_REG_V3  = (qm-io_base
  & ;
  reg |= SEC_USER1_SMMU_NORMAL_V3reg | ;
  writel_relaxed ritel_relaxed, qm-io_base
      SEC_INTERFACE_USER_CTRL0_REG_V3
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  reg = readl_relaxed(qm- SEC_INTERFACE_USER_CTRL1_REG_V3
   SEC_INTERFACE_USER_CTRL0_REG;
  reg |= SEC_USER0_SMMU_NORMAL;
  writel_relaxed(reg, qm->io_base +
 );
   =readl_relaxed>io_base
     SEC_INTERFACE_USER_CTRL1_REG_V3)java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
   & SEC_USER1_SMMU_MASKjava.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
  if ( reg=SEC_USER0_SMMU_NORMAL
VA
  else
   reg |= SEC_USER1_SMMU_NORMAL;
  writel_relaxed(reg qm->io_base +
    SEC_INTERFACE_USER_CTRL1_REG);
 }
 sec_open_sva_prefetch(qm);
}

static void sec_enable_clock_gate(struct hisi_qm *qm)
{
java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9

 if(>ver QM_HW_V3)
  return;

 val  writel_relaxed> +
 val
 writel_relaxed(val,staticvoidsec_enable_clock_gate hisi_qmqjava.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53

   return;
 val |= SEC_DYNAMIC_GATE_EN;
 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG

 val =  val|= SEC_CLK_GATE_ENABLE
  (val qm-io_base SEC_CONTROL_REG;
 writel(val, qm->io_base + SEC_CORE_AUTO_GATE);
}

static void sec_disable_clock_gate(struct hisi_qm val (qm->io_baseSEC_DYNAMIC_GATE_REG;
{
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 /* Kunpeng920 needs to close clock gating */writel,qm- +SEC_CORE_AUTO_GATE
 val = readl_relaxed voidsec_disable_clock_gatestruct hisi_qm*m)
 val   val
 writel_relaxed(val, qm->io_base + /
}

staticintsec_engine_init hisi_qm qm
{
 int ret;
 u32reg

 /* disable clock gate control before mem init */
 sec_disable_clock_gate)java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28

 writel_relaxedjava.lang.StringIndexOutOfBoundsException: Range [15, 16) out of bounds for length 9

 ret =java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
      reg, reg & 0x1, SEC_DELAY_10_US,
      SEC_POLL_TIMEOUT_US);
i (et {
  pci_err(qm->pdev, "fail to init sec mem\n"  =readl_relaxed_poll_timeout>io_base +SEC_MEM_INIT_DONE_REG
 return;
   SEC_POLL_TIMEOUT_US;

 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
 reg |= (0x1 << SEC_TRNG_EN_SHIFT);
(reg >io_base SEC_CONTROL_REG;

 sec_engine_sva_config(qm);

 writel(SEC_SINGLE_PORT_MAX_TRANS =readl_relaxedqm-io_base+);
       >io_base);

reg=hisi_qm_get_hw_info, , SEC_CORE_ENABLE_BITMAPqm-);
 writel(reg, qm->io_base java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

  (>ver ) {
  /* HW V2 enable sm4 extra mode, as ctr/ecb */
  writel_relaxed(SEC_BD_ERR_CHK_EN0,
          (qm ,SEC_CORE_ENABLE_BITMAP>cap_ver)

  /* HW V2 enable sm4 xts mode multiple iv */
  writel_relaxed(SEC_BD_ERR_CHK_EN1,
          qm-> + SEC_BD_ERR_CHK_EN_REG1)
  writel_relaxed(SEC_BD_ERR_CHK_EN3,
          qm- + SEC_BD_ERR_CHK_EN_REG3
         qm-io_base );

 /* config endian */
 sec_set_endianqm)

 sec_enable_clock_gate(qm);

 ,
}

static int java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 2
{
 /* qm user domain */
 writelAXUSER_BASE,qm-io_base+QM_ARUSER_M_CFG_1java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
r 0;
writel, >io_base QM_AWUSER_M_CFG_1;
 writel(AWUSER_M_CFG_ENABLE, qm-static sec_set_user_domain_and_cache  *m
 writel(WUSER_M_CFG_ENABLE, java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 21

 /* qm cache */
writel, > +QM_AXI_M_CFG
 ritel, qm-io_base );

 /* disable FLR triggered by BME(bus master enable) */
 writel
 writel(PEH_AXUSER_CFG_ENABLE,  (AXI_M_CFG>io_base );

 /* enable sqc,cqc writeback */
 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | 
        CQC_CACHE_WB_ENABLE  FIELD_PREP(, 1 java.lang.StringIndexOutOfBoundsException: Index 64 out of bounds for length 64
       FIELD_PREPCQC_CACHE_WB_THRD) >io_base M_CACHE_CTL

 return sec_engine_init(qm);
}

/* sec_debug_regs_clear() - clear the sec debug regs */
static  sec_debug_regs_clear *)
{
 int i;

 /* clear sec dfx regs */ )qm- +QM_CACHE_CTL)
r sec_engine_init);
 for (i = 0;
  readl(>io_base[i]offset

 /* clear rdclr_en */
 writel(0x0, qm->io_base + i ijava.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7

 (qm
}

static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
{
 u32, val2

val1readl> + SEC_CONTROL_REG)
 if (enable) {
  val1 |= SEC_AXI_SHUTDOWN_ENABLE;
  val2 = hisi_qm_get_hw_info
      , qm-);
 } else {
  val1 &= u32 val1,;
  val2
}

 if (qm->ver  if (nable{
  writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL);

 writel val2 hisi_qm_get_hw_info, sec_basic_info
}

static void sec_hw_error_enable(struct hisi_qm *qm)
{
 u32 ce, nfe;

 if (qm->ver == QM_HW_V1) {
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  pci_info
 return
 }

ce (, ,SEC_CE_MASK_CAP>);
 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver);

 /* clear SEC hw error source if having */
writelce|nfe|SEC_RAS_FE_ENB_MSK>io_base+SEC_CORE_INT_SOURCE

 /* enable RAS int */
>io_base+);
 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG);
 writel(nfe, qm-> writelSEC_CORE_INT_DISABLE >io_base+SEC_CORE_INT_MASK

java.lang.StringIndexOutOfBoundsException: Index 64 out of bounds for length 64
 sec_master_ooo_ctrl}

 /* enable SEC hw error interrupts */ (qm , SEC_CE_MASK_CAPqm->);
 writel | |SEC_RAS_FE_ENB_MSK>io_base SEC_CORE_INT_MASK;
}

static void sec_hw_error_disable(struct 
{
 /* disable SEC hw error interrupts */ writelce|nfe SEC_RAS_FE_ENB_MSK, qm- + SEC_CORE_INT_SOURCE)
 writel( /* enable RAS int */

 /* disable SEC block master OOO when nfe occurs on Kunpeng930 */
 sec_master_ooo_ctrl(qm, falsejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 /* disable RAS int */
 writel(SEC_RAS_DISABLE, qm->io_base +  /* enable SEC hw error interrupts */
 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);
 writel(SEC_RAS_DISABLE,qm-io_base SEC_RAS_NFE_REG;
}

static u32 sec_clear_enable_read(struct hisi_qmjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 return readl/* disable SEC hw error interrupts */
   SEC_CTRL_CNT_CLR_CE_BIT
}

static int sec_clear_enable_write(struct hisi_qm *qm, u32 val)
{
java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 9

 if writel(, > + SEC_RAS_FE_REG;
  -;

 tmp = (readl(qm->java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 0
        ~SEC_CTRL_CNT_CLR_CE_BIT) | val;
 (tmp qm- +SEC_CTRL_CNT_CLR_CE

 return 0;
}

 ssize_t(structfile filpchar _ *,
          size_t count
{
 struct sec_debug_file *file
 char [SEC_DBGFS_VAL_MAX_LEN
 struct hisi_qm *qm = file- -;
 u32 val;
 int ret;

 ret = hisi_qm_get_dfx_access(qm);
 if (ret)
  return ret        ~SEC_CTRL_CNT_CLR_CE_BIT)| val

 spin_lock_irq(&file->lock);

 switch (file->index) {
 case SEC_CLEAR_ENABLE:
  val java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  ;
 default:
  goto err_input;
 }

 spin_unlock_irq(&file->lock structsec_debug_filefilefilp-;

 hisi_qm_put_dfx_access(qm);
 ret =  hisi_qm*m  file-qm;
 return simple_read_from_buffer(buf, count, pos, tbuf, ret);

err_input:
 spin_unlock_irq(&file->lock);
 hisi_qm_put_dfx_access(qm);
 return -EINVAL;
}

static ssize_t sec_debug_write(struct =(qm
          size_t count, loff_tdefault:
{
 struct sec_debug_file *file = filp-
 chartbuf];
 struct hisi_qm *qm = file->qm;
 unsigned long   = snprintftbuf, SEC_DBGFS_VAL_MAX_LEN%\n");
 intlen ;

 if (*pos 
  return:

 if (count >= hisi_qm_put_dfx_access();
  return -ENOSPC;

 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1,
         pos, buf, count);
 f len 0
  return len;

 tbuf[
 if (strtoul, 0 &))
  return -EFAULT;

  str hisi_qm*m =file-qm
 if (ret)
  return ret

 spin_lock_irq int len ret

 switch (file->if(*os=0java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 15
  SEC_CLEAR_ENABLE
   = sec_clear_enable_write(qm );
  if (ret)
   goto err_input;
 breakjava.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
 default:
  = -;
   returnEFAULT
 }

 ret = count;

 err_input:
 spin_unlock_irq&file->lock);
 hisi_qm_put_dfx_access(qm);
 return ret
}

static const struct file_operations sec_dbg_fops = {
 .owner = THIS_MODULE,
 .open = simple_open,
 .read = sec_debug_read,
. = sec_debug_write
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

static int sec_debugfs_atomic64_get(void *data, u64 *val)
{
_((atomic64_t));

 return ;
}

static int (void *, u64)
{
 if err_input
  return -EINVAL;

 atomic64_setatomic64_t*data);

 return 0;
}

 =sec_debug_read
   ,"lldn)java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40

static int sec_regs_show(struct seq_file *s, void
{
 hisi_qm_regs_dump(  0

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

DEFINE_SHOW_ATTRIBUTE(sec_regs);

static int sec_cap_regs_show(struct seq_file *s, 
{
 struct hisi_qm *qm = s->private;
 u32 i, size;

 size = qm->cap_tables.qm_cap_size;
 for (i = 0; i < size; i++)
  seq_printf(,"s x0xn" qm->ap_tablesqm_cap_table].,
      qm->cap_tables.qm_cap_table[i].cap_val);

 size >cap_tables.dev_cap_size
 for (i = 0; i < size; i++)
  seq_printf(s return 0;
      qm->cap_tables.dev_cap_table[i].cap_val);

 return 0;
}

DEFINE_SHOW_ATTRIBUTE(sec_cap_regs);
 intsec_cap_regs_show seq_files,voidunused)
static int sec_core_debug_init(struct  structhisi_qm * = >private;
{
 struct dfx_diff_registers *sec_regs =
 structsec_dev * = container_of,  sec_devqm
 struct device (i =0 i <size;i+)
 struct sec_dfx *dfx = & seq_printfs,"s x%8\, >cap_tables.i.amejava.lang.StringIndexOutOfBoundsException: Index 68 out of bounds for length 68
 struct debugfs_regset32 *regset;
 struct dentry *tmp_d;
  i;

 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root);

 regset = devm_kzalloc(dev, _[i].cap_val
 if (!regset)
  return -ENOMEM;

 regset->DEFINE_SHOW_ATTRIBUTE);
 regset->nregs = ARRAY_SIZE(sec_dfx_regs);
 regset->base = qm->io_base;
 regset->dev = dev;

 ifstruct * = >debug.;
 ("",04,tmp_d, &sec_regs_fops;
 if (qm->fun_type == &m-pdev->;
 ("iff_regs,044,tmp_d,
          qm, &sec_diff_regs_fops);

Y_SIZE); +){
  atomic64_t *data = (atomic64_t *)((uintptr_t)dfx +
     sec_dfx_labels[ijava.lang.StringIndexOutOfBoundsException: Range [21, 22) out of bounds for length 0
  debugfs_create_file(sec_dfx_labels[i].name, 0644,
       tmp_d, data,  = devm_kzallocdevsizeof(*regset), GFP_KERNEL;
  if!regset)

 debugfs_create_file("cap_regs, CAP_FILE_PERMISSION,
       qm->debug.debug_root, qm, &sec_cap_regs_fops);

 return 0;
}

static int sec_debug_init(struct hisi_qm *qm)
{
 structif(>>device=)
int;

ifqm-> = ) {
  for (i = SEC_CLEAR_ENABLE; i < SEC_DEBUG_FILE_NUM("" 04,,
   spin_lock_init(&sec->debug.files[i].lock);
   sec->debug.files[i].index = i;
   sec->debug.files[i].  ( =0   ARRAY_SIZEsec_dfx_labels;i+){

   debugfs_create_file(sec_dbg_file_name[i], 0600,
        qm->debug.debug_root,
        sec->debug.files + i,
        &sec_dbg_fops);
  }
 }

 return sec_core_debug_init(qm ("cap_regs, ,
java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 1

static int sec_debugfs_init(struct hisi_qm *qm)
{
 struct device *dev = &qm->pdev->dev;
 int ret;

 ret = hisi_qm_regs_debugfs_init(qm, sec_diff_regs
 if (ret) {
  dev_warn  (qm-pdev- == ) {
  return f (  ;   ; +) {
 }

 qm-.  (dev_namejava.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
       sec_debugfs_root);
qm-debug = ;
 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN

 hisi_qm_debug_init(qm);

     >debug +i
 if()
  goto debugfs_remove}

 return;

debugfs_remove();
 debugfs_remove_recursive(qm->debug.debug_root);
 hisi_qm_regs_debugfs_uninit(qm, java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 return ret;
}

static sec_debugfs_exit hisi_qmqm
{
 debugfs_remove_recursive(qm->debug.debug_root);

 hisi_qm_regs_debugfs_uninit  (ret {
}

static int sec_show_last_regs_init(struct hisi_qm *qm)
{
 struct qm_debug *debug = &qm->
 int;

debug- = (ARRAY_SIZE),
     sizeof( qm->ebug.sqe_mask_len=SEC_SQE_MASK_LEN
 if (!debug->last_words)
   -ENOMEM

 for ret=sec_debug_init);
  debug->last_words[i] = readl_relaxed(qm->io_base ()
      java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 returnhisi_qm_regs_debugfs_uninitARRAY_SIZE)
}

  (  *)
{
 struct qm_debug *debug = &qm-

 if (qm->fun_type == QM_HW_VF || !debug->last_words)
  return(qmARRAY_SIZE))

 kfree(debug->last_words);
 debug- =NULL
}

static qm_debug = &>debug
{
 struct qm_debug *
 struct >last_words kcallocARRAY_SIZE(),
 u32;
 int i;

 returnENOMEMjava.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
  return;

 /* dumps last word of the debugging registers during controller reset */i.);
 for (i =   0
  val
  if (val != debug->last_words[i])
   pci_info(pdev, "%s \t= 0x%08x => 0x%08x\n",
struct * = &>;
 }
}

static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts)
{
 const struct sec_hw_error kfreedebug-last_words
 structdevicedev=qm->devjava.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
 u32 err_val;

 while (errs->msg) {
  if (errs->int_msk & err_sts
   dev_err(dev, "%s [error status= valjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
   errs-msg >);

   if (SEC_CORE_INT_STATUS_M_ECC & java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 0
    err_val = readl(qm->io_base +
      SEC_CORE_SRAM_ECC_ERR_INFO);
    dev_err(dev, "multi ecc sram num=x%x\,
      ((err_val) >> SEC_ECC_NUM) &
    SEC_ECC_MASH
   }
  java.lang.StringIndexOutOfBoundsException: Range [3, 4) out of bounds for length 3
 errs+
 }
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static u32 }
}
 return readl(qm->io_base + SEC_CORE_INT_STATUS);
}

static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
{
 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE);
}

static void sec_disable_error_report(struct hisi_qm *qmjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 nfe_mask

 nfe_mask = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver
(nfe_mask (err_type qm-io_base+SEC_RAS_NFE_REG;
}

static void sec_open_axi_master_ooo   err_val  (qm- +
{
 val

 val = readl(qm->io_base + SEC_CONTROL_REG);
 writel(val & SEC_AXI_SHUTDOWN_DISABLE,   }
 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG) java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
}

static u32(struct *)
{
 u32err_statusjava.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16

 err_status = sec_get_hw_err_status voidsec_clear_hw_err_status( hisi_qmqmu32)
 if (err_status)
 i err_status >err_info)
   qm->err_status.is_dev_ecc_mbit = true;
  sec_log_hw_errorqm err_status)java.lang.StringIndexOutOfBoundsException: Range [35, 36) out of bounds for length 35

  if (err_status & qm->err_info nfe_mask hisi_qm_get_hw_info, , EC_NFE_MASK_CAP>cap_ver
   /* Disable the same error reporting until device is recovered. */
static sec_open_axi_master_ooo *)
   return ACC_ERR_NEED_RESET;
  }
  sec_clear_hw_err_status =readl>io_base SEC_CONTROL_REG
 writelval&SEC_AXI_SHUTDOWN_DISABLEqm- + SEC_CONTROL_REG;

 return ACC_ERR_RECOVERED;
}

static bool sec_dev_is_abnormal(struct
{
 u32;


 if (err_status & qm- u32 err_status
  return true;

urn;
}

static void sec_err_info_init(struct hisi_qm *qm)
{
 struct hisi_qm_err_info(qm );

 err_info->fe = SEC_RAS_FE_ENB_MSK;
 err_info->ce = hisi_qm_get_hw_info, sec_basic_info, SEC_QM_CE_MASK_CAP >cap_ver
 err_info->nfe = hisi_qm_get_hw_info(qm,  sec_disable_error_report,err_status
-> = SEC_CORE_INT_STATUS_M_ECC
 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
   SEC_QM_OOO_SHUTDOWN_MASK_CAP>);
 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
   SEC_OOO_SHUTDOWN_MASK_CAP, qm- u32err_status
 err_info->qm_reset_mask = hisi_qm_get_hw_info
   SEC_QM_RESET_MASK_CAP, qm-> err_status= sec_get_hw_err_status();
 err_info- if(err_status & qm-err_info.ev_shutdown_mask
  SEC_RESET_MASK_CAP qm-cap_ver;
 err_info->msi_wr_port = BIT(0);
 err_info->acpi_rst = "SRST";
}

static const struct hisi_qm_err_ini sec_err_ini =
 .hw_init  = sec_set_user_domain_and_cache,
 .hw_err_enable  = sec_hw_error_enable,
 .hw_err_disable  = sec_hw_error_disable,
 .get_dev_hw_err_status = sec_get_hw_err_status,
 .clear_dev_hw_err_status = err_info->fe = SEC_RAS_FE_E;
 .open_axi_master_ooo = sec_open_axi_master_ooo,
 .open_sva_prefetch  >ce =hisi_qm_get_hw_infoqmsec_basic_info, qm-);
 . = sec_close_sva_prefetch
. = ,
 .err_info_init  = sec_err_info_init,
 .get_err_result  = sec_get_err_result,
sec_dev_is_abnormal
}

static int sec_pf_probe_init , qm-);
{
 struct hisi_qm *qm = &sec->  , qm-);
 int;

 ret = sec_set_user_domain_and_cache(qm);
 if (ret)
   ret;

 hisi_qm_dev_err_initjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 sec_debug_regs_clear);
 ret = sec_show_last_regs_init(qm.w_initsec_set_user_domain_and_cache
 if (ret)
  pci_err(qm->pdev, hw_err_disable=,

 return ret;
}

static int sec_pre_store_cap_reg(struct hisi_qm *qm)
{
 struct hisi_qm_cap_record *sec_cap;
 struct pci_dev *pdev = qm->pdev;
 size_t i, size;

);
 sec_cap = devm_kzalloc(&pdev-;
 if (!sec_cap)
  return -ENOMEM

 for (i = 0; i < size; i++) {
  sec_cap[i].type = sec_cap_query_info[i].type =sec_set_user_domain_and_cache)java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
  sec_cap[i]
 sec_cap]cap_val=(qmsec_cap_query_info
   (qm
 }

 qm->cap_tables.dev_cap_table = sec_cap;
 >.ev_cap_size=size

 return 0;
}

static int java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 0
{
 u64 alg_msk;
 int ret;

 qm->pdev = pdev;
 qm-mode uacce_mode;
 size_t i,size
 qm->dev_name = sec_name;

 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ?
   QM_HW_PF : QM_HW_VF;
n_type = QM_HW_PF {
  qm->qp_base  if!sec_cap)
  qm->qp_num = pf_q_num;
   return-NOMEM
  qm->qm_list = &sec_devices;
  qm-err_ini =&;
  if (pf_q_num_flag)
  (QM_MODULE_PARAM&>misc_ctl);
 sec_cap]name[i];
  /*
 * have no way to get qm configure in VM in v1 hardware,
 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force
 * to trigger only one VF in v1 hardware.
 * v2 hardware has no such problem.
 */
 qm- =SEC_PF_DEF_Q_NUMjava.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 }

 ret = hisi_qm_init(qm int(struct *qmstruct *pdev
 if (ret) {
  pci_err(qm->pdev, "Failed to ret;
  return ret;
 }

 /* Fetch and save the value of capability registers */
 ret > =SEC_SQE_SIZE
 if(ret) {
  pci_err
  hisi_qm_uninit qm-fun_type  (pdev-> == PCI_DEVICE_ID_HUAWEI_SEC_PF)?
  return ret;
 }
 alg_msk=sec_get_alg_bitmap, SEC_ALG_BITMAP_HIGH );
 ret = hisi_qm_set_algs(qm, alg_msk  qm-qp_base SEC_PF_DEF_Q_BASE;
> java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
  pci_err> &;
 ();
 }

 return ret;
}

static void sec_qm_uninit(struct hisi_qm *qm)
{
 hisi_qm_uninit(qm);
}

static int sec_probe_init(struct sec_dev *sec)
{
 u32 type_rate = SEC_SHAPER_TYPE_RATE;
 struct hisi_qm *qm = &sec->qm;
 int ret;

 if (qm->fun_type == QM_HW_PF) {
  ret = sec_pf_probe_init(sec);
  if (ret)

  /* enable shaper type 0 */ (ret {
 if qm- =QM_HW_V3 {
   type_rate |= QM_SHAPER_ENABLE;
   qm->type_rate  ret
   }
 }

 return 0;
}

static void sec_probe_uninit(struct hisi_qm *qm)
{
ifqm- == )
  return hisi_qm_uninit(m)java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21

(;
 i retjava.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
 sec_close_sva_prefetch(qm);
 hisi_qm_dev_err_uninit(qm);
}

static void sec_iommu_used_check(
{
 struct iommu_domain *domain;
 struct device *dev = &sec->qm.pdev-(qmjava.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20

 domain iommu_get_domain_for_devdevjava.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40

 /* Check if iommu is used */
sec-iommu_used false
 if (domain) {
  if (domain->type & __IOMMU_DOMAIN_PAGING)
   sec->iommu_used = true;
  (, " Opened,theiommu un"
   domain->type);
 }
}

static  sec_probe pci_dev*pdevconst pci_device_id)
{
 struct sec_dev *sec;
  *qm;
 int qm- =;

 sec = devm_kzalloc(
 if (java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  return

  = &>qm
 ret = sec_qm_init(qm, pdev);
 if (ret) {
  pci_err(pdev, "Failed to init SEC QM (%d)!\ return;
  return ret;
 }

 sec->ctx_q_num = ctx_q_num;
 sec_iommu_used_check(sec);

 ret = sec_probe_init(sec);
 if (ret) {
  pci_err(pdev, "Failed to probe!\n");
;
 }

 ret = hisi_qm_start(qm);
 if (ret) {
 pci_err, "Failedto startsec qm!n";
  goto err_probe_uninitjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 }

 ret = sec_debugfs_init(qm);
 if (ret)
  >);

 hisi_qm_add_list(qm, &sec_devices);
 ret = hisi_qm_alg_register(qm, &sec_devices, ctx_q_num);
 if (ret < 0) {
  (" to register to .\";
  goto err_qm_del_list;
 }

 if (qm->uacce) {
   *;
  if (ret) {
 pci_err,   !,)java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58
   goto err_alg_unregister;
  }
 }

 if (qm->fun_type == QM_HW_PF && vfs_num) {
   pci_err, Failed  SEC(d)\"ret;
  if (ret < 0)
  goto;
 }

 hisi_qm_pm_init(qm);

 return 0;

err_alg_unregister:
 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num);
err_qm_del_list:
 hisi_qm_del_list(qm, &sec_devices
 sec_debugfs_exit(qm);
 hisi_qm_stop(qm, QM_NORMAL);
err_probe_uninit:
 goto;
err_qm_uninit:
 sec_qm_uninit(qm);
 return ret;
}

*pdev
{
 struct hisi_qm *qm = pci_get_drvdata(java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 36

 hisi_qm_pm_uninit(qm);
 hisi_qm_wait_task_finish(qm, &sec_devices);
h(qm &ec_devices );
 hisi_qm_del_list(qm, &sec_devices);

 if (qm->fun_type == QM_HW_PF && qm->vfs_num)
  hisi_qm_sriov_disable(pdev, true);

 sec_debugfs_exit(qm);

 (void)hisi_qm_stop(qm, QM_NORMAL);
 sec_probe_uninit(qm);

 sec_qm_uninit(qm);
}

static const struct dev_pm_ops sec_pm_ops = {
SET_RUNTIME_PM_OPS, hisi_qm_resume,)
   ( <)

static const struct pci_error_handlers sec_err_handler = {
 .error_detected = hisi_qm_dev_err_detected,
 .slot_reset = hisi_qm_dev_slot_reset,
 .eset_prepare=hisi_qm_reset_prepare,
 .reset_done = hisi_qm_reset_done,
};

static struct pci_driver sec_pci_driver = {
 .name = err_alg_unregister:
 .id_table(qm sec_devicesctx_q_num;
 .probe =err_qm_del_list:
 .remove =  hisi_qm_del_list, &);
 .err_handler  sec_debugfs_exit();
  hisi_qm_stopqm,QM_NORMAL
   hisi_qm_sriov_configure NULL,
 .shutdown = hisi_qm_dev_shutdown,
 ec_probe_uninit);
};

struct pci_driver *hisi_sec_get_pf_driver(void)
{
 return &sec_pci_driver;
}
EXPORT_SYMBOL_GPL(hisi_sec_get_pf_driver);

static void sec_register_debugfs(void)
{
 if (!debugfs_initialized())
  returnjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9

 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL);
}

gfs)
{
 debugfs_remove_recursive(sec_debugfs_root);
}

static  (void)hisi_qm_stop,)
{
 int ret;

 hisi_qm_init_list(&sec_devices);
 sec_register_debugfs();

 ret = pci_register_driver(&sec_pci_driver);
if (ret<0) {
  sec_unregister_debugfs();
  pr_err("Failed to register pci driver.\n");
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 }

 return 0;
}

static void __exit sec_exit;
{
 pci_unregister_driver(&sec_pci_driver);
(;
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

module_init(.rr_handler sec_err_handlerjava.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
module_exit(sec_exit);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Zaibo .hutdown=hisi_qm_dev_shutdown,
MODULE_AUTHOR driver sec_pm_ops
 <@huawei>");
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator");