Quelle  gc_9_4_2_offset.h   Sprache: C

/*
 * Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _gc_9_4_2_OFFSET_HEADER
#define _gc_9_4_2_OFFSET_HEADER



// addressBlock: didtind
// base address: 0x0
#define ixDIDT_SQ_CTRL0                                                                                0x0000
#define ixDIDT_SQ_CTRL2                                                                                0x0002
#define ixDIDT_SQ_STALL_CTRL                                                                           0x0004
#define ixDIDT_SQ_TUNING_CTRL                                                                          0x0005
#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL                                                              0x0006
#define ixDIDT_SQ_CTRL3                                                                                0x0007
#define ixDIDT_SQ_STALL_PATTERN_1_2                                                                    0x0008
#define ixDIDT_SQ_STALL_PATTERN_3_4                                                                    0x0009
#define ixDIDT_SQ_STALL_PATTERN_5_6                                                                    0x000a
#define ixDIDT_SQ_STALL_PATTERN_7                                                                      0x000b
#define ixDIDT_SQ_MPD_SCALE_FACTOR                                                                     0x000c
#define ixDIDT_SQ_THROTTLE_CNTL0                                                                       0x000d
#define ixDIDT_SQ_THROTTLE_CNTL1                                                                       0x000e
#define ixDIDT_SQ_THROTTLE_CNTL_STATUS                                                                 0x000f
#define ixDIDT_SQ_WEIGHT0_3                                                                            0x0010
#define ixDIDT_SQ_WEIGHT4_7                                                                            0x0011
#define ixDIDT_SQ_WEIGHT8_11                                                                           0x0012
#define ixDIDT_SQ_EDC_CTRL                                                                             0x0013
#define ixDIDT_SQ_THROTTLE_CTRL                                                                        0x0014
#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2                                                                0x0015
#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4                                                                0x0016
#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6                                                                0x0017
#define ixDIDT_SQ_EDC_STALL_PATTERN_7                                                                  0x0018
#define ixDIDT_SQ_EDC_STATUS                                                                           0x0019
#define ixDIDT_SQ_EDC_STALL_DELAY_1                                                                    0x001a
#define ixDIDT_SQ_EDC_STALL_DELAY_2                                                                    0x001b
#define ixDIDT_SQ_EDC_STALL_DELAY_3                                                                    0x001c
#define ixDIDT_SQ_EDC_STALL_DELAY_4                                                                    0x001d
#define ixDIDT_SQ_EDC_OVERFLOW                                                                         0x001e
#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA                                                              0x001f
#define ixDIDT_DB_CTRL0                                                                                0x0020
#define ixDIDT_DB_CTRL2                                                                                0x0022
#define ixDIDT_DB_STALL_CTRL                                                                           0x0024
#define ixDIDT_DB_TUNING_CTRL                                                                          0x0025
#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL                                                              0x0026
#define ixDIDT_DB_CTRL3                                                                                0x0027
#define ixDIDT_DB_STALL_PATTERN_1_2                                                                    0x0028
#define ixDIDT_DB_STALL_PATTERN_3_4                                                                    0x0029
#define ixDIDT_DB_STALL_PATTERN_5_6                                                                    0x002a
#define ixDIDT_DB_STALL_PATTERN_7                                                                      0x002b
#define ixDIDT_DB_MPD_SCALE_FACTOR                                                                     0x002c
#define ixDIDT_DB_THROTTLE_CNTL0                                                                       0x002d
#define ixDIDT_DB_THROTTLE_CNTL1                                                                       0x002e
#define ixDIDT_DB_THROTTLE_CNTL_STATUS                                                                 0x002f
#define ixDIDT_DB_WEIGHT0_3                                                                            0x0030
#define ixDIDT_DB_WEIGHT4_7                                                                            0x0031
#define ixDIDT_DB_WEIGHT8_11                                                                           0x0032
#define ixDIDT_DB_EDC_CTRL                                                                             0x0033
#define ixDIDT_DB_THROTTLE_CTRL                                                                        0x0034
#define ixDIDT_DB_EDC_STALL_PATTERN_1_2                                                                0x0035
#define ixDIDT_DB_EDC_STALL_PATTERN_3_4                                                                0x0036
#define ixDIDT_DB_EDC_STALL_PATTERN_5_6                                                                0x0037
#define ixDIDT_DB_EDC_STALL_PATTERN_7                                                                  0x0038
#define ixDIDT_DB_EDC_STATUS                                                                           0x0039
#define ixDIDT_DB_EDC_STALL_DELAY_1                                                                    0x003a
#define ixDIDT_DB_EDC_OVERFLOW                                                                         0x003e
#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA                                                              0x003f
#define ixDIDT_TD_CTRL0                                                                                0x0040
#define ixDIDT_TD_CTRL2                                                                                0x0042
#define ixDIDT_TD_STALL_CTRL                                                                           0x0044
#define ixDIDT_TD_TUNING_CTRL                                                                          0x0045
#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL                                                              0x0046
#define ixDIDT_TD_CTRL3                                                                                0x0047
#define ixDIDT_TD_STALL_PATTERN_1_2                                                                    0x0048
#define ixDIDT_TD_STALL_PATTERN_3_4                                                                    0x0049
#define ixDIDT_TD_STALL_PATTERN_5_6                                                                    0x004a
#define ixDIDT_TD_STALL_PATTERN_7                                                                      0x004b
#define ixDIDT_TD_MPD_SCALE_FACTOR                                                                     0x004c
#define ixDIDT_TD_THROTTLE_CNTL0                                                                       0x004d
#define ixDIDT_TD_THROTTLE_CNTL1                                                                       0x004e
#define ixDIDT_TD_THROTTLE_CNTL_STATUS                                                                 0x004f
#define ixDIDT_TD_WEIGHT0_3                                                                            0x0050
#define ixDIDT_TD_WEIGHT4_7                                                                            0x0051
#define ixDIDT_TD_WEIGHT8_11                                                                           0x0052
#define ixDIDT_TD_EDC_CTRL                                                                             0x0053
#define ixDIDT_TD_THROTTLE_CTRL                                                                        0x0054
#define ixDIDT_TD_EDC_STALL_PATTERN_1_2                                                                0x0055
#define ixDIDT_TD_EDC_STALL_PATTERN_3_4                                                                0x0056
#define ixDIDT_TD_EDC_STALL_PATTERN_5_6                                                                0x0057
#define ixDIDT_TD_EDC_STALL_PATTERN_7                                                                  0x0058
#define ixDIDT_TD_EDC_STATUS                                                                           0x0059
#define ixDIDT_TD_EDC_STALL_DELAY_1                                                                    0x005a
#define ixDIDT_TD_EDC_STALL_DELAY_2                                                                    0x005b
#define ixDIDT_TD_EDC_STALL_DELAY_3                                                                    0x005c
#define ixDIDT_TD_EDC_STALL_DELAY_4                                                                    0x005d
#define ixDIDT_TD_EDC_OVERFLOW                                                                         0x005e
#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA                                                              0x005f
#define ixDIDT_TCP_CTRL0                                                                               0x0060
#define ixDIDT_TCP_CTRL2                                                                               0x0062
#define ixDIDT_TCP_STALL_CTRL                                                                          0x0064
#define ixDIDT_TCP_TUNING_CTRL                                                                         0x0065
#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL                                                             0x0066
#define ixDIDT_TCP_CTRL3                                                                               0x0067
#define ixDIDT_TCP_STALL_PATTERN_1_2                                                                   0x0068
#define ixDIDT_TCP_STALL_PATTERN_3_4                                                                   0x0069
#define ixDIDT_TCP_STALL_PATTERN_5_6                                                                   0x006a
#define ixDIDT_TCP_STALL_PATTERN_7                                                                     0x006b
#define ixDIDT_TCP_MPD_SCALE_FACTOR                                                                    0x006c
#define ixDIDT_TCP_THROTTLE_CNTL0                                                                      0x006d
#define ixDIDT_TCP_THROTTLE_CNTL1                                                                      0x006e
#define ixDIDT_TCP_THROTTLE_CNTL_STATUS                                                                0x006f
#define ixDIDT_TCP_WEIGHT0_3                                                                           0x0070
#define ixDIDT_TCP_WEIGHT4_7                                                                           0x0071
#define ixDIDT_TCP_WEIGHT8_11                                                                          0x0072
#define ixDIDT_TCP_EDC_CTRL                                                                            0x0073
#define ixDIDT_TCP_THROTTLE_CTRL                                                                       0x0074
#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2                                                               0x0075
#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4                                                               0x0076
#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6                                                               0x0077
#define ixDIDT_TCP_EDC_STALL_PATTERN_7                                                                 0x0078
#define ixDIDT_TCP_EDC_STATUS                                                                          0x0079
#define ixDIDT_TCP_EDC_STALL_DELAY_1                                                                   0x007a
#define ixDIDT_TCP_EDC_STALL_DELAY_2                                                                   0x007b
#define ixDIDT_TCP_EDC_STALL_DELAY_3                                                                   0x007c
#define ixDIDT_TCP_EDC_STALL_DELAY_4                                                                   0x007d
#define ixDIDT_TCP_EDC_OVERFLOW                                                                        0x007e
#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA                                                             0x007f
#define ixDIDT_SQ_STALL_EVENT_COUNTER                                                                  0x00a0
#define ixDIDT_DB_STALL_EVENT_COUNTER                                                                  0x00a1
#define ixDIDT_TD_STALL_EVENT_COUNTER                                                                  0x00a2
#define ixDIDT_TCP_STALL_EVENT_COUNTER                                                                 0x00a3
#define ixDIDT_DBR_STALL_EVENT_COUNTER                                                                 0x00a4
#define ixDIDT_SQ_EDC_PCC_PERF_COUNTER                                                                 0x00a5
#define ixDIDT_TD_EDC_PCC_PERF_COUNTER                                                                 0x00a6
#define ixDIDT_TCP_EDC_PCC_PERF_COUNTER                                                                0x00a7
#define ixDIDT_DB_EDC_PCC_PERF_COUNTER                                                                 0x00a8
#define ixDIDT_DBR_EDC_PCC_PERF_COUNTER                                                                0x00a9
#define ixDIDT_SQ_CTRL1                                                                                0x00b0
#define ixDIDT_SQ_EDC_THRESHOLD                                                                        0x00b1
#define ixDIDT_DB_CTRL1                                                                                0x00b2
#define ixDIDT_DB_EDC_THRESHOLD                                                                        0x00b3
#define ixDIDT_TD_CTRL1                                                                                0x00b4
#define ixDIDT_TD_EDC_THRESHOLD                                                                        0x00b5
#define ixDIDT_TCP_CTRL1                                                                               0x00b6
#define ixDIDT_TCP_EDC_THRESHOLD                                                                       0x00b7


// addressBlock: gc_cpdec
// base address: 0x8200
#define regCP_CPC_STATUS                                                                                0x0084
#define regCP_CPC_STATUS_BASE_IDX                                                                       0
#define regCP_CPC_BUSY_STAT                                                                             0x0085
#define regCP_CPC_BUSY_STAT_BASE_IDX                                                                    0
#define regCP_CPC_STALLED_STAT1                                                                         0x0086
#define regCP_CPC_STALLED_STAT1_BASE_IDX                                                                0
#define regCP_CPF_STATUS                                                                                0x0087
#define regCP_CPF_STATUS_BASE_IDX                                                                       0
#define regCP_CPF_BUSY_STAT                                                                             0x0088
#define regCP_CPF_BUSY_STAT_BASE_IDX                                                                    0
#define regCP_CPF_STALLED_STAT1                                                                         0x0089
#define regCP_CPF_STALLED_STAT1_BASE_IDX                                                                0
#define regCP_CPC_GRBM_FREE_COUNT                                                                       0x008b
#define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX                                                              0
#define regCP_CPC_PRIV_VIOLATION_ADDR                                                                   0x008c
#define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX                                                          0
#define regCP_MEC_CNTL                                                                                  0x008d
#define regCP_MEC_CNTL_BASE_IDX                                                                         0
#define regCP_MEC_ME1_HEADER_DUMP                                                                       0x008e
#define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX                                                              0
#define regCP_MEC_ME2_HEADER_DUMP                                                                       0x008f
#define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX                                                              0
#define regCP_CPC_SCRATCH_INDEX                                                                         0x0090
#define regCP_CPC_SCRATCH_INDEX_BASE_IDX                                                                0
#define regCP_CPC_SCRATCH_DATA                                                                          0x0091
#define regCP_CPC_SCRATCH_DATA_BASE_IDX                                                                 0
#define regCP_CPF_GRBM_FREE_COUNT                                                                       0x0092
#define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX                                                              0
#define regCP_CPC_HALT_HYST_COUNT                                                                       0x00a7
#define regCP_CPC_HALT_HYST_COUNT_BASE_IDX                                                              0
#define regCP_CE_COMPARE_COUNT                                                                          0x00c0
#define regCP_CE_COMPARE_COUNT_BASE_IDX                                                                 0
#define regCP_CE_DE_COUNT                                                                               0x00c1
#define regCP_CE_DE_COUNT_BASE_IDX                                                                      0
#define regCP_DE_CE_COUNT                                                                               0x00c2
#define regCP_DE_CE_COUNT_BASE_IDX                                                                      0
#define regCP_DE_LAST_INVAL_COUNT                                                                       0x00c3
#define regCP_DE_LAST_INVAL_COUNT_BASE_IDX                                                              0
#define regCP_DE_DE_COUNT                                                                               0x00c4
#define regCP_DE_DE_COUNT_BASE_IDX                                                                      0
#define regCP_STALLED_STAT3                                                                             0x019c
#define regCP_STALLED_STAT3_BASE_IDX                                                                    0
#define regCP_STALLED_STAT1                                                                             0x019d
#define regCP_STALLED_STAT1_BASE_IDX                                                                    0
#define regCP_STALLED_STAT2                                                                             0x019e
#define regCP_STALLED_STAT2_BASE_IDX                                                                    0
#define regCP_BUSY_STAT                                                                                 0x019f
#define regCP_BUSY_STAT_BASE_IDX                                                                        0
#define regCP_STAT                                                                                      0x01a0
#define regCP_STAT_BASE_IDX                                                                             0
#define regCP_ME_HEADER_DUMP                                                                            0x01a1
#define regCP_ME_HEADER_DUMP_BASE_IDX                                                                   0
#define regCP_PFP_HEADER_DUMP                                                                           0x01a2
#define regCP_PFP_HEADER_DUMP_BASE_IDX                                                                  0
#define regCP_GRBM_FREE_COUNT                                                                           0x01a3
#define regCP_GRBM_FREE_COUNT_BASE_IDX                                                                  0
#define regCP_CE_HEADER_DUMP                                                                            0x01a4
#define regCP_CE_HEADER_DUMP_BASE_IDX                                                                   0
#define regCP_PFP_INSTR_PNTR                                                                            0x01a5
#define regCP_PFP_INSTR_PNTR_BASE_IDX                                                                   0
#define regCP_ME_INSTR_PNTR                                                                             0x01a6
#define regCP_ME_INSTR_PNTR_BASE_IDX                                                                    0
#define regCP_CE_INSTR_PNTR                                                                             0x01a7
#define regCP_CE_INSTR_PNTR_BASE_IDX                                                                    0
#define regCP_MEC1_INSTR_PNTR                                                                           0x01a8
#define regCP_MEC1_INSTR_PNTR_BASE_IDX                                                                  0
#define regCP_MEC2_INSTR_PNTR                                                                           0x01a9
#define regCP_MEC2_INSTR_PNTR_BASE_IDX                                                                  0
#define regCP_CSF_STAT                                                                                  0x01b4
#define regCP_CSF_STAT_BASE_IDX                                                                         0
#define regCP_ME_CNTL                                                                                   0x01b6
#define regCP_ME_CNTL_BASE_IDX                                                                          0
#define regCP_CNTX_STAT                                                                                 0x01b8
#define regCP_CNTX_STAT_BASE_IDX                                                                        0
#define regCP_ME_PREEMPTION                                                                             0x01b9
#define regCP_ME_PREEMPTION_BASE_IDX                                                                    0
#define regCP_ROQ_THRESHOLDS                                                                            0x01bc
#define regCP_ROQ_THRESHOLDS_BASE_IDX                                                                   0
#define regCP_MEQ_STQ_THRESHOLD                                                                         0x01bd
#define regCP_MEQ_STQ_THRESHOLD_BASE_IDX                                                                0
#define regCP_RB2_RPTR                                                                                  0x01be
#define regCP_RB2_RPTR_BASE_IDX                                                                         0
#define regCP_RB1_RPTR                                                                                  0x01bf
#define regCP_RB1_RPTR_BASE_IDX                                                                         0
#define regCP_RB0_RPTR                                                                                  0x01c0
#define regCP_RB0_RPTR_BASE_IDX                                                                         0
#define regCP_RB_RPTR                                                                                   0x01c0
#define regCP_RB_RPTR_BASE_IDX                                                                          0
#define regCP_RB_WPTR_DELAY                                                                             0x01c1
#define regCP_RB_WPTR_DELAY_BASE_IDX                                                                    0
#define regCP_RB_WPTR_POLL_CNTL                                                                         0x01c2
#define regCP_RB_WPTR_POLL_CNTL_BASE_IDX                                                                0
#define regCP_ROQ1_THRESHOLDS                                                                           0x01d5
#define regCP_ROQ1_THRESHOLDS_BASE_IDX                                                                  0
#define regCP_ROQ2_THRESHOLDS                                                                           0x01d6
#define regCP_ROQ2_THRESHOLDS_BASE_IDX                                                                  0
#define regCP_STQ_THRESHOLDS                                                                            0x01d7
#define regCP_STQ_THRESHOLDS_BASE_IDX                                                                   0
#define regCP_QUEUE_THRESHOLDS                                                                          0x01d8
#define regCP_QUEUE_THRESHOLDS_BASE_IDX                                                                 0
#define regCP_MEQ_THRESHOLDS                                                                            0x01d9
#define regCP_MEQ_THRESHOLDS_BASE_IDX                                                                   0
#define regCP_ROQ_AVAIL                                                                                 0x01da
#define regCP_ROQ_AVAIL_BASE_IDX                                                                        0
#define regCP_STQ_AVAIL                                                                                 0x01db
#define regCP_STQ_AVAIL_BASE_IDX                                                                        0
#define regCP_ROQ2_AVAIL                                                                                0x01dc
#define regCP_ROQ2_AVAIL_BASE_IDX                                                                       0
#define regCP_MEQ_AVAIL                                                                                 0x01dd
#define regCP_MEQ_AVAIL_BASE_IDX                                                                        0
#define regCP_CMD_INDEX                                                                                 0x01de
#define regCP_CMD_INDEX_BASE_IDX                                                                        0
#define regCP_CMD_DATA                                                                                  0x01df
#define regCP_CMD_DATA_BASE_IDX                                                                         0
#define regCP_ROQ_RB_STAT                                                                               0x01e0
#define regCP_ROQ_RB_STAT_BASE_IDX                                                                      0
#define regCP_ROQ_IB1_STAT                                                                              0x01e1
#define regCP_ROQ_IB1_STAT_BASE_IDX                                                                     0
#define regCP_ROQ_IB2_STAT                                                                              0x01e2
#define regCP_ROQ_IB2_STAT_BASE_IDX                                                                     0
#define regCP_STQ_STAT                                                                                  0x01e3
#define regCP_STQ_STAT_BASE_IDX                                                                         0
#define regCP_STQ_WR_STAT                                                                               0x01e4
#define regCP_STQ_WR_STAT_BASE_IDX                                                                      0
#define regCP_MEQ_STAT                                                                                  0x01e5
#define regCP_MEQ_STAT_BASE_IDX                                                                         0
#define regCP_CEQ1_AVAIL                                                                                0x01e6
#define regCP_CEQ1_AVAIL_BASE_IDX                                                                       0
#define regCP_CEQ2_AVAIL                                                                                0x01e7
#define regCP_CEQ2_AVAIL_BASE_IDX                                                                       0
#define regCP_CE_ROQ_RB_STAT                                                                            0x01e8
#define regCP_CE_ROQ_RB_STAT_BASE_IDX                                                                   0
#define regCP_CE_ROQ_IB1_STAT                                                                           0x01e9
#define regCP_CE_ROQ_IB1_STAT_BASE_IDX                                                                  0
#define regCP_CE_ROQ_IB2_STAT                                                                           0x01ea
#define regCP_CE_ROQ_IB2_STAT_BASE_IDX                                                                  0
#define regCP_PRIV_VIOLATION_ADDR                                                                       0x01fa
#define regCP_PRIV_VIOLATION_ADDR_BASE_IDX                                                              0


// addressBlock: gc_cppdec
// base address: 0xc080
#define regCP_EOPQ_WAIT_TIME                                                                            0x1035
#define regCP_EOPQ_WAIT_TIME_BASE_IDX                                                                   0
#define regCP_CPC_MGCG_SYNC_CNTL                                                                        0x1036
#define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX                                                               0
#define regCPC_INT_INFO                                                                                 0x1037
#define regCPC_INT_INFO_BASE_IDX                                                                        0
#define regCP_VIRT_STATUS                                                                               0x1038
#define regCP_VIRT_STATUS_BASE_IDX                                                                      0
#define regCPC_INT_ADDR                                                                                 0x1039
#define regCPC_INT_ADDR_BASE_IDX                                                                        0
#define regCPC_INT_PASID                                                                                0x103a
#define regCPC_INT_PASID_BASE_IDX                                                                       0
#define regCP_GFX_ERROR                                                                                 0x103b
#define regCP_GFX_ERROR_BASE_IDX                                                                        0
#define regCPG_UTCL1_CNTL                                                                               0x103c
#define regCPG_UTCL1_CNTL_BASE_IDX                                                                      0
#define regCPC_UTCL1_CNTL                                                                               0x103d
#define regCPC_UTCL1_CNTL_BASE_IDX                                                                      0
#define regCPF_UTCL1_CNTL                                                                               0x103e
#define regCPF_UTCL1_CNTL_BASE_IDX                                                                      0
#define regCP_AQL_SMM_STATUS                                                                            0x103f
#define regCP_AQL_SMM_STATUS_BASE_IDX                                                                   0
#define regCP_RB0_BASE                                                                                  0x1040
#define regCP_RB0_BASE_BASE_IDX                                                                         0
#define regCP_RB_BASE                                                                                   0x1040
#define regCP_RB_BASE_BASE_IDX                                                                          0
#define regCP_RB0_CNTL                                                                                  0x1041
#define regCP_RB0_CNTL_BASE_IDX                                                                         0
#define regCP_RB_CNTL                                                                                   0x1041
#define regCP_RB_CNTL_BASE_IDX                                                                          0
#define regCP_RB_RPTR_WR                                                                                0x1042
#define regCP_RB_RPTR_WR_BASE_IDX                                                                       0
#define regCP_RB0_RPTR_ADDR                                                                             0x1043
#define regCP_RB0_RPTR_ADDR_BASE_IDX                                                                    0
#define regCP_RB_RPTR_ADDR                                                                              0x1043
#define regCP_RB_RPTR_ADDR_BASE_IDX                                                                     0
#define regCP_RB0_RPTR_ADDR_HI                                                                          0x1044
#define regCP_RB0_RPTR_ADDR_HI_BASE_IDX                                                                 0
#define regCP_RB_RPTR_ADDR_HI                                                                           0x1044
#define regCP_RB_RPTR_ADDR_HI_BASE_IDX                                                                  0
#define regCP_RB0_BUFSZ_MASK                                                                            0x1045
#define regCP_RB0_BUFSZ_MASK_BASE_IDX                                                                   0
#define regCP_RB_BUFSZ_MASK                                                                             0x1045
#define regCP_RB_BUFSZ_MASK_BASE_IDX                                                                    0
#define regCP_RB_WPTR_POLL_ADDR_LO                                                                      0x1046
#define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                             0
#define regCP_RB_WPTR_POLL_ADDR_HI                                                                      0x1047
#define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                             0
#define regCP_INT_CNTL                                                                                  0x1049
#define regCP_INT_CNTL_BASE_IDX                                                                         0
#define regCP_INT_STATUS                                                                                0x104a
#define regCP_INT_STATUS_BASE_IDX                                                                       0
#define regCP_DEVICE_ID                                                                                 0x104b
#define regCP_DEVICE_ID_BASE_IDX                                                                        0
#define regCP_ME0_PIPE_PRIORITY_CNTS                                                                    0x104c
#define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX                                                           0
#define regCP_RING_PRIORITY_CNTS                                                                        0x104c
#define regCP_RING_PRIORITY_CNTS_BASE_IDX                                                               0
#define regCP_ME0_PIPE0_PRIORITY                                                                        0x104d
#define regCP_ME0_PIPE0_PRIORITY_BASE_IDX                                                               0
#define regCP_RING0_PRIORITY                                                                            0x104d
#define regCP_RING0_PRIORITY_BASE_IDX                                                                   0
#define regCP_ME0_PIPE1_PRIORITY                                                                        0x104e
#define regCP_ME0_PIPE1_PRIORITY_BASE_IDX                                                               0
#define regCP_RING1_PRIORITY                                                                            0x104e
#define regCP_RING1_PRIORITY_BASE_IDX                                                                   0
#define regCP_ME0_PIPE2_PRIORITY                                                                        0x104f
#define regCP_ME0_PIPE2_PRIORITY_BASE_IDX                                                               0
#define regCP_RING2_PRIORITY                                                                            0x104f
#define regCP_RING2_PRIORITY_BASE_IDX                                                                   0
#define regCP_FATAL_ERROR                                                                               0x1050
#define regCP_FATAL_ERROR_BASE_IDX                                                                      0
#define regCP_RB_VMID                                                                                   0x1051
#define regCP_RB_VMID_BASE_IDX                                                                          0
#define regCP_ME0_PIPE0_VMID                                                                            0x1052
#define regCP_ME0_PIPE0_VMID_BASE_IDX                                                                   0
#define regCP_ME0_PIPE1_VMID                                                                            0x1053
#define regCP_ME0_PIPE1_VMID_BASE_IDX                                                                   0
#define regCP_RB0_WPTR                                                                                  0x1054
#define regCP_RB0_WPTR_BASE_IDX                                                                         0
#define regCP_RB_WPTR                                                                                   0x1054
#define regCP_RB_WPTR_BASE_IDX                                                                          0
#define regCP_RB0_WPTR_HI                                                                               0x1055
#define regCP_RB0_WPTR_HI_BASE_IDX                                                                      0
#define regCP_RB_WPTR_HI                                                                                0x1055
#define regCP_RB_WPTR_HI_BASE_IDX                                                                       0
#define regCP_RB1_WPTR                                                                                  0x1056
#define regCP_RB1_WPTR_BASE_IDX                                                                         0
#define regCP_RB1_WPTR_HI                                                                               0x1057
#define regCP_RB1_WPTR_HI_BASE_IDX                                                                      0
#define regCP_RB2_WPTR                                                                                  0x1058
#define regCP_RB2_WPTR_BASE_IDX                                                                         0
#define regCP_RB_DOORBELL_CONTROL                                                                       0x1059
#define regCP_RB_DOORBELL_CONTROL_BASE_IDX                                                              0
#define regCP_RB_DOORBELL_RANGE_LOWER                                                                   0x105a
#define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX                                                          0
#define regCP_RB_DOORBELL_RANGE_UPPER                                                                   0x105b
#define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX                                                          0
#define regCP_MEC_DOORBELL_RANGE_LOWER                                                                  0x105c
#define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX                                                         0
#define regCP_MEC_DOORBELL_RANGE_UPPER                                                                  0x105d
#define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX                                                         0
#define regCPG_UTCL1_ERROR                                                                              0x105e
#define regCPG_UTCL1_ERROR_BASE_IDX                                                                     0
#define regCPC_UTCL1_ERROR                                                                              0x105f
#define regCPC_UTCL1_ERROR_BASE_IDX                                                                     0
#define regCP_RB1_BASE                                                                                  0x1060
#define regCP_RB1_BASE_BASE_IDX                                                                         0
#define regCP_RB1_CNTL                                                                                  0x1061
#define regCP_RB1_CNTL_BASE_IDX                                                                         0
#define regCP_RB1_RPTR_ADDR                                                                             0x1062
#define regCP_RB1_RPTR_ADDR_BASE_IDX                                                                    0
#define regCP_RB1_RPTR_ADDR_HI                                                                          0x1063
#define regCP_RB1_RPTR_ADDR_HI_BASE_IDX                                                                 0
#define regCP_RB2_BASE                                                                                  0x1065
#define regCP_RB2_BASE_BASE_IDX                                                                         0
#define regCP_RB2_CNTL                                                                                  0x1066
#define regCP_RB2_CNTL_BASE_IDX                                                                         0
#define regCP_RB2_RPTR_ADDR                                                                             0x1067
#define regCP_RB2_RPTR_ADDR_BASE_IDX                                                                    0
#define regCP_RB2_RPTR_ADDR_HI                                                                          0x1068
#define regCP_RB2_RPTR_ADDR_HI_BASE_IDX                                                                 0
#define regCP_RB0_ACTIVE                                                                                0x1069
#define regCP_RB0_ACTIVE_BASE_IDX                                                                       0
#define regCP_RB_ACTIVE                                                                                 0x1069
#define regCP_RB_ACTIVE_BASE_IDX                                                                        0
#define regCP_INT_CNTL_RING0                                                                            0x106a
#define regCP_INT_CNTL_RING0_BASE_IDX                                                                   0
#define regCP_INT_CNTL_RING1                                                                            0x106b
#define regCP_INT_CNTL_RING1_BASE_IDX                                                                   0
#define regCP_INT_CNTL_RING2                                                                            0x106c
#define regCP_INT_CNTL_RING2_BASE_IDX                                                                   0
#define regCP_INT_STATUS_RING0                                                                          0x106d
#define regCP_INT_STATUS_RING0_BASE_IDX                                                                 0
#define regCP_INT_STATUS_RING1                                                                          0x106e
#define regCP_INT_STATUS_RING1_BASE_IDX                                                                 0
#define regCP_INT_STATUS_RING2                                                                          0x106f
#define regCP_INT_STATUS_RING2_BASE_IDX                                                                 0
#define regCP_ME_F32_INTERRUPT                                                                          0x1073
#define regCP_ME_F32_INTERRUPT_BASE_IDX                                                                 0
#define regCP_PFP_F32_INTERRUPT                                                                         0x1074
#define regCP_PFP_F32_INTERRUPT_BASE_IDX                                                                0
#define regCP_CE_F32_INTERRUPT                                                                          0x1075
#define regCP_CE_F32_INTERRUPT_BASE_IDX                                                                 0
#define regCP_MEC1_F32_INTERRUPT                                                                        0x1076
#define regCP_MEC1_F32_INTERRUPT_BASE_IDX                                                               0
#define regCP_MEC2_F32_INTERRUPT                                                                        0x1077
#define regCP_MEC2_F32_INTERRUPT_BASE_IDX                                                               0
#define regCP_PWR_CNTL                                                                                  0x1078
#define regCP_PWR_CNTL_BASE_IDX                                                                         0
#define regCP_MEM_SLP_CNTL                                                                              0x1079
#define regCP_MEM_SLP_CNTL_BASE_IDX                                                                     0
#define regCP_ECC_DMA_FIRST_OCCURRENCE                                                                  0x107a
#define regCP_ECC_DMA_FIRST_OCCURRENCE_BASE_IDX                                                         0
#define regCP_ECC_FIRSTOCCURRENCE                                                                       0x107a
#define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX                                                              0
#define regCP_ECC_FIRSTOCCURRENCE_RING0                                                                 0x107b
#define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX                                                        0
#define regCP_ECC_FIRSTOCCURRENCE_RING1                                                                 0x107c
#define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX                                                        0
#define regCP_ECC_FIRSTOCCURRENCE_RING2                                                                 0x107d
#define regCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX                                                        0
#define regGB_EDC_MODE                                                                                  0x107e
#define regGB_EDC_MODE_BASE_IDX                                                                         0
#define regCP_PQ_WPTR_POLL_CNTL                                                                         0x1083
#define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX                                                                0
#define regCP_PQ_WPTR_POLL_CNTL1                                                                        0x1084
#define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX                                                               0
#define regCP_ME1_PIPE0_INT_CNTL                                                                        0x1085
#define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX                                                               0
#define regCP_ME1_PIPE1_INT_CNTL                                                                        0x1086
#define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX                                                               0
#define regCP_ME1_PIPE2_INT_CNTL                                                                        0x1087
#define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX                                                               0
#define regCP_ME1_PIPE3_INT_CNTL                                                                        0x1088
#define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX                                                               0
#define regCP_ME2_PIPE0_INT_CNTL                                                                        0x1089
#define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX                                                               0
#define regCP_ME2_PIPE1_INT_CNTL                                                                        0x108a
#define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX                                                               0
#define regCP_ME2_PIPE2_INT_CNTL                                                                        0x108b
#define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX                                                               0
#define regCP_ME2_PIPE3_INT_CNTL                                                                        0x108c
#define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX                                                               0
#define regCP_ME1_PIPE0_INT_STATUS                                                                      0x108d
#define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX                                                             0
#define regCP_ME1_PIPE1_INT_STATUS                                                                      0x108e
#define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX                                                             0
#define regCP_ME1_PIPE2_INT_STATUS                                                                      0x108f
#define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX                                                             0
#define regCP_ME1_PIPE3_INT_STATUS                                                                      0x1090
#define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX                                                             0
#define regCP_ME2_PIPE0_INT_STATUS                                                                      0x1091
#define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX                                                             0
#define regCP_ME2_PIPE1_INT_STATUS                                                                      0x1092
#define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX                                                             0
#define regCP_ME2_PIPE2_INT_STATUS                                                                      0x1093
#define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX                                                             0
#define regCP_ME2_PIPE3_INT_STATUS                                                                      0x1094
#define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX                                                             0
#define regCP_ME1_INT_STAT_DEBUG                                                                        0x1095
#define regCP_ME1_INT_STAT_DEBUG_BASE_IDX                                                               0
#define regCP_ME2_INT_STAT_DEBUG                                                                        0x1096
#define regCP_ME2_INT_STAT_DEBUG_BASE_IDX                                                               0
#define regCC_GC_EDC_CONFIG                                                                             0x1098
#define regCC_GC_EDC_CONFIG_BASE_IDX                                                                    0
#define regCP_ME1_PIPE_PRIORITY_CNTS                                                                    0x1099
#define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX                                                           0
#define regCP_ME1_PIPE0_PRIORITY                                                                        0x109a
#define regCP_ME1_PIPE0_PRIORITY_BASE_IDX                                                               0
#define regCP_ME1_PIPE1_PRIORITY                                                                        0x109b
#define regCP_ME1_PIPE1_PRIORITY_BASE_IDX                                                               0
#define regCP_ME1_PIPE2_PRIORITY                                                                        0x109c
#define regCP_ME1_PIPE2_PRIORITY_BASE_IDX                                                               0
#define regCP_ME1_PIPE3_PRIORITY                                                                        0x109d
#define regCP_ME1_PIPE3_PRIORITY_BASE_IDX                                                               0
#define regCP_ME2_PIPE_PRIORITY_CNTS                                                                    0x109e
#define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX                                                           0
#define regCP_ME2_PIPE0_PRIORITY                                                                        0x109f
#define regCP_ME2_PIPE0_PRIORITY_BASE_IDX                                                               0
#define regCP_ME2_PIPE1_PRIORITY                                                                        0x10a0
#define regCP_ME2_PIPE1_PRIORITY_BASE_IDX                                                               0
#define regCP_ME2_PIPE2_PRIORITY                                                                        0x10a1
#define regCP_ME2_PIPE2_PRIORITY_BASE_IDX                                                               0
#define regCP_ME2_PIPE3_PRIORITY                                                                        0x10a2
#define regCP_ME2_PIPE3_PRIORITY_BASE_IDX                                                               0
#define regCP_CE_PRGRM_CNTR_START                                                                       0x10a3
#define regCP_CE_PRGRM_CNTR_START_BASE_IDX                                                              0
#define regCP_PFP_PRGRM_CNTR_START                                                                      0x10a4
#define regCP_PFP_PRGRM_CNTR_START_BASE_IDX                                                             0
#define regCP_ME_PRGRM_CNTR_START                                                                       0x10a5
#define regCP_ME_PRGRM_CNTR_START_BASE_IDX                                                              0
#define regCP_MEC1_PRGRM_CNTR_START                                                                     0x10a6
#define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX                                                            0
#define regCP_MEC2_PRGRM_CNTR_START                                                                     0x10a7
#define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX                                                            0
#define regCP_CE_INTR_ROUTINE_START                                                                     0x10a8
#define regCP_CE_INTR_ROUTINE_START_BASE_IDX                                                            0
#define regCP_PFP_INTR_ROUTINE_START                                                                    0x10a9
#define regCP_PFP_INTR_ROUTINE_START_BASE_IDX                                                           0
#define regCP_ME_INTR_ROUTINE_START                                                                     0x10aa
#define regCP_ME_INTR_ROUTINE_START_BASE_IDX                                                            0
#define regCP_MEC1_INTR_ROUTINE_START                                                                   0x10ab
#define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX                                                          0
#define regCP_MEC2_INTR_ROUTINE_START                                                                   0x10ac
#define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX                                                          0
#define regCP_CONTEXT_CNTL                                                                              0x10ad
#define regCP_CONTEXT_CNTL_BASE_IDX                                                                     0
#define regCP_MAX_CONTEXT                                                                               0x10ae
#define regCP_MAX_CONTEXT_BASE_IDX                                                                      0
#define regCP_IQ_WAIT_TIME1                                                                             0x10af
#define regCP_IQ_WAIT_TIME1_BASE_IDX                                                                    0
#define regCP_IQ_WAIT_TIME2                                                                             0x10b0
#define regCP_IQ_WAIT_TIME2_BASE_IDX                                                                    0
#define regCP_RB0_BASE_HI                                                                               0x10b1
#define regCP_RB0_BASE_HI_BASE_IDX                                                                      0
#define regCP_RB1_BASE_HI                                                                               0x10b2
#define regCP_RB1_BASE_HI_BASE_IDX                                                                      0
#define regCP_VMID_RESET                                                                                0x10b3
#define regCP_VMID_RESET_BASE_IDX                                                                       0
#define regCPC_INT_CNTL                                                                                 0x10b4
#define regCPC_INT_CNTL_BASE_IDX                                                                        0
#define regCPC_INT_STATUS                                                                               0x10b5
#define regCPC_INT_STATUS_BASE_IDX                                                                      0
#define regCP_VMID_PREEMPT                                                                              0x10b6
#define regCP_VMID_PREEMPT_BASE_IDX                                                                     0
#define regCPC_INT_CNTX_ID                                                                              0x10b7
#define regCPC_INT_CNTX_ID_BASE_IDX                                                                     0
#define regCP_PQ_STATUS                                                                                 0x10b8
#define regCP_PQ_STATUS_BASE_IDX                                                                        0
#define regCP_CPC_IC_BASE_LO                                                                            0x10b9
#define regCP_CPC_IC_BASE_LO_BASE_IDX                                                                   0
#define regCP_CPC_IC_BASE_HI                                                                            0x10ba
#define regCP_CPC_IC_BASE_HI_BASE_IDX                                                                   0
#define regCP_CPC_IC_BASE_CNTL                                                                          0x10bb
#define regCP_CPC_IC_BASE_CNTL_BASE_IDX                                                                 0
#define regCP_CPC_IC_OP_CNTL                                                                            0x10bc
#define regCP_CPC_IC_OP_CNTL_BASE_IDX                                                                   0
#define regCP_MEC1_F32_INT_DIS                                                                          0x10bd
#define regCP_MEC1_F32_INT_DIS_BASE_IDX                                                                 0
#define regCP_MEC2_F32_INT_DIS                                                                          0x10be
#define regCP_MEC2_F32_INT_DIS_BASE_IDX                                                                 0
#define regCP_VMID_STATUS                                                                               0x10bf
#define regCP_VMID_STATUS_BASE_IDX                                                                      0


// addressBlock: gc_cppdec2
// base address: 0xc600
#define regCP_RB_DOORBELL_CONTROL_SCH_0                                                                 0x1180
#define regCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX                                                        0
#define regCP_RB_DOORBELL_CONTROL_SCH_1                                                                 0x1181
#define regCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX                                                        0
#define regCP_RB_DOORBELL_CONTROL_SCH_2                                                                 0x1182
#define regCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX                                                        0
#define regCP_RB_DOORBELL_CONTROL_SCH_3                                                                 0x1183
#define regCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX                                                        0
#define regCP_RB_DOORBELL_CONTROL_SCH_4                                                                 0x1184
#define regCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX                                                        0
#define regCP_RB_DOORBELL_CONTROL_SCH_5                                                                 0x1185
#define regCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX                                                        0
#define regCP_RB_DOORBELL_CONTROL_SCH_6                                                                 0x1186
#define regCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX                                                        0
#define regCP_RB_DOORBELL_CONTROL_SCH_7                                                                 0x1187
#define regCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX                                                        0
#define regCP_RB_DOORBELL_CLEAR                                                                         0x1188
#define regCP_RB_DOORBELL_CLEAR_BASE_IDX                                                                0
#define regCPF_EDC_TAG_CNT                                                                              0x1189
#define regCPF_EDC_TAG_CNT_BASE_IDX                                                                     0
#define regCPF_EDC_ROQ_CNT                                                                              0x118a
#define regCPF_EDC_ROQ_CNT_BASE_IDX                                                                     0
#define regCPG_EDC_TAG_CNT                                                                              0x118b
#define regCPG_EDC_TAG_CNT_BASE_IDX                                                                     0
#define regCPG_EDC_DMA_CNT                                                                              0x118d
#define regCPG_EDC_DMA_CNT_BASE_IDX                                                                     0
#define regCPC_EDC_SCRATCH_CNT                                                                          0x118e
#define regCPC_EDC_SCRATCH_CNT_BASE_IDX                                                                 0
#define regCPC_EDC_UCODE_CNT                                                                            0x118f
#define regCPC_EDC_UCODE_CNT_BASE_IDX                                                                   0
#define regDC_EDC_STATE_CNT                                                                             0x1191
#define regDC_EDC_STATE_CNT_BASE_IDX                                                                    0
--> --------------------

--> maximum size reached

--> --------------------