Quelle  sparx5_main_regs.h   Sprache: C

/* SPDX-License-Identifier: GPL-2.0+
 * Microchip Sparx5 Switch driver
 *
 * Copyright (c) 2024 Microchip Technology Inc.
 */

/* This file is autogenerated by cml-utils 2024-10-04 10:40:40 +0200.
 * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b
 */

#ifndef _SPARX5_MAIN_REGS_H_
#define _SPARX5_MAIN_REGS_H_

#include <linux/bitfield.h>
#include <linux/types.h>
#include <linux/bug.h>

#include "sparx5_regs.h"

enum sparx5_target {
 TARGET_ANA_AC = 1,
 TARGET_ANA_ACL = 2,
 TARGET_ANA_AC_POL = 4,
 TARGET_ANA_AC_SDLB = 5,
 TARGET_ANA_CL = 6,
 TARGET_ANA_L2 = 7,
 TARGET_ANA_L3 = 8,
 TARGET_ASM = 9,
 TARGET_CLKGEN = 11,
 TARGET_CPU = 12,
 TARGET_DEV10G = 17,
 TARGET_DEV25G = 29,
 TARGET_DEV2G5 = 37,
 TARGET_DEV5G = 102,
 TARGET_DSM = 115,
 TARGET_EACL = 116,
 TARGET_FDMA = 117,
 TARGET_GCB = 118,
 TARGET_HSCH = 119,
 TARGET_HSIO_WRAP = 120,
 TARGET_LRN = 122,
 TARGET_PCEP = 129,
 TARGET_PCS10G_BR = 132,
 TARGET_PCS25G_BR = 144,
 TARGET_PCS5G_BR = 160,
 TARGET_PORT_CONF = 173,
 TARGET_PTP = 174,
 TARGET_QFWD = 175,
 TARGET_QRES = 176,
 TARGET_QS = 177,
 TARGET_QSYS = 178,
 TARGET_REW = 179,
 TARGET_VCAP_ES0 = 323,
 TARGET_VCAP_ES2 = 324,
 TARGET_VCAP_SUPER = 326,
 TARGET_VOP = 327,
 TARGET_XQS = 331,
 TARGET_DEVRGMII = 392,
 NUM_TARGETS = 517
};

/* sparx5_main.c
 *
 * This is used by the register macros to access chip differences (if any) in:
 * target size, register address, register count, group address, group count,
 * group size, field position and field size.
 */
extern const struct sparx5_regs *regs;

/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
#define spx5_field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
#define spx5_field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))

#define __REG(...)    __VA_ARGS__

/* ANA_AC:RAM_CTRL:RAM_INIT */
#define ANA_AC_RAM_INIT                                                        \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_RAM_CTRL], 0, 1, 4, 0,\
       0, 1, 4)

#define ANA_AC_RAM_INIT_RAM_INIT                 BIT(1)
#define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\
 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
#define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\
 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)

#define ANA_AC_RAM_INIT_RAM_CFG_HOOK             BIT(0)
#define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\
 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
#define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\
 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)

/* ANA_AC:PS_COMMON:OWN_UPSID */
#define ANA_AC_OWN_UPSID(r)                                                    \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PS_COMMON], 0, 1, 352,\
       52, r, regs->rcnt[RC_ANA_AC_OWN_UPSID], 4)

#define ANA_AC_OWN_UPSID_OWN_UPSID               GENMASK(4, 0)
#define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\
 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
#define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\
 FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x)

/* ANA_AC:MIRROR_PROBE:PROBE_CFG */
#define ANA_AC_PROBE_CFG(g)                                                    \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3,  \
       32, 0, 0, 1, 4)

#define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD     GENMASK(31, 27)
#define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\
 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x)
#define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\
 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x)

#define ANA_AC_PROBE_CFG_PROBE_CPU_SET           GENMASK(26, 19)
#define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\
 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x)
#define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\
 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x)

#define ANA_AC_PROBE_CFG_PROBE_VID               GENMASK(18, 6)
#define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\
 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VID, x)
#define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\
 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VID, x)

#define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE         GENMASK(5, 4)
#define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\
 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x)
#define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\
 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x)

#define ANA_AC_PROBE_CFG_PROBE_MAC_MODE          GENMASK(3, 2)
#define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\
 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x)
#define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\
 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x)

#define ANA_AC_PROBE_CFG_PROBE_DIRECTION         GENMASK(1, 0)
#define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\
 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x)
#define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\
 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x)

/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */
#define ANA_AC_PROBE_PORT_CFG(g)                                               \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3,  \
       32, 8, 0, 1, 4)

/* SPARX5 ONLY */
/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */
#define ANA_AC_PROBE_PORT_CFG1(g)                                              \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3,  \
       32, 12, 0, 1, 4)

/* SPARX5 ONLY */
/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */
#define ANA_AC_PROBE_PORT_CFG2(g)                                              \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3,  \
       32, 16, 0, 1, 4)

#define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2  BIT(0)
#define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\
 FIELD_PREP(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x)
#define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\
 FIELD_GET(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x)

/* ANA_AC:SRC:SRC_CFG */
#define ANA_AC_SRC_CFG(g)                                                      \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g,              \
       regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 0, 0, 1, 4)

/* SPARX5 ONLY */
/* ANA_AC:SRC:SRC_CFG1 */
#define ANA_AC_SRC_CFG1(g)                                                     \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g,              \
       regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 4, 0, 1, 4)

/* SPARX5 ONLY */
/* ANA_AC:SRC:SRC_CFG2 */
#define ANA_AC_SRC_CFG2(g)                                                     \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g,              \
       regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 8, 0, 1, 4)

#define ANA_AC_SRC_CFG2_PORT_MASK2               BIT(0)
#define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\
 FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x)
#define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\
 FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x)

/* ANA_AC:PGID:PGID_CFG */
#define ANA_AC_PGID_CFG(g)                                                     \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g,             \
       regs->gcnt[GC_ANA_AC_PGID], 16, 0, 0, 1, 4)

/* SPARX5 ONLY */
/* ANA_AC:PGID:PGID_CFG1 */
#define ANA_AC_PGID_CFG1(g)                                                    \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g,             \
       regs->gcnt[GC_ANA_AC_PGID], 16, 4, 0, 1, 4)

/* SPARX5 ONLY */
/* ANA_AC:PGID:PGID_CFG2 */
#define ANA_AC_PGID_CFG2(g)                                                    \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g,             \
       regs->gcnt[GC_ANA_AC_PGID], 16, 8, 0, 1, 4)

#define ANA_AC_PGID_CFG2_PORT_MASK2              BIT(0)
#define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\
 FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x)
#define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\
 FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x)

/* ANA_AC:PGID:PGID_MISC_CFG */
#define ANA_AC_PGID_MISC_CFG(g)                                                \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g,             \
       regs->gcnt[GC_ANA_AC_PGID], 16, 12, 0, 1, 4)

#define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU         GENMASK(6, 4)
#define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\
 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
#define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\
 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)

#define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA      BIT(1)
#define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\
 FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
#define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\
 FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)

#define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA   BIT(0)
#define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\
 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
#define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\
 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)

/* ANA_AC:TSN_SF:TSN_SF */
#define ANA_AC_TSN_SF                                                          \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF], 0, 1, 4, 0,  \
       0, 1, 4)

#define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY BIT(9)
#define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\
 FIELD_PREP(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x)
#define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\
 FIELD_GET(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x)

#define ANA_AC_TSN_SF_PORT_NUM\
 GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_PORT_NUM] + 0 - 1, 0)
#define ANA_AC_TSN_SF_PORT_NUM_SET(x)\
 spx5_field_prep(ANA_AC_TSN_SF_PORT_NUM, x)
#define ANA_AC_TSN_SF_PORT_NUM_GET(x)\
 spx5_field_get(ANA_AC_TSN_SF_PORT_NUM, x)

/* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */
#define ANA_AC_TSN_SF_CFG(g)                                                   \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_CFG], g,       \
       regs->gcnt[GC_ANA_AC_TSN_SF_CFG], 4, 0, 0, 1, 4)

#define ANA_AC_TSN_SF_CFG_TSN_SGID\
 GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] + 16 - 1, 16)
#define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\
 spx5_field_prep(ANA_AC_TSN_SF_CFG_TSN_SGID, x)
#define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\
 spx5_field_get(ANA_AC_TSN_SF_CFG_TSN_SGID, x)

#define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU            GENMASK(15, 2)
#define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\
 FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x)
#define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_GET(x)\
 FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x)

#define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA     BIT(1)
#define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(x)\
 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x)
#define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_GET(x)\
 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x)

#define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE   BIT(0)
#define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(x)\
 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x)
#define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\
 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x)

/* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */
#define ANA_AC_TSN_SF_STATUS                                                   \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_STATUS], 0, 1, \
       16, 0, 0, 1, 4)

#define ANA_AC_TSN_SF_STATUS_FRM_LEN             GENMASK(25, 12)
#define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\
 FIELD_PREP(ANA_AC_TSN_SF_STATUS_FRM_LEN, x)
#define ANA_AC_TSN_SF_STATUS_FRM_LEN_GET(x)\
 FIELD_GET(ANA_AC_TSN_SF_STATUS_FRM_LEN, x)

#define ANA_AC_TSN_SF_STATUS_DLB_DROP            BIT(11)
#define ANA_AC_TSN_SF_STATUS_DLB_DROP_SET(x)\
 FIELD_PREP(ANA_AC_TSN_SF_STATUS_DLB_DROP, x)
#define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\
 FIELD_GET(ANA_AC_TSN_SF_STATUS_DLB_DROP, x)

#define ANA_AC_TSN_SF_STATUS_TSN_SFID\
 GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] + 1 - 1, 1)
#define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\
 spx5_field_prep(ANA_AC_TSN_SF_STATUS_TSN_SFID, x)
#define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\
 spx5_field_get(ANA_AC_TSN_SF_STATUS_TSN_SFID, x)

#define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD          BIT(0)
#define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\
 FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x)
#define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\
 FIELD_GET(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x)

/* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */
#define ANA_AC_SG_ACCESS_CTRL                                                  \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \
       0, 0, 1, 4)

#define ANA_AC_SG_ACCESS_CTRL_SGID\
 GENMASK(regs->fsize[FW_ANA_AC_SG_ACCESS_CTRL_SGID] + 0 - 1, 0)
#define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\
 spx5_field_prep(ANA_AC_SG_ACCESS_CTRL_SGID, x)
#define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\
 spx5_field_get(ANA_AC_SG_ACCESS_CTRL_SGID, x)

#define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE      BIT(28)
#define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\
 FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x)
#define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\
 FIELD_GET(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x)

/* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */
#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD                                      \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \
       8, 0, 1, 4)

#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS GENMASK(15, 0)
#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\
 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x)
#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_GET(x)\
 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x)

#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA BIT(31)
#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(x)\
 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x)
#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\
 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x)

/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */
#define ANA_AC_SG_CONFIG_REG_1                                                 \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
       48, 0, 1, 4)

/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */
#define ANA_AC_SG_CONFIG_REG_2                                                 \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
       52, 0, 1, 4)

/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */
#define ANA_AC_SG_CONFIG_REG_3                                                 \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
       56, 0, 1, 4)

#define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB GENMASK(15, 0)
#define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\
 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x)
#define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_GET(x)\
 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x)

#define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH       GENMASK(18, 16)
#define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(x)\
 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x)
#define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_GET(x)\
 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x)

#define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE       BIT(20)
#define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(x)\
 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x)
#define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_GET(x)\
 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x)

#define ANA_AC_SG_CONFIG_REG_3_INIT_IPS          GENMASK(24, 21)
#define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(x)\
 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x)
#define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_GET(x)\
 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x)

#define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE   BIT(25)
#define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(x)\
 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x)
#define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_GET(x)\
 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x)

#define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA    BIT(26)
#define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_SET(x)\
 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x)
#define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_GET(x)\
 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x)

#define ANA_AC_SG_CONFIG_REG_3_INVALID_RX        BIT(27)
#define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_SET(x)\
 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x)
#define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_GET(x)\
 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x)

#define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA BIT(28)
#define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_SET(x)\
 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x)
#define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_GET(x)\
 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x)

#define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED   BIT(29)
#define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_SET(x)\
 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x)
#define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\
 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x)

/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */
#define ANA_AC_SG_CONFIG_REG_4                                                 \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
       60, 0, 1, 4)

/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */
#define ANA_AC_SG_CONFIG_REG_5                                                 \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
       64, 0, 1, 4)

/* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */
#define ANA_AC_SG_GCL_GS_CONFIG(r)                                             \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
       0, r, 4, 4)

#define ANA_AC_SG_GCL_GS_CONFIG_IPS              GENMASK(3, 0)
#define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\
 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_IPS, x)
#define ANA_AC_SG_GCL_GS_CONFIG_IPS_GET(x)\
 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_IPS, x)

#define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE       BIT(4)
#define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(x)\
 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x)
#define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\
 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x)

/* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */
#define ANA_AC_SG_GCL_TI_CONFIG(r)                                             \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
       16, r, 4, 4)

/* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */
#define ANA_AC_SG_GCL_OCT_CONFIG(r)                                            \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
       32, r, 4, 4)

/* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */
#define ANA_AC_SG_STATUS_REG_1                                                 \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \
       0, 0, 1, 4)

/* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */
#define ANA_AC_SG_STATUS_REG_2                                                 \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \
       4, 0, 1, 4)

/* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */
#define ANA_AC_SG_STATUS_REG_3                                                 \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \
       8, 0, 1, 4)

#define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB GENMASK(15, 0)
#define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\
 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x)
#define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_GET(x)\
 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x)

#define ANA_AC_SG_STATUS_REG_3_GATE_STATE        BIT(16)
#define ANA_AC_SG_STATUS_REG_3_GATE_STATE_SET(x)\
 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x)
#define ANA_AC_SG_STATUS_REG_3_GATE_STATE_GET(x)\
 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x)

#define ANA_AC_SG_STATUS_REG_3_IPS               GENMASK(23, 20)
#define ANA_AC_SG_STATUS_REG_3_IPS_SET(x)\
 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_IPS, x)
#define ANA_AC_SG_STATUS_REG_3_IPS_GET(x)\
 FIELD_GET(ANA_AC_SG_STATUS_REG_3_IPS, x)

#define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING    BIT(24)
#define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_SET(x)\
 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x)
#define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_GET(x)\
 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x)

#define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX   GENMASK(27, 25)
#define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_SET(x)\
 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x)
#define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\
 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x)

/* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */
#define ANA_AC_SG_STATUS_REG_4                                                 \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \
       12, 0, 1, 4)

/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */
#define ANA_AC_PORT_SGE_CFG(r)                                                 \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\
       0, 1, 20, 0, r, 4, 4)

#define ANA_AC_PORT_SGE_CFG_MASK\
 GENMASK(regs->fsize[FW_ANA_AC_PORT_SGE_CFG_MASK] + 0 - 1, 0)
#define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\
 spx5_field_prep(ANA_AC_PORT_SGE_CFG_MASK, x)
#define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\
 spx5_field_get(ANA_AC_PORT_SGE_CFG_MASK, x)

/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */
#define ANA_AC_STAT_RESET                                                      \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\
       0, 1, 20, 16, 0, 1, 4)

#define ANA_AC_STAT_RESET_RESET                  BIT(0)
#define ANA_AC_STAT_RESET_RESET_SET(x)\
 FIELD_PREP(ANA_AC_STAT_RESET_RESET, x)
#define ANA_AC_STAT_RESET_RESET_GET(x)\
 FIELD_GET(ANA_AC_STAT_RESET_RESET, x)

/* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */
#define ANA_AC_PORT_STAT_CFG(g, r)                                             \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\
       regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 4, r, 4, 4)

#define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK       GENMASK(11, 4)
#define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\
 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
#define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\
 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)

#define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE    GENMASK(3, 1)
#define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\
 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
#define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\
 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)

#define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE        BIT(0)
#define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\
 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
#define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\
 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)

/* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */
#define ANA_AC_PORT_STAT_LSB_CNT(g, r)                                         \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\
       regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 20, r, 4, 4)

/* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */
#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r)                                  \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \
       0, 1, 24, 0, r, 2, 4)

#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE GENMASK(2, 0)
#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\
 FIELD_PREP(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x)
#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\
 FIELD_GET(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x)

/* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */
#define ANA_AC_ACL_STAT_GLOBAL_CFG(r)                                          \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \
       0, 1, 24, 8, r, 2, 4)

#define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE BIT(0)
#define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\
 FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x)
#define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\
 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x)

/* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */
#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r)                                   \
 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \
       0, 1, 24, 16, r, 2, 4)

#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK GENMASK(3, 0)
#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\
 FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x)
#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\
 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x)

/* ANA_ACL:COMMON:VCAP_S2_CFG */
#define ANA_ACL_VCAP_S2_CFG(r)                                                 \
 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
       0, r, regs->rcnt[RC_ANA_ACL_VCAP_S2_CFG], 4)

#define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA BIT(28)
#define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA     GENMASK(27, 26)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA GENMASK(25, 24)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA GENMASK(23, 22)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA GENMASK(21, 20)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA GENMASK(19, 18)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA GENMASK(17, 16)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA GENMASK(15, 14)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA GENMASK(13, 12)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA GENMASK(11, 10)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA     GENMASK(9, 8)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA GENMASK(7, 6)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA GENMASK(5, 4)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x)

#define ANA_ACL_VCAP_S2_CFG_SEC_ENA              GENMASK(3, 0)
#define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x)
#define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x)

/* ANA_ACL:COMMON:SWAP_IP_CTRL */
#define ANA_ACL_SWAP_IP_CTRL                                                   \
 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
       412, 0, 1, 4)

#define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL GENMASK(23, 18)
#define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\
 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x)
#define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x)\
 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x)

#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL GENMASK(17, 10)
#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x)\
 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x)
#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x)\
 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x)

#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL GENMASK(9, 2)
#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x)\
 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x)
#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x)\
 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x)

#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA BIT(1)
#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x)
#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x)\
 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x)

#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA BIT(0)
#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x)
#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\
 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x)

/* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */
#define ANA_ACL_VCAP_S2_RLEG_STAT(r)                                           \
 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
       424, r, 4, 4)

#define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK GENMASK(12, 6)
#define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x)
#define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x)

#define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK GENMASK(5, 0)
#define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x)
#define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x)

/* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */
#define ANA_ACL_VCAP_S2_FRAGMENT_CFG                                           \
 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
       440, 0, 1, 4)

#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN  GENMASK(9, 5)
#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x)
#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x)

#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS BIT(4)
#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x)
#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x)

#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES GENMASK(3, 0)
#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x)
#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x)

/* ANA_ACL:COMMON:OWN_UPSID */
#define ANA_ACL_OWN_UPSID(r)                                                   \
 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
       580, r, regs->rcnt[RC_ANA_ACL_OWN_UPSID], 4)

#define ANA_ACL_OWN_UPSID_OWN_UPSID              GENMASK(4, 0)
#define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\
 FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
#define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\
 FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x)

/* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */
#define ANA_ACL_VCAP_S2_KEY_SEL(g, r)                                          \
 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_KEY_SEL], g,        \
       regs->gcnt[GC_ANA_ACL_KEY_SEL], 16, 0, r, 4, 4)

#define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA      BIT(13)
#define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x)
#define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x)

#define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL BIT(12)
#define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x)
#define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x)

#define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL  GENMASK(11, 10)
#define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x)
#define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x)

#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL   GENMASK(9, 8)
#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x)
#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x)

#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL   GENMASK(7, 6)
#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x)
#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x)

#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL   GENMASK(5, 3)
#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x)
#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x)

#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL   GENMASK(2, 1)
#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x)
#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x)

#define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL      BIT(0)
#define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x)\
 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x)
#define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\
 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x)

/* ANA_ACL:CNT_A:CNT_A */
#define ANA_ACL_CNT_A(g)                                                       \
 __REG(TARGET_ANA_ACL, 0, 1, 0, g, regs->gcnt[GC_ANA_ACL_CNT_A], 4, 0,  \
       0, 1, 4)

/* ANA_ACL:CNT_B:CNT_B */
#define ANA_ACL_CNT_B(g)                                                       \
 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_CNT_B], g,          \
       regs->gcnt[GC_ANA_ACL_CNT_B], 4, 0, 0, 1, 4)

/* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */
#define ANA_ACL_SEC_LOOKUP_STICKY(r)                                           \
 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_STICKY], 0, 1, 16,  \
       0, r, 4, 4)

#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY BIT(17)
#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY BIT(16)
#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY BIT(15)
#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY BIT(14)
#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY BIT(13)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY BIT(12)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY BIT(11)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(10)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(9)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY BIT(8)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(6)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(5)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(4)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(3)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY BIT(2)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY BIT(1)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x)

#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\
 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\
 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)

/* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */
#define ANA_AC_POL_POL_UPD_INT_CFG                                             \
 __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_POL_ALL_CFG], \
       0, 1, 1160, 1148, 0, 1, 4)

#define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT   GENMASK(9, 0)
#define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\
 FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
#define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\
 FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)

/* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */
#define ANA_AC_POL_BDLB_DLB_CTRL                                               \
 __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_COMMON_BDLB], \
       0, 1, 8, 0, 0, 1, 4)

#define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19)
#define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\
 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
#define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\
 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)

#define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT   GENMASK(18, 4)
#define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\
 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
#define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\
 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)

#define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA        BIT(1)
#define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\
 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
#define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\
 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)

#define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA     BIT(0)
#define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\
 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
#define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\
 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)

/* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */
#define ANA_AC_POL_SLB_DLB_CTRL                                                \
 __REG(TARGET_ANA_AC_POL, 0, 1,                                         \
       regs->gaddr[GA_ANA_AC_POL_COMMON_BUM_SLB], 0, 1, 20, 0, 0, 1, 4)

#define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS  GENMASK(26, 19)
#define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\
 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
#define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\
 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)

#define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT    GENMASK(18, 4)
#define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\
 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
#define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\
 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)

#define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA         BIT(1)
#define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\
 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
#define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\
 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)

#define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA      BIT(0)
#define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\
 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
#define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\
 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)

/* ANA_AC_SDLB:LBGRP_TBL:XLB_START */
#define ANA_AC_SDLB_XLB_START(g)                                               \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
       g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 0, 0, 1, 4)

#define ANA_AC_SDLB_XLB_START_LBSET_START\
 GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_START_LBSET_START] + 0 - 1, 0)
#define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\
 spx5_field_prep(ANA_AC_SDLB_XLB_START_LBSET_START, x)
#define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\
 spx5_field_get(ANA_AC_SDLB_XLB_START_LBSET_START, x)

/* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */
#define ANA_AC_SDLB_PUP_INTERVAL(g)                                            \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
       g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 4, 0, 1, 4)

#define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL    GENMASK(19, 0)
#define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x)
#define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\
 FIELD_GET(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x)

/* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */
#define ANA_AC_SDLB_PUP_CTRL(g)                                                \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
       g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 8, 0, 1, 4)

#define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT           GENMASK(18, 0)
#define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x)
#define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_GET(x)\
 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x)

#define ANA_AC_SDLB_PUP_CTRL_PUP_ENA             BIT(24)
#define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x)
#define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\
 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x)

/* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */
#define ANA_AC_SDLB_LBGRP_MISC(g)                                              \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
       g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 12, 0, 1, 4)

#define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT\
 GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] + 8 - 1, 8)
#define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\
 spx5_field_prep(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x)
#define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\
 spx5_field_get(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x)

/* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */
#define ANA_AC_SDLB_FRM_RATE_TOKENS(g)                                         \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
       g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 16, 0, 1, 4)

#define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS GENMASK(12, 0)
#define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x)
#define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\
 FIELD_GET(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x)

/* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */
#define ANA_AC_SDLB_LBGRP_STATE_TBL(g)                                         \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
       g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 20, 0, 1, 4)

#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING  BIT(0)
#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x)
#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_GET(x)\
 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x)

#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK BIT(1)
#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x)
#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\
 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x)

#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT\
 GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] + 16 - 1, 16)
#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\
 spx5_field_prep(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x)
#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\
 spx5_field_get(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x)

/* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */
#define ANA_AC_SDLB_PUP_TOKENS(g, r)                                           \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
       regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 0, r, 2, 4)

#define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS        GENMASK(12, 0)
#define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x)
#define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\
 FIELD_GET(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x)

/* ANA_AC_SDLB:LBSET_TBL:THRES */
#define ANA_AC_SDLB_THRES(g, r)                                                \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
       regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 8, r, 2, 4)

#define ANA_AC_SDLB_THRES_THRES                  GENMASK(9, 0)
#define ANA_AC_SDLB_THRES_THRES_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_THRES_THRES, x)
#define ANA_AC_SDLB_THRES_THRES_GET(x)\
 FIELD_GET(ANA_AC_SDLB_THRES_THRES, x)

#define ANA_AC_SDLB_THRES_THRES_HYS              GENMASK(25, 16)
#define ANA_AC_SDLB_THRES_THRES_HYS_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_THRES_THRES_HYS, x)
#define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\
 FIELD_GET(ANA_AC_SDLB_THRES_THRES_HYS, x)

/* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */
#define ANA_AC_SDLB_XLB_NEXT(g)                                                \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
       regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 16, 0, 1, 4)

#define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT\
 GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] + 0 - 1, 0)
#define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\
 spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x)
#define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\
 spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x)

#define ANA_AC_SDLB_XLB_NEXT_LBGRP\
 GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] + 24 - 1, 24)
#define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\
 spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBGRP, x)
#define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\
 spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBGRP, x)

/* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */
#define ANA_AC_SDLB_INH_CTRL(g, r)                                             \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
       regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 20, r, 2, 4)

#define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX      GENMASK(12, 0)
#define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x)
#define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_GET(x)\
 FIELD_GET(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x)

#define ANA_AC_SDLB_INH_CTRL_INH_MODE            GENMASK(21, 20)
#define ANA_AC_SDLB_INH_CTRL_INH_MODE_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_MODE, x)
#define ANA_AC_SDLB_INH_CTRL_INH_MODE_GET(x)\
 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_MODE, x)

#define ANA_AC_SDLB_INH_CTRL_INH_LB              BIT(24)
#define ANA_AC_SDLB_INH_CTRL_INH_LB_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_LB, x)
#define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\
 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_LB, x)

/* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */
#define ANA_AC_SDLB_INH_LBSET_ADDR(g)                                          \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
       regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 28, 0, 1, 4)

#define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR\
 GENMASK(regs->fsize[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] + 0 - 1, 0)
#define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\
 spx5_field_prep(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x)
#define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\
 spx5_field_get(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x)

/* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */
#define ANA_AC_SDLB_DLB_MISC(g)                                                \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
       regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 32, 0, 1, 4)

#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA    BIT(0)
#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x)
#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_GET(x)\
 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x)

#define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA BIT(6)
#define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x)
#define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_GET(x)\
 FIELD_GET(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x)

#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ         GENMASK(14, 8)
#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x)
#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\
 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x)

/* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */
#define ANA_AC_SDLB_DLB_CFG(g)                                                 \
 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
       regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 36, 0, 1, 4)

#define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA   BIT(11)
#define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x)
#define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_GET(x)\
 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x)

#define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL        GENMASK(10, 9)
#define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x)
#define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_GET(x)\
 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x)

#define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS         BIT(8)
#define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x)
#define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_GET(x)\
 FIELD_GET(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x)

#define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS       BIT(7)
#define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x)
#define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_GET(x)\
 FIELD_GET(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x)

#define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL      GENMASK(6, 5)
#define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x)
#define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_GET(x)\
 FIELD_GET(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x)

#define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL       GENMASK(4, 3)
#define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x)
#define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_GET(x)\
 FIELD_GET(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x)

#define ANA_AC_SDLB_DLB_CFG_DLB_MODE             BIT(2)
#define ANA_AC_SDLB_DLB_CFG_DLB_MODE_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x)
#define ANA_AC_SDLB_DLB_CFG_DLB_MODE_GET(x)\
 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x)

#define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK    GENMASK(1, 0)
#define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_SET(x)\
 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x)
#define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\
 FIELD_GET(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x)

/* ANA_CL:PORT:FILTER_CTRL */
#define ANA_CL_FILTER_CTRL(g)                                                  \
 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
       regs->gcnt[GC_ANA_CL_PORT], 512, 4, 0, 1, 4)

#define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS    BIT(2)
#define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\
 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
#define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\
 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)

#define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS   BIT(1)
#define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\
 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
#define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\
 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)

#define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA  BIT(0)
#define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\
 FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
#define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\
 FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)

/* ANA_CL:PORT:VLAN_FILTER_CTRL */
#define ANA_CL_VLAN_FILTER_CTRL(g, r)                                          \
 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
       regs->gcnt[GC_ANA_CL_PORT], 512, 8, r, 3, 4)

#define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10)
#define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
#define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\
 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)

#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS    BIT(9)
#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\
 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)

#define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS         BIT(8)
#define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
#define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\
 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)

#define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS    BIT(7)
#define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
#define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\
 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)

#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS BIT(6)
#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\
 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)

#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS BIT(5)
#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\
 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)

#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS BIT(4)
#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\
 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)

#define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS         BIT(3)
#define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
#define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\
 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)

#define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS   BIT(2)
#define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
#define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\
 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)

#define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS   BIT(1)
#define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
#define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\
 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)

#define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS   BIT(0)
#define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
#define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\
 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)

/* ANA_CL:PORT:ETAG_FILTER_CTRL */
#define ANA_CL_ETAG_FILTER_CTRL(g)                                             \
 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
       regs->gcnt[GC_ANA_CL_PORT], 512, 20, 0, 1, 4)

#define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1)
#define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\
 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
#define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\
 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)

#define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS         BIT(0)
#define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\
 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
#define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\
 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)

/* ANA_CL:PORT:VLAN_CTRL */
#define ANA_CL_VLAN_CTRL(g)                                                    \
 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
       regs->gcnt[GC_ANA_CL_PORT], 512, 32, 0, 1, 4)

#define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26)
#define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
#define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\
 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)

#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP    GENMASK(25, 23)
#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\
 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)

#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI    BIT(22)
#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\
 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)

#define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA  BIT(21)
#define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
#define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\
 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)

#define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL            BIT(20)
#define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
#define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\
 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)

#define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA          BIT(19)
#define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
#define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\
 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)

#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT            GENMASK(18, 17)
#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\
 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)

#define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE           BIT(16)
#define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
#define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\
 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)

#define ANA_CL_VLAN_CTRL_PORT_PCP                GENMASK(15, 13)
#define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x)
#define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\
 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x)

#define ANA_CL_VLAN_CTRL_PORT_DEI                BIT(12)
#define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x)
#define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\
 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x)

#define ANA_CL_VLAN_CTRL_PORT_VID                GENMASK(11, 0)
#define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x)
#define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\
 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x)

/* ANA_CL:PORT:VLAN_CTRL_2 */
#define ANA_CL_VLAN_CTRL_2(g)                                                  \
 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
       regs->gcnt[GC_ANA_CL_PORT], 512, 36, 0, 1, 4)

#define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT         GENMASK(1, 0)
#define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\
 FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
#define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\
 FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)

/* ANA_CL:PORT:PCP_DEI_MAP_CFG */
--> --------------------

--> maximum size reached

--> --------------------