// SPDX-License-Identifier: GPL-2.0-or-later /* * Low-level parallel-support for PC-style hardware integrated in the * LASI-Controller (on GSC-Bus) for HP-PARISC Workstations * * (C) 1999-2001 by Helge Deller <deller@gmx.de> * * based on parport_pc.c by * Grant Guenther <grant@torque.net> * Phil Blundell <philb@gnu.org> * Tim Waugh <tim@cyberelk.demon.co.uk> * Jose Renau <renau@acm.org> * David Campbell * Andrea Arcangeli
*/
MODULE_AUTHOR("Helge Deller ");
MODULE_DESCRIPTION("HP-PARISC PC-style parallel port driver");
MODULE_LICENSE("GPL");
/* * Clear TIMEOUT BIT in EPP MODE * * This is also used in SPP detection.
*/ staticint clear_epp_timeout(struct parport *pb)
{ unsignedchar r;
if (!(parport_gsc_read_status(pb) & 0x01)) return 1;
/* To clear timeout some chips require double read */
parport_gsc_read_status(pb);
r = parport_gsc_read_status(pb);
parport_writeb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
parport_writeb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
r = parport_gsc_read_status(pb);
return !(r & 0x01);
}
/* * Access functions. * * Most of these aren't static because they may be used by the * parport_xxx_yyy macros. extern __inline__ versions of several * of these are in parport_gsc.h.
*/
/* * Checks for port existence, all ports support SPP MODE
*/ staticint parport_SPP_supported(struct parport *pb)
{ unsignedchar r, w;
/* * first clear an eventually pending EPP timeout * I (sailer@ife.ee.ethz.ch) have an SMSC chipset * that does not even respond to SPP cycles if an EPP * timeout is pending
*/
clear_epp_timeout(pb);
/* Do a simple read-write test to make sure the port exists. */
w = 0xc;
parport_writeb (w, CONTROL (pb));
/* Is there a control register that we can read from? Some * ports don't allow reads, so read_control just returns a * software copy. Some ports _do_ allow reads, so bypass the * software copy here. In addition, some bits aren't
* writable. */
r = parport_readb (CONTROL (pb)); if ((r & 0xf) == w) {
w = 0xe;
parport_writeb (w, CONTROL (pb));
r = parport_readb (CONTROL (pb));
parport_writeb (0xc, CONTROL (pb)); if ((r & 0xf) == w) return PARPORT_MODE_PCSPP;
}
/* Try the data register. The data lines aren't tri-stated at
* this stage, so we expect back what we wrote. */
w = 0xaa;
parport_gsc_write_data (pb, w);
r = parport_gsc_read_data (pb); if (r == w) {
w = 0x55;
parport_gsc_write_data (pb, w);
r = parport_gsc_read_data (pb); if (r == w) return PARPORT_MODE_PCSPP;
}
return 0;
}
/* Detect PS/2 support. * * Bit 5 (0x20) sets the PS/2 data direction; setting this high * allows us to read data from the data lines. In theory we would get back * 0xff but any peripheral attached to the port may drag some or all of the * lines down to zero. So if we get back anything that isn't the contents * of the data register we deem PS/2 support to be present. * * Some SPP ports have "half PS/2" ability - you can't turn off the line * drivers, but an external peripheral with sufficiently beefy drivers of * its own can overpower them and assert its own levels onto the bus, from * where they can then be read back as normal. Ports with this property * and the right type of device attached are likely to fail the SPP test, * (as they will appear to have stuck bits) and so the fact that they might * be misdetected here is rather academic.
*/
staticint parport_PS2_supported(struct parport *pb)
{ int ok = 0;
clear_epp_timeout(pb);
/* try to tri-state the buffer */
parport_gsc_data_reverse (pb);
parport_gsc_write_data(pb, 0x55); if (parport_gsc_read_data(pb) != 0x55) ok++;
parport_gsc_write_data(pb, 0xaa); if (parport_gsc_read_data(pb) != 0xaa) ok++;
/* Now that we've told the sharing engine about the port, and found out its characteristics, let the high-level drivers
know about it. */
parport_announce_port (p);
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