// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) // Copyright(c) 2015-17 Intel Corporation.
/* * MIPI Discovery And Configuration (DisCo) Specification for SoundWire * specifies properties to be implemented for SoundWire Masters and Slaves. * The DisCo spec doesn't mandate these properties. However, SDW bus cannot * work without knowing these values. * * The helper functions read the Master and Slave properties. Implementers * of Master or Slave drivers can use any of the below three mechanisms: * a) Use these APIs here as .read_prop() callback for Master and Slave * b) Implement own methods and set those as .read_prop(), but invoke * APIs in this file for generic read and override the values with * platform specific data * c) Implement ones own methods which do not use anything provided * here
*/
ret = fwnode_property_read_u32_array(link, "mipi-sdw-clock-frequencies-supported",
prop->clk_freq, prop->num_clk_freq); if (ret < 0) return ret;
}
/* * Check the frequencies supported. If FW doesn't provide max * freq, then populate here by checking values.
*/ if (!prop->max_clk_freq && prop->clk_freq) {
prop->max_clk_freq = prop->clk_freq[0]; for (i = 1; i < prop->num_clk_freq; i++) { if (prop->clk_freq[i] > prop->max_clk_freq)
prop->max_clk_freq = prop->clk_freq[i];
}
}
ret = fwnode_property_read_u32_array(node, "mipi-sdw-lane-list",
dpn[i].lane_list, dpn[i].num_lanes); if (ret < 0) return ret;
}
fwnode_handle_put(node);
i++;
}
return 0;
}
/* * In MIPI DisCo spec for SoundWire, lane mapping for a slave device is done with * mipi-sdw-lane-x-mapping properties, where x is 1..7, and the values for those * properties are mipi-sdw-manager-lane-x or mipi-sdw-peripheral-link-y, where x * is an integer between 1 to 7 if the lane is connected to a manager lane, y is a * character between A to E if the lane is connected to another peripheral lane.
*/ int sdw_slave_read_lane_mapping(struct sdw_slave *slave)
{ struct sdw_slave_prop *prop = &slave->prop; struct device *dev = &slave->dev; char prop_name[30]; constchar *prop_val;
size_t len; int ret, i;
u8 lane;
for (i = 0; i < SDW_MAX_LANES; i++) {
snprintf(prop_name, sizeof(prop_name), "mipi-sdw-lane-%d-mapping", i);
ret = device_property_read_string(dev, prop_name, &prop_val); if (ret) continue;
len = strlen(prop_val); if (len < 1) return -EINVAL;
/* The last character is enough to identify the connection */
ret = kstrtou8(&prop_val[len - 1], 10, &lane); if (ret) return ret; if (in_range(lane, 1, SDW_MAX_LANES - 1))
prop->lane_maps[i] = lane;
} return 0;
}
EXPORT_SYMBOL(sdw_slave_read_lane_mapping);
/* * Read dp0 properties - we don't rely on the 'mipi-sdw-dp-0-supported' * property since the 'mipi-sdw-dp0-subproperties' property is logically * equivalent.
*/
port = device_get_named_child_node(dev, "mipi-sdw-dp-0-subproperties"); if (!port) {
dev_dbg(dev, "DP0 node not found!!\n");
} else {
prop->dp0_prop = devm_kzalloc(&slave->dev, sizeof(*prop->dp0_prop),
GFP_KERNEL); if (!prop->dp0_prop) {
fwnode_handle_put(port); return -ENOMEM;
}
sdw_slave_read_dp0(slave, port, prop->dp0_prop);
fwnode_handle_put(port);
}
/* * Based on each DPn port, get source and sink dpn properties. * Also, some ports can operate as both source or sink.
*/
/* Allocate memory for set bits in port lists */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, sizeof(*prop->src_dpn_prop),
GFP_KERNEL); if (!prop->src_dpn_prop) return -ENOMEM;
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