// SPDX-License-Identifier: GPL-2.0-only /* * PowerMac G5 SMU driver * * Copyright 2004 J. Mayer <l_indien@magic.fr> * Copyright 2005 Benjamin Herrenschmidt, IBM Corp.
*/
/* * TODO: * - maybe add timeout to commands ? * - blocking version of time functions * - polling version of i2c commands (including timer that works with * interrupts off) * - maybe avoid some data copies with i2c by directly using the smu cmd * buffer and a lower level internal interface * - understand SMU -> CPU events and implement reception of them via * the userland interface
*/
/* * I don't think there will ever be more than one SMU, so * for now, just hard code that
*/ static DEFINE_MUTEX(smu_mutex); staticstruct smu_device *smu; static DEFINE_MUTEX(smu_part_access); staticint smu_irq_inited; staticunsignedlong smu_cmdbuf_abs;
/* Fill the SMU command buffer */
smu->cmd_buf->cmd = cmd->cmd;
smu->cmd_buf->length = cmd->data_len;
memcpy(smu->cmd_buf->data, cmd->data_buf, cmd->data_len);
/* Flush command and data to RAM */
faddr = (unsignedlong)smu->cmd_buf;
fend = faddr + smu->cmd_buf->length + 2;
flush_dcache_range(faddr, fend);
/* We also disable NAP mode for the duration of the command * on U3 based machines. * This is slightly racy as it can be written back to 1 by a sysctl * but that never happens in practice. There seem to be an issue with * U3 based machines such as the iMac G5 where napping for the * whole duration of the command prevents the SMU from fetching it * from memory. This might be related to the strange i2c based * mechanism the SMU uses to access memory.
*/ if (smu->broken_nap)
powersave_nap = 0;
/* This isn't exactly a DMA mapping here, I suspect * the SMU is actually communicating with us via i2c to the * northbridge or the CPU to access RAM.
*/
writel(smu->cmd_buf_abs, smu->db_buf);
/* Ring the SMU doorbell */
pmac_do_feature_call(PMAC_FTR_WRITE_GPIO, NULL, smu->doorbell, 4);
}
if (rc == 0) { unsignedlong faddr; int reply_len;
u8 ack;
/* CPU might have brought back the cache line, so we need * to flush again before peeking at the SMU response. We * flush the entire buffer for now as we haven't read the * reply length (it's only 2 cache lines anyway)
*/
faddr = (unsignedlong)smu->cmd_buf;
flush_dcache_range(faddr, faddr + 256);
/* Now complete the command. Write status last in order as we lost * ownership of the command structure as soon as it's no longer -1
*/
done = cmd->done;
misc = cmd->misc;
mb();
cmd->status = rc;
/* Re-enable NAP mode */ if (smu->broken_nap)
powersave_nap = 1;
bail: /* Start next command if any */
smu_start_cmd();
spin_unlock_irqrestore(&smu->lock, flags);
/* Call command completion handler if any */ if (done)
done(cmd, misc);
/* It's an edge interrupt, nothing to do */ return IRQ_HANDLED;
}
static irqreturn_t smu_msg_intr(int irq, void *arg)
{ /* I don't quite know what to do with this one, we seem to never * receive it, so I suspect we have to arm it someway in the SMU * to start getting events that way.
*/
printk(KERN_INFO "SMU: message interrupt !\n");
/* It's an edge interrupt, nothing to do */ return IRQ_HANDLED;
}
/* * Queued command management. *
*/
int smu_queue_cmd(struct smu_cmd *cmd)
{ unsignedlong flags;
if (smu == NULL) return -ENODEV; if (cmd->data_len > SMU_MAX_DATA ||
cmd->reply_len > SMU_MAX_DATA) return -EINVAL;
/* * SMU based G5s need some memory below 2Gb. Thankfully this is * called at a time where memblock is still available.
*/
smu_cmdbuf_abs = memblock_phys_alloc_range(4096, 4096, 0, 0x80000000UL); if (smu_cmdbuf_abs == 0) {
printk(KERN_ERR "SMU: Command buffer allocation failed !\n");
ret = -EINVAL; goto fail_np;
}
/* smu_cmdbuf_abs is in the low 2G of RAM, can be converted to a * 32 bits value safely
*/
smu->cmd_buf_abs = (u32)smu_cmdbuf_abs;
smu->cmd_buf = __va(smu_cmdbuf_abs);
/* Current setup has one doorbell GPIO that does both doorbell * and ack. GPIOs are at 0x50, best would be to find that out * in the device-tree though.
*/
smu->doorbell = data; if (smu->doorbell < 0x50)
smu->doorbell += 0x50;
/* Now look for the smu-interrupt GPIO */ do {
smu->msg_node = of_find_node_by_name(NULL, "smu-interrupt"); if (smu->msg_node == NULL) break; if (of_property_read_reg(smu->msg_node, 0, &data, NULL)) {
of_node_put(smu->msg_node);
smu->msg_node = NULL; break;
}
smu->msg = data; if (smu->msg < 0x50)
smu->msg += 0x50;
} while(0);
/* Doorbell buffer is currently hard-coded, I didn't find a proper * device-tree entry giving the address. Best would probably to use * an offset for K2 base though, but let's do it that way for now.
*/
smu->db_buf = ioremap(0x8000860c, 0x1000); if (smu->db_buf == NULL) {
printk(KERN_ERR "SMU: Can't map doorbell buffer pointer !\n");
ret = -ENXIO; goto fail_msg_node;
}
/* U3 has an issue with NAP mode when issuing SMU commands */
smu->broken_nap = pmac_get_uninorth_variant() < 4; if (smu->broken_nap)
printk(KERN_INFO "SMU: using NAP mode workaround\n");
staticint smu_late_init(void)
{ if (!smu) return 0;
timer_setup(&smu->i2c_timer, smu_i2c_retry, 0);
if (smu->db_node) {
smu->db_irq = irq_of_parse_and_map(smu->db_node, 0); if (!smu->db_irq)
printk(KERN_ERR "smu: failed to map irq for node %pOF\n",
smu->db_node);
} if (smu->msg_node) {
smu->msg_irq = irq_of_parse_and_map(smu->msg_node, 0); if (!smu->msg_irq)
printk(KERN_ERR "smu: failed to map irq for node %pOF\n",
smu->msg_node);
}
smu_irq_inited = 1; return 0;
} /* This has to be before arch_initcall as the low i2c stuff relies on the * above having been done before we reach arch_initcalls
*/
core_initcall(smu_late_init);
/* * Ok, we are matched, now expose all i2c busses. We have to defer * that unfortunately or it would deadlock inside the device model
*/
schedule_work(&smu_expose_childs_work);
staticint __init smu_init_sysfs(void)
{ /* * For now, we don't power manage machines with an SMU chip, * I'm a bit too far from figuring out how that works with those * new chipsets, but that will come back and bite us
*/
platform_driver_register(&smu_of_platform_driver); return 0;
}
/* Check for read case */ if (!fail && cmd->read) { if (cmd->pdata[0] < 1)
fail = 1; else
memcpy(cmd->info.data, &cmd->pdata[1],
cmd->info.datalen);
}
DPRINTK("SMU: completing, success: %d\n", !fail);
/* Update status and mark no pending i2c command with lock * held so nobody comes in while we dequeue an eventual * pending next i2c command
*/
spin_lock_irqsave(&smu->lock, flags);
smu->cmd_i2c_cur = NULL;
wmb();
cmd->status = fail ? -EIO : 0;
/* Is there another i2c command waiting ? */ if (!list_empty(&smu->cmd_i2c_list)) { struct smu_i2c_cmd *newcmd;
/* Fetch it, new current, remove from list */
newcmd = list_entry(smu->cmd_i2c_list.next, struct smu_i2c_cmd, link);
smu->cmd_i2c_cur = newcmd;
list_del(&cmd->link);
/* Queue with low level smu */
list_add_tail(&cmd->scmd.link, &smu->cmd_list); if (smu->cmd_cur == NULL)
smu_start_cmd();
}
spin_unlock_irqrestore(&smu->lock, flags);
/* Call command completion handler if any */ if (done)
done(cmd, misc);
/* Check transfer type, sanitize some "info" fields * based on transfer type and do more checking
*/
cmd->info.caddr = cmd->info.devaddr;
cmd->read = cmd->info.devaddr & 0x01; switch(cmd->info.type) { case SMU_I2C_TRANSFER_SIMPLE:
cmd->info.sublen = 0;
memset(cmd->info.subaddr, 0, sizeof(cmd->info.subaddr)); break; case SMU_I2C_TRANSFER_COMBINED:
cmd->info.devaddr &= 0xfe;
fallthrough; case SMU_I2C_TRANSFER_STDSUB: if (cmd->info.sublen > 3) return -EINVAL; break; default: return -EINVAL;
}
/* Finish setting up command based on transfer direction
*/ if (cmd->read) { if (cmd->info.datalen > SMU_I2C_READ_MAX) return -EINVAL;
memset(cmd->info.data, 0xff, cmd->info.datalen);
cmd->scmd.data_len = 9;
} else { if (cmd->info.datalen > SMU_I2C_WRITE_MAX) return -EINVAL;
cmd->scmd.data_len = 9 + cmd->info.datalen;
}
/* Enqueue command in i2c list, and if empty, enqueue also in * main command list
*/
spin_lock_irqsave(&smu->lock, flags); if (smu->cmd_i2c_cur == NULL) {
smu->cmd_i2c_cur = cmd;
list_add_tail(&cmd->scmd.link, &smu->cmd_list); if (smu->cmd_cur == NULL)
smu_start_cmd();
} else
list_add_tail(&cmd->link, &smu->cmd_i2c_list);
spin_unlock_irqrestore(&smu->lock, flags);
/* First query the partition info */
DPRINTK("SMU: Query partition infos ... (irq=%d)\n", smu->db_irq);
smu_queue_simple(&cmd, SMU_CMD_PARTITION_COMMAND, 2,
smu_done_complete, &comp,
SMU_CMD_PARTITION_LATEST, id);
wait_for_completion(&comp);
DPRINTK("SMU: done, status: %d, reply_len: %d\n",
cmd.cmd.status, cmd.cmd.reply_len);
/* Partition doesn't exist (or other error) */ if (cmd.cmd.status != 0 || cmd.cmd.reply_len != 6) return NULL;
/* Fetch address and length from reply */
addr = *((u16 *)cmd.buffer);
len = cmd.buffer[3] << 2; /* Calucluate total length to allocate, including the 17 bytes * for "sdb-partition-XX" that we append at the end of the buffer
*/
tlen = sizeof(struct property) + len + 18;
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