Quelle  cix,sky1.h   Sprache: C

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright 2024-2025 Cix Technology Group Co., Ltd.
 */

#ifndef _DT_BINDINGS_CLK_CIX_SKY1_H
#define _DT_BINDINGS_CLK_CIX_SKY1_H

#define CLK_TREE_CPU_GICxCLK   0
#define CLK_TREE_CPU_PPUCLK   1
#define CLK_TREE_CPU_PERIPHCLK   2
#define CLK_TREE_DSU_CLK   3
#define CLK_TREE_DSU_PCLK   4
#define CLK_TREE_CPU_CLK_BC0   5
#define CLK_TREE_CPU_CLK_BC1   6
#define CLK_TREE_CPU_CLK_BC2   7
#define CLK_TREE_CPU_CLK_BC3   8
#define CLK_TREE_CPU_CLK_MC0   9
#define CLK_TREE_CPU_CLK_MC1   10
#define CLK_TREE_CPU_CLK_MC2   11
#define CLK_TREE_CPU_CLK_MC3   12
#define CLK_TREE_CPU_CLK_LC0   13
#define CLK_TREE_CPU_CLK_LC1   14
#define CLK_TREE_CPU_CLK_LC2   15
#define CLK_TREE_CPU_CLK_LC3   16
#define CLK_TREE_CSI_CTRL0_PCLK   17
#define CLK_TREE_CSI_CTRL1_PCLK   18
#define CLK_TREE_CSI_CTRL2_PCLK   19
#define CLK_TREE_CSI_CTRL3_PCLK   20
#define CLK_TREE_CSI_DMA0_PCLK   21
#define CLK_TREE_CSI_DMA1_PCLK   22
#define CLK_TREE_CSI_DMA2_PCLK   23
#define CLK_TREE_CSI_DMA3_PCLK   24
#define CLK_TREE_CSI_PHY0_PSM   25
#define CLK_TREE_CSI_PHY1_PSM   26
#define CLK_TREE_CSI_PHY0_APBCLK  27
#define CLK_TREE_CSI_PHY1_APBCLK  28
#define CLK_TREE_FCH_APB_CLK   29
#define CLK_TREE_GPU_CLK_400M   30
#define CLK_TREE_GPU_CLK_CORE   31
#define CLK_TREE_GPU_CLK_STACKS   32
#define CLK_TREE_DP0_PIXEL0   33
#define CLK_TREE_DP0_PIXEL1   34
#define CLK_TREE_DP1_PIXEL0   35
#define CLK_TREE_DP1_PIXEL1   36
#define CLK_TREE_DP2_PIXEL0   37
#define CLK_TREE_DP2_PIXEL1   38
#define CLK_TREE_DP3_PIXEL0   39
#define CLK_TREE_DP3_PIXEL1   40
#define CLK_TREE_DP4_PIXEL0   41
#define CLK_TREE_DP4_PIXEL1   42
#define CLK_TREE_DPU_CLK   43
#define CLK_TREE_DPU0_ACLK   44
#define CLK_TREE_DPU1_ACLK   45
#define CLK_TREE_DPU2_ACLK   46
#define CLK_TREE_DPU3_ACLK   47
#define CLK_TREE_DPU4_ACLK   48
#define CLK_TREE_DPC0_VIDCLK0   49
#define CLK_TREE_DPC0_VIDCLK1   50
#define CLK_TREE_DPC1_VIDCLK0   51
#define CLK_TREE_DPC1_VIDCLK1   52
#define CLK_TREE_DPC2_VIDCLK0   53
#define CLK_TREE_DPC2_VIDCLK1   54
#define CLK_TREE_DPC3_VIDCLK0   55
#define CLK_TREE_DPC3_VIDCLK1   56
#define CLK_TREE_DPC4_VIDCLK0   57
#define CLK_TREE_DPC4_VIDCLK1   58
#define CLK_TREE_DPC0_APBCLK   59
#define CLK_TREE_DPC1_APBCLK   60
#define CLK_TREE_DPC2_APBCLK   61
#define CLK_TREE_DPC3_APBCLK   62
#define CLK_TREE_DPC4_APBCLK   63
#define CLK_TREE_NPU_MEMCLK   64
#define CLK_TREE_NPU_SYSCLK   65
#define CLK_TREE_NPU_DBGCLK   66
#define CLK_TREE_VPU_APBCLK   67
#define CLK_TREE_ISP_ACLK   68
#define CLK_TREE_ISP_SCLK   69
#define CLK_TREE_AUDIO_CLK4   70
#define CLK_TREE_AUDIO_CLK5   71
#define CLK_TREE_CAMERA_MCLK0   72
#define CLK_TREE_CAMERA_MCLK1   73
#define CLK_TREE_CAMERA_MCLK2   74
#define CLK_TREE_CAMERA_MCLK3   75
#define CLK_TREE_AUDIO_CLK0   76
#define CLK_TREE_AUDIO_CLK1   77
#define CLK_TREE_AUDIO_CLK2   78
#define CLK_TREE_AUDIO_CLK3   79
#define CLK_TREE_MM_NI700_CLK   80
#define CLK_TREE_SYS_NI700_CLK   81
#define CLK_TREE_GMAC0_ACLK   82
#define CLK_TREE_GMAC1_ACLK   83
#define CLK_TREE_GMAC0_DIV_ACLK   84
#define CLK_TREE_GMAC0_DIV_TXCLK  85
#define CLK_TREE_GMAC0_RGMII0_TXCLK  86
#define CLK_TREE_GMAC1_DIV_ACLK   87
#define CLK_TREE_GMAC1_DIV_TXCLK  88
#define CLK_TREE_GMAC1_RGMII0_TXCLK  89
#define CLK_TREE_GMAC0_PCLK   90
#define CLK_TREE_GMAC1_PCLK   91
#define CLK_TREE_USB2_0_AXI_GATE  92
#define CLK_TREE_USB2_0_APB_GATE  93
#define CLK_TREE_USB2_1_AXI_GATE  94
#define CLK_TREE_USB2_1_APB_GATE  95
#define CLK_TREE_USB2_2_AXI_GATE  96
#define CLK_TREE_USB2_2_APB_GATE  97
#define CLK_TREE_USB2_3_AXI_GATE  98
#define CLK_TREE_USB2_3_APB_GATE  99
#define CLK_TREE_USB2_0_PHY_GATE  100
#define CLK_TREE_USB2_1_PHY_GATE  101
#define CLK_TREE_USB2_2_PHY_GATE  102
#define CLK_TREE_USB2_3_PHY_GATE  103
#define CLK_TREE_USB3C_DRD_AXI_GATE  104
#define CLK_TREE_USB3C_DRD_APB_GATE  105
#define CLK_TREE_USB3C_DRD_PHY2_GATE  106
#define CLK_TREE_USB3C_DRD_PHY3_GATE  107
#define CLK_TREE_USB3C_0_AXI_GATE  108
#define CLK_TREE_USB3C_0_APB_GATE  109
#define CLK_TREE_USB3C_0_PHY2_GATE  110
#define CLK_TREE_USB3C_0_PHY3_GATE  111
#define CLK_TREE_USB3C_1_AXI_GATE  112
#define CLK_TREE_USB3C_1_APB_GATE  113
#define CLK_TREE_USB3C_1_PHY2_GATE  114
#define CLK_TREE_USB3C_1_PHY3_GATE  115
#define CLK_TREE_USB3C_2_AXI_GATE  116
#define CLK_TREE_USB3C_2_APB_GATE  117
#define CLK_TREE_USB3C_2_PHY2_GATE  118
#define CLK_TREE_USB3C_2_PHY3_GATE  119
#define CLK_TREE_USB3A_0_AXI_GATE  120
#define CLK_TREE_USB3A_0_APB_GATE  121
#define CLK_TREE_USB3A_0_PHY2_GATE  122
#define CLK_TREE_USB3A_1_AXI_GATE  123
#define CLK_TREE_USB3A_1_APB_GATE  124
#define CLK_TREE_USB3A_1_PHY2_GATE  125
#define CLK_TREE_USB3A_PHY3_GATE  126
#define CLK_TREE_USB2_0_CLK_SOF   127
#define CLK_TREE_USB2_1_CLK_SOF   128
#define CLK_TREE_USB2_2_CLK_SOF   129
#define CLK_TREE_USB2_3_CLK_SOF   130
#define CLK_TREE_USB3C_DRD_CLK_SOF  131
#define CLK_TREE_USB3C_H0_CLK_SOF  132
#define CLK_TREE_USB3C_H1_CLK_SOF  133
#define CLK_TREE_USB3C_H2_CLK_SOF  134
#define CLK_TREE_USB3A_H0_CLK_SOF  135
#define CLK_TREE_USB3A_H1_CLK_SOF  136
#define CLK_TREE_USB2_0_CLK_LPM   137
#define CLK_TREE_USB2_1_CLK_LPM   138
#define CLK_TREE_USB2_2_CLK_LPM   139
#define CLK_TREE_USB2_3_CLK_LPM   140
#define CLK_TREE_USB3C_DRD_CLK_LPM  141
#define CLK_TREE_USB3C_H0_CLK_LPM  142
#define CLK_TREE_USB3C_H1_CLK_LPM  143
#define CLK_TREE_USB3C_H2_CLK_LPM  144
#define CLK_TREE_USB3A_H0_CLK_LPM  145
#define CLK_TREE_USB3A_H1_CLK_LPM  146
#define CLK_TREE_USB2_0_PHY_REF   147
#define CLK_TREE_USB2_1_PHY_REF   148
#define CLK_TREE_USB2_2_PHY_REF   149
#define CLK_TREE_USB2_3_PHY_REF   150
#define CLK_TREE_USB3C_DRD_PHY_REF  151
#define CLK_TREE_USB3C_H0_PHY_REF  152
#define CLK_TREE_USB3C_H1_PHY_REF  153
#define CLK_TREE_USB3C_H2_PHY_REF  154
#define CLK_TREE_USB3A_H0_PHY_REF  155
#define CLK_TREE_USB3A_H1_PHY_REF  156
#define CLK_TREE_USB3C_DRD_PHY_x4_REF  157
#define CLK_TREE_USB3C_H0_PHY_x4_REF  158
#define CLK_TREE_USB3C_H1_PHY_x4_REF  159
#define CLK_TREE_USB3C_H2_PHY_x4_REF  160
#define CLK_TREE_USB3A_PHY_x2_REF  161
#define CLK_TREE_PCIE_X8CTRL_APB  162
#define CLK_TREE_PCIE_X4CTRL_APB  163
#define CLK_TREE_PCIE_X2CTRL_APB  164
#define CLK_TREE_PCIE_X1_0CTRL_APB  165
#define CLK_TREE_PCIE_X1_1CTRL_APB  166
#define CLK_TREE_PCIE_X8_PHY_APB  167
#define CLK_TREE_PCIE_X4_PHY_APB  168
#define CLK_TREE_PCIE_X211_PHY_APB  169
#define CLK_TREE_PCIE_NI700_CLK   170
#define CLK_TREE_PCIE_CTRL0_CLK   171
#define CLK_TREE_PCIE_CTRL1_CLK   172
#define CLK_TREE_PCIE_CTRL2_CLK   173
#define CLK_TREE_PCIE_CTRL3_CLK   174
#define CLK_TREE_PCIE_CTRL4_CLK   175
#define CLK_TREE_CSI_CTRL0_SYSCLK  176
#define CLK_TREE_CSI_CTRL1_SYSCLK  177
#define CLK_TREE_CSI_CTRL2_SYSCLK  178
#define CLK_TREE_CSI_CTRL3_SYSCLK  179
#define CLK_TREE_CSI_CTRL0_PIXEL0_CLK  180
#define CLK_TREE_CSI_CTRL0_PIXEL1_CLK  181
#define CLK_TREE_CSI_CTRL0_PIXEL2_CLK  182
#define CLK_TREE_CSI_CTRL0_PIXEL3_CLK  183
#define CLK_TREE_CSI_CTRL1_PIXEL0_CLK  184
#define CLK_TREE_CSI_CTRL2_PIXEL0_CLK  185
#define CLK_TREE_CSI_CTRL2_PIXEL1_CLK  186
#define CLK_TREE_CSI_CTRL2_PIXEL2_CLK  187
#define CLK_TREE_CSI_CTRL2_PIXEL3_CLK  188
#define CLK_TREE_CSI_CTRL3_PIXEL0_CLK  189
#define CLK_TREE_CI700_GCLK0   190
#define CLK_TREE_DDRC0_ACLK_CLK   191
#define CLK_TREE_DDRC1_ACLK_CLK   192
#define CLK_TREE_DDRC2_ACLK_CLK   193
#define CLK_TREE_DDRC3_ACLK_CLK   194
#define CLK_TREE_DDRC0_DFICLK_CLK  195
#define CLK_TREE_DDRC1_DFICLK_CLK  196
#define CLK_TREE_DDRC2_DFICLK_CLK  197
#define CLK_TREE_DDRC3_DFICLK_CLK  198
#define CLK_TREE_PHY0_SYNC_CLK   199
#define CLK_TREE_PHY1_SYNC_CLK   200
#define CLK_TREE_PHY2_SYNC_CLK   201
#define CLK_TREE_PHY3_SYNC_CLK   202
#define CLK_TREE_PHY0_BYPASS_CLK  203
#define CLK_TREE_PHY1_BYPASS_CLK  204
#define CLK_TREE_PHY2_BYPASS_CLK  205
#define CLK_TREE_PHY3_BYPASS_CLK  206
#define CLK_TREE_DDRC_0_APB   207
#define CLK_TREE_DDRC_1_APB   208
#define CLK_TREE_DDRC_2_APB   209
#define CLK_TREE_DDRC_3_APB   210
#define CLK_TREE_TZC400_0_APB   211
#define CLK_TREE_TZC400_1_APB   212
#define CLK_TREE_TZC400_2_APB   213
#define CLK_TREE_TZC400_3_APB   214
#define CLK_TREE_S5_SENSOR_HUB_25M  215
#define CLK_TREE_S5_SENSOR_HUB_400M  216
#define CLK_TREE_S5_CSS600_100M   217
#define CLK_TREE_S5_DFD_800M   218
#define CLK_TREE_S5_CSU_SE_800M   219
#define CLK_TREE_S5_CSU_PM_800M   220
#define CLK_TREE_PCIE_REF_B0   221
#define CLK_TREE_PCIE_REF_B1   222
#define CLK_TREE_PCIE_REF_B2   223
#define CLK_TREE_PCIE_REF_B3   224
#define CLK_TREE_PCIE_REF_B4   225
#define CLK_TREE_PCIE_REF_PHY_X8  226
#define CLK_TREE_PCIE_REF_PHY_X4  227
#define CLK_TREE_PCIE_REF_PHY_X211  228
#define CLK_TREE_GMAC_REC_CLK   229
#define CLK_TREE_GPUTOP_PLL   230
#define CLK_TREE_GPUCORE_PLL   231
#define CLK_TREE_CPU_PLL_LIT   232
#define CLK_TREE_CPU_PLL0   233
#define CLK_TREE_CPU_PLL1   234
#define CLK_TREE_CPU_PLL2   235
#define CLK_TREE_CPU_PLL3   236
#define CLK_TREE_FCH_I3C0_FUNC   237
#define CLK_TREE_FCH_I3C1_FUNC   238
#define CLK_TREE_FCH_DMA_ACLK   239
#define CLK_TREE_FCH_XSPI_FUNC   240
#define CLK_TREE_FCH_XSPI_MACLK   241
#define CLK_TREE_FCH_TIMER_FUN   242
#define CLK_TREE_FCH_APB_IO_S0   243
#define CLK_TREE_FCH_I3C0_APB   244
#define CLK_TREE_FCH_I3C1_APB   245
#define CLK_TREE_FCH_UART0_APB   246
#define CLK_TREE_FCH_UART1_APB   247
#define CLK_TREE_FCH_UART2_APB   248
#define CLK_TREE_FCH_UART3_APB   249
#define CLK_TREE_FCH_SPI0_APB   250
#define CLK_TREE_FCH_SPI1_APB   251
#define CLK_TREE_FCH_XSPI_APB   252
#define CLK_TREE_FCH_I2C0_APB   253
#define CLK_TREE_FCH_I2C1_APB   254
#define CLK_TREE_FCH_I2C2_APB   255
#define CLK_TREE_FCH_I2C3_APB   256
#define CLK_TREE_FCH_I2C4_APB   257
#define CLK_TREE_FCH_I2C5_APB   258
#define CLK_TREE_FCH_I2C6_APB   259
#define CLK_TREE_FCH_I2C7_APB   260
#define CLK_TREE_FCH_TIMER_APB   261
#define CLK_TREE_FCH_GPIO_APB   262
#define CLK_TREE_FCH_UART0_FUNC   263
#define CLK_TREE_FCH_UART1_FUNC   264
#define CLK_TREE_FCH_UART2_FUNC   265
#define CLK_TREE_FCH_UART3_FUNC   266
/* 267~271 not used by AP, skip */
#define CLK_TREE_GPU_CLK_200M   272

#endif