/* See the comment in snd_cht_mc_probe() */ if (ctx->quirks & QUIRK_PMC_PLT_CLK_0) return 0;
codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI); if (!codec_dai) {
dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); return -EIO;
}
if (SND_SOC_DAPM_EVENT_ON(event)) {
ret = clk_prepare_enable(ctx->mclk); if (ret < 0) {
dev_err(card->dev, "could not configure MCLK state"); return ret;
}
} else {
clk_disable_unprepare(ctx->mclk);
}
staticint cht_codec_init(struct snd_soc_pcm_runtime *runtime)
{ int ret; int jack_type; struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card); struct snd_soc_jack *jack = &ctx->jack;
if (ctx->ts3a227e_present) { /* * The jack has already been created in the * cht_max98090_headset_init() function.
*/
snd_soc_jack_notifier_register(jack, &cht_jack_nb); return 0;
}
ret = snd_soc_card_jack_new_pins(runtime->card, "Headset Jack",
jack_type, jack,
hs_jack_pins,
ARRAY_SIZE(hs_jack_pins)); if (ret) {
dev_err(runtime->dev, "Headset Jack creation failed %d\n", ret); return ret;
}
ret = snd_soc_jack_add_gpiods(runtime->card->dev->parent, jack,
ARRAY_SIZE(hs_jack_gpios),
hs_jack_gpios); if (ret) { /* * flag error but don't bail if jack detect is broken * due to platform issues or bad BIOS/configuration
*/
dev_err(runtime->dev, "jack detection gpios not added, error %d\n", ret);
}
/* See the comment in snd_cht_mc_probe() */ if (ctx->quirks & QUIRK_PMC_PLT_CLK_0) return 0;
/* * The firmware might enable the clock at * boot (this information may or may not * be reflected in the enable clock register). * To change the rate we must disable the clock * first to cover these cases. Due to common * clock framework restrictions that do not allow * to disable a clock that has not been enabled, * we need to enable the clock first.
*/
ret = clk_prepare_enable(ctx->mclk); if (!ret)
clk_disable_unprepare(ctx->mclk);
ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);
if (ret)
dev_err(runtime->dev, "unable to set MCLK rate\n");
/* use space before codec name to simplify card ID, and simplify driver name */ #define SOF_CARD_NAME "bytcht max98090"/* card name will be 'sof-bytcht max98090 */ #define SOF_DRIVER_NAME "SOF"
#define CARD_NAME "chtmax98090" #define DRIVER_NAME NULL /* card name will be used for driver name */
drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL); if (!drv) return -ENOMEM;
dmi_id = dmi_first_match(cht_max98090_quirk_table); if (dmi_id)
drv->quirks = (unsignedlong)dmi_id->driver_data;
drv->ts3a227e_present = acpi_dev_found("104C227E"); if (!drv->ts3a227e_present) { /* no need probe TI jack detection chip */
snd_soc_card_cht.aux_dev = NULL;
snd_soc_card_cht.num_aux_devs = 0;
ret_val = devm_acpi_dev_add_driver_gpios(dev->parent,
acpi_max98090_gpios); if (ret_val)
dev_dbg(dev, "Unable to add GPIO mapping table\n");
}
drv->mclk = devm_clk_get(dev, mclk_name); if (IS_ERR(drv->mclk)) {
dev_err(dev, "Failed to get MCLK from %s: %ld\n",
mclk_name, PTR_ERR(drv->mclk)); return PTR_ERR(drv->mclk);
}
/* * Boards which have the MAX98090's clk connected to clk_0 do not seem * to like it if we muck with the clock. If we disable the clock when * it is unused we get "max98090 i2c-193C9890:00: PLL unlocked" errors * and the PLL never seems to lock again. * So for these boards we enable it here once and leave it at that.
*/ if (drv->quirks & QUIRK_PMC_PLT_CLK_0) {
ret_val = clk_prepare_enable(drv->mclk); if (ret_val < 0) {
dev_err(dev, "MCLK enable error: %d\n", ret_val); return ret_val;
}
}
sof_parent = snd_soc_acpi_sof_parent(dev);
/* set card and driver name */ if (sof_parent) {
snd_soc_card_cht.name = SOF_CARD_NAME;
snd_soc_card_cht.driver_name = SOF_DRIVER_NAME;
} else {
snd_soc_card_cht.name = CARD_NAME;
snd_soc_card_cht.driver_name = DRIVER_NAME;
}
/* set pm ops */ if (sof_parent)
dev->driver->pm = &snd_soc_pm_ops;
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