uint64_t memstress_nested_pages(int nr_vcpus)
{ /* * 513 page tables is enough to identity-map 256 TiB of L2 with 1G * pages and 4-level paging, plus a few pages per-vCPU for data * structures such as the VMCS.
*/ return 513 + 10 * nr_vcpus;
}
/* * Identity map the first 4G and the test region with 1G pages so that * KVM can shadow the EPT12 with the maximum huge page size supported * by the backing source.
*/
nested_identity_map_1g(vmx, vm, 0, 0x100000000ULL);
start = align_down(memstress_args.gpa, PG_SIZE_1G);
end = align_up(memstress_args.gpa + memstress_args.size, PG_SIZE_1G);
nested_identity_map_1g(vmx, vm, start, end - start);
}
if (vcpu_id == 0) {
memstress_setup_ept(vmx, vm);
vmx0 = vmx;
} else { /* Share the same EPT table across all vCPUs. */
vmx->eptp = vmx0->eptp;
vmx->eptp_hva = vmx0->eptp_hva;
vmx->eptp_gpa = vmx0->eptp_gpa;
}
/* * Override the vCPU to run memstress_l1_guest_code() which will * bounce it into L2 before calling memstress_guest_code().
*/
vcpu_regs_get(vcpus[vcpu_id], ®s);
regs.rip = (unsignedlong) memstress_l1_guest_code;
vcpu_regs_set(vcpus[vcpu_id], ®s);
vcpu_args_set(vcpus[vcpu_id], 2, vmx_gva, vcpu_id);
}
}
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