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Quellcode-Bibliothek© Kompilation durch diese Firma[Weder Korrektheit noch Funktionsfähigkeit der Software werden zugesichert.]Datei: sharedRuntime_ppc.cpp Sprache: C |
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/*
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2012, 2022 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * */ #include "precompiled.hpp" #include "asm/macroAssembler.inline.hpp" #include "code/debugInfoRec.hpp" #include "code/compiledIC.hpp" #include "code/icBuffer.hpp" #include "code/vtableStubs.hpp" #include "frame_ppc.hpp" #include "compiler/oopMap.hpp" #include "gc/shared/gcLocker.hpp" #include "interpreter/interpreter.hpp" #include "interpreter/interp_masm.hpp" #include "memory/resourceArea.hpp" #include "oops/compiledICHolder.hpp" #include "oops/klass.inline.hpp" #include "prims/methodHandles.hpp" #include "runtime/continuation.hpp" #include "runtime/continuationEntry.inline.hpp" #include "runtime/jniHandles.hpp" #include "runtime/os.inline.hpp" #include "runtime/safepointMechanism.hpp" #include "runtime/sharedRuntime.hpp" #include "runtime/signature.hpp" #include "runtime/stubRoutines.hpp" #include "runtime/vframeArray.hpp" #include "utilities/align.hpp" #include "utilities/macros.hpp" #include "vmreg_ppc.inline.hpp" #ifdef COMPILER1 #include "c1/c1_Runtime1.hpp" #endif #ifdef COMPILER2 #include "opto/ad.hpp" #include "opto/runtime.hpp" #endif #include <alloca.h> #define __ masm-> #ifdef PRODUCT #define BLOCK_COMMENT(str) // nothing #else #define BLOCK_COMMENT(str) __ block_comment(str) #endif #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") class RegisterSaver { // Used for saving volatile registers. public: // Support different return pc locations. enum ReturnPCLocation { return_pc_is_lr, return_pc_is_pre_saved, return_pc_is_thread_saved_exception_pc }; static OopMap* push_frame_reg_args_and_save_live_registers(MacroAssembler* masm, int* out_frame_size_in_bytes, bool generate_oop_map, int return_pc_adjustment, ReturnPCLocation return_pc_location, bool save_vectors = false); static void restore_live_registers_and_pop_frame(MacroAssembler* masm, int frame_size_in_bytes, bool restore_ctr, bool save_vectors = false); static void push_frame_and_save_argument_registers(MacroAssembler* masm, Register r_temp, int frame_size, int total_args, const VMRegPair *regs, const VMRegPair *regs2 = NULL); static void restore_argument_registers_and_pop_frame(MacroAssembler*masm, int frame_size, int total_args, const VMRegPair *regs, const VMRegPair *regs2 = NULL); // During deoptimization only the result registers need to be restored // all the other values have already been extracted. static void restore_result_registers(MacroAssembler* masm, int frame_size_in_bytes); // Constants and data structures: typedef enum { int_reg, float_reg, special_reg, vs_reg } RegisterType; typedef enum { reg_size = 8, half_reg_size = reg_size / 2, vs_reg_size = 16 } RegisterConstants; typedef struct { RegisterType reg_type; int reg_num; VMReg vmreg; } LiveRegType; }; #define RegisterSaver_LiveIntReg(regname) \ { RegisterSaver::int_reg, regname->encoding(), regname->as_VMReg() } #define RegisterSaver_LiveFloatReg(regname) \ { RegisterSaver::float_reg, regname->encoding(), regname->as_VMReg() } #define RegisterSaver_LiveSpecialReg(regname) \ { RegisterSaver::special_reg, regname->encoding(), regname->as_VMReg() } #define RegisterSaver_LiveVSReg(regname) \ { RegisterSaver::vs_reg, regname->encoding(), regname->as_VMReg() } static const RegisterSaver::LiveRegType RegisterSaver_LiveRegs[] = { // Live registers which get spilled to the stack. Register // positions in this array correspond directly to the stack layout. // // live special registers: // RegisterSaver_LiveSpecialReg(SR_CTR), // // live float registers: // RegisterSaver_LiveFloatReg( F0 ), RegisterSaver_LiveFloatReg( F1 ), RegisterSaver_LiveFloatReg( F2 ), RegisterSaver_LiveFloatReg( F3 ), RegisterSaver_LiveFloatReg( F4 ), RegisterSaver_LiveFloatReg( F5 ), RegisterSaver_LiveFloatReg( F6 ), RegisterSaver_LiveFloatReg( F7 ), RegisterSaver_LiveFloatReg( F8 ), RegisterSaver_LiveFloatReg( F9 ), RegisterSaver_LiveFloatReg( F10 ), RegisterSaver_LiveFloatReg( F11 ), RegisterSaver_LiveFloatReg( F12 ), RegisterSaver_LiveFloatReg( F13 ), RegisterSaver_LiveFloatReg( F14 ), RegisterSaver_LiveFloatReg( F15 ), RegisterSaver_LiveFloatReg( F16 ), RegisterSaver_LiveFloatReg( F17 ), RegisterSaver_LiveFloatReg( F18 ), RegisterSaver_LiveFloatReg( F19 ), RegisterSaver_LiveFloatReg( F20 ), RegisterSaver_LiveFloatReg( F21 ), RegisterSaver_LiveFloatReg( F22 ), RegisterSaver_LiveFloatReg( F23 ), RegisterSaver_LiveFloatReg( F24 ), RegisterSaver_LiveFloatReg( F25 ), RegisterSaver_LiveFloatReg( F26 ), RegisterSaver_LiveFloatReg( F27 ), RegisterSaver_LiveFloatReg( F28 ), RegisterSaver_LiveFloatReg( F29 ), RegisterSaver_LiveFloatReg( F30 ), RegisterSaver_LiveFloatReg( F31 ), // // live integer registers: // RegisterSaver_LiveIntReg( R0 ), //RegisterSaver_LiveIntReg( R1 ), // stack pointer RegisterSaver_LiveIntReg( R2 ), RegisterSaver_LiveIntReg( R3 ), RegisterSaver_LiveIntReg( R4 ), RegisterSaver_LiveIntReg( R5 ), RegisterSaver_LiveIntReg( R6 ), RegisterSaver_LiveIntReg( R7 ), RegisterSaver_LiveIntReg( R8 ), RegisterSaver_LiveIntReg( R9 ), RegisterSaver_LiveIntReg( R10 ), RegisterSaver_LiveIntReg( R11 ), RegisterSaver_LiveIntReg( R12 ), //RegisterSaver_LiveIntReg( R13 ), // system thread id RegisterSaver_LiveIntReg( R14 ), RegisterSaver_LiveIntReg( R15 ), RegisterSaver_LiveIntReg( R16 ), RegisterSaver_LiveIntReg( R17 ), RegisterSaver_LiveIntReg( R18 ), RegisterSaver_LiveIntReg( R19 ), RegisterSaver_LiveIntReg( R20 ), RegisterSaver_LiveIntReg( R21 ), RegisterSaver_LiveIntReg( R22 ), RegisterSaver_LiveIntReg( R23 ), RegisterSaver_LiveIntReg( R24 ), RegisterSaver_LiveIntReg( R25 ), RegisterSaver_LiveIntReg( R26 ), RegisterSaver_LiveIntReg( R27 ), RegisterSaver_LiveIntReg( R28 ), RegisterSaver_LiveIntReg( R29 ), RegisterSaver_LiveIntReg( R30 ), RegisterSaver_LiveIntReg( R31 ) // must be the last register (see save/restore functions bel }; static const RegisterSaver::LiveRegType RegisterSaver_LiveVSRegs[] = { // // live vector scalar registers (optional, only these ones are used by C2): // RegisterSaver_LiveVSReg( VSR32 ), RegisterSaver_LiveVSReg( VSR33 ), RegisterSaver_LiveVSReg( VSR34 ), RegisterSaver_LiveVSReg( VSR35 ), RegisterSaver_LiveVSReg( VSR36 ), RegisterSaver_LiveVSReg( VSR37 ), RegisterSaver_LiveVSReg( VSR38 ), RegisterSaver_LiveVSReg( VSR39 ), RegisterSaver_LiveVSReg( VSR40 ), RegisterSaver_LiveVSReg( VSR41 ), RegisterSaver_LiveVSReg( VSR42 ), RegisterSaver_LiveVSReg( VSR43 ), RegisterSaver_LiveVSReg( VSR44 ), RegisterSaver_LiveVSReg( VSR45 ), RegisterSaver_LiveVSReg( VSR46 ), RegisterSaver_LiveVSReg( VSR47 ), RegisterSaver_LiveVSReg( VSR48 ), RegisterSaver_LiveVSReg( VSR49 ), RegisterSaver_LiveVSReg( VSR50 ), RegisterSaver_LiveVSReg( VSR51 ) }; OopMap* RegisterSaver::push_frame_reg_args_and_save_live_registers(MacroAssembler int* out_frame_size_in_bytes, bool generate_oop_map, int return_pc_adjustment, ReturnPCLocation return_pc_location, bool save_vectors) { // Push an abi_reg_args-frame and store all registers which may be live. // If requested, create an OopMap: Record volatile registers as // callee-save values in an OopMap so their save locations will be // propagated to the RegisterMap of the caller frame during // StackFrameStream construction (needed for deoptimization; see // compiledVFrame::create_stack_value). // If return_pc_adjustment != 0 adjust the return pc by return_pc_adjustment. // Updated return pc is returned in R31 (if not return_pc_is_pre_saved). // calculate frame size const int regstosave_num = sizeof(RegisterSaver_LiveRegs) / sizeof(RegisterSaver::LiveRegType); const int vsregstosave_num = save_vectors ? (sizeof(RegisterSaver_LiveVSRegs) / sizeof(RegisterSaver::LiveRegType)) : 0; const int register_save_size = regstosave_num * reg_size + vsregstosave_num * vs_reg_size; const int frame_size_in_bytes = align_up(register_save_size, frame::alignment_in_byte + frame::abi_reg_args_size; *out_frame_size_in_bytes = frame_size_in_bytes; const int frame_size_in_slots = frame_size_in_bytes / sizeof(jint); const int register_save_offset = frame_size_in_bytes - register_save_size; // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words. OopMap* map = generate_oop_map ? new OopMap(frame_size_in_slots, 0) : NULL; BLOCK_COMMENT("push_frame_reg_args_and_save_live_registers {"); // push a new frame __ push_frame(frame_size_in_bytes, noreg); // Save some registers in the last (non-vector) slots of the new frame so we // can use them as scratch regs or to determine the return pc. __ std(R31, frame_size_in_bytes - reg_size - vsregstosave_num * vs_reg_size, R1_SP); __ std(R30, frame_size_in_bytes - 2*reg_size - vsregstosave_num * vs_reg_size, R1_SP); // save the flags // Do the save_LR_CR by hand and adjust the return pc if requested. __ mfcr(R30); __ std(R30, frame_size_in_bytes + _abi0(cr), R1_SP); switch (return_pc_location) { case return_pc_is_lr: __ mflr(R31); break; case return_pc_is_pre_saved: assert(return_pc_adjustment == 0, "unsupported"); break; case return_pc_is_thread_saved_exception_pc: __ ld(R31, thread_(saved_exception_pc)) default: ShouldNotReachHere(); } if (return_pc_location != return_pc_is_pre_saved) { if (return_pc_adjustment != 0) { __ addi(R31, R31, return_pc_adjustment); } __ std(R31, frame_size_in_bytes + _abi0(lr), R1_SP); } // save all registers (ints and floats) int offset = register_save_offset; for (int i = 0; i < regstosave_num; i++) { int reg_num = RegisterSaver_LiveRegs[i].reg_num; int reg_type = RegisterSaver_LiveRegs[i].reg_type; switch (reg_type) { case RegisterSaver::int_reg: { if (reg_num < 30) { // We spilled R30-31 right at the beginning. __ std(as_Register(reg_num), offset, R1_SP); } break; } case RegisterSaver::float_reg: { __ stfd(as_FloatRegister(reg_num), offset, R1_SP); break; } case RegisterSaver::special_reg: { if (reg_num == SR_CTR.encoding()) { __ mfctr(R30); __ std(R30, offset, R1_SP); } else { Unimplemented(); } break; } default: ShouldNotReachHere(); } if (generate_oop_map) { map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), RegisterSaver_LiveRegs[i].vmreg); map->set_callee_saved(VMRegImpl::stack2reg((offset + half_reg_size)>>2), RegisterSaver_LiveRegs[i].vmreg->next()); } offset += reg_size; } for (int i = 0; i < vsregstosave_num; i++) { int reg_num = RegisterSaver_LiveVSRegs[i].reg_num; int reg_type = RegisterSaver_LiveVSRegs[i].reg_type; __ li(R30, offset); __ stxvd2x(as_VectorSRegister(reg_num), R30, R1_SP); if (generate_oop_map) { map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), RegisterSaver_LiveVSRegs[i].vmreg); } offset += vs_reg_size; } assert(offset == frame_size_in_bytes, "consistency check"); BLOCK_COMMENT("} push_frame_reg_args_and_save_live_registers"); // And we're done. return map; } // Pop the current frame and restore all the registers that we // saved. void RegisterSaver::restore_live_registers_and_pop_frame(MacroAssembler* masm, int frame_size_in_bytes, bool restore_ctr, bool save_vectors) { const int regstosave_num = sizeof(RegisterSaver_LiveRegs) / sizeof(RegisterSaver::LiveRegType); const int vsregstosave_num = save_vectors ? (sizeof(RegisterSaver_LiveVSRegs) / sizeof(RegisterSaver::LiveRegType)) : 0; const int register_save_size = regstosave_num * reg_size + vsregstosave_num * vs_reg_size; const int register_save_offset = frame_size_in_bytes - register_save_size; BLOCK_COMMENT("restore_live_registers_and_pop_frame {"); // restore all registers (ints and floats) int offset = register_save_offset; for (int i = 0; i < regstosave_num; i++) { int reg_num = RegisterSaver_LiveRegs[i].reg_num; int reg_type = RegisterSaver_LiveRegs[i].reg_type; switch (reg_type) { case RegisterSaver::int_reg: { if (reg_num != 31) // R31 restored at the end, it's the tmp reg! __ ld(as_Register(reg_num), offset, R1_SP); break; } case RegisterSaver::float_reg: { __ lfd(as_FloatRegister(reg_num), offset, R1_SP); break; } case RegisterSaver::special_reg: { if (reg_num == SR_CTR.encoding()) { if (restore_ctr) { // Nothing to do here if ctr already contains the next address. __ ld(R31, offset, R1_SP); __ mtctr(R31); } } else { Unimplemented(); } break; } default: ShouldNotReachHere(); } offset += reg_size; } for (int i = 0; i < vsregstosave_num; i++) { int reg_num = RegisterSaver_LiveVSRegs[i].reg_num; int reg_type = RegisterSaver_LiveVSRegs[i].reg_type; __ li(R31, offset); __ lxvd2x(as_VectorSRegister(reg_num), R31, R1_SP); offset += vs_reg_size; } assert(offset == frame_size_in_bytes, "consistency check"); // restore link and the flags __ ld(R31, frame_size_in_bytes + _abi0(lr), R1_SP); __ mtlr(R31); __ ld(R31, frame_size_in_bytes + _abi0(cr), R1_SP); __ mtcr(R31); // restore scratch register's value __ ld(R31, frame_size_in_bytes - reg_size - vsregstosave_num * vs_reg_size, R1_SP); // pop the frame __ addi(R1_SP, R1_SP, frame_size_in_bytes); BLOCK_COMMENT("} restore_live_registers_and_pop_frame"); } void RegisterSaver::push_frame_and_save_argument_registers(MacroAssembler* masm, Re int frame_size,int total_args, const VMRegPair *regs, const VMRegPair *regs2) { __ push_frame(frame_size, r_temp); int st_off = frame_size - wordSize; for (int i = 0; i < total_args; i++) { VMReg r_1 = regs[i].first(); VMReg r_2 = regs[i].second(); if (!r_1->is_valid()) { assert(!r_2->is_valid(), ""); continue; } if (r_1->is_Register()) { Register r = r_1->as_Register(); __ std(r, st_off, R1_SP); st_off -= wordSize; } else if (r_1->is_FloatRegister()) { FloatRegister f = r_1->as_FloatRegister(); __ stfd(f, st_off, R1_SP); st_off -= wordSize; } } if (regs2 != NULL) { for (int i = 0; i < total_args; i++) { VMReg r_1 = regs2[i].first(); VMReg r_2 = regs2[i].second(); if (!r_1->is_valid()) { assert(!r_2->is_valid(), ""); continue; } if (r_1->is_Register()) { Register r = r_1->as_Register(); __ std(r, st_off, R1_SP); st_off -= wordSize; } else if (r_1->is_FloatRegister()) { FloatRegister f = r_1->as_FloatRegister(); __ stfd(f, st_off, R1_SP); st_off -= wordSize; } } } } void RegisterSaver::restore_argument_registers_and_pop_frame(MacroAssembler*masm, int total_args, const VMRegPair *regs, const VMRegPair *regs2) { int st_off = frame_size - wordSize; for (int i = 0; i < total_args; i++) { VMReg r_1 = regs[i].first(); VMReg r_2 = regs[i].second(); if (r_1->is_Register()) { Register r = r_1->as_Register(); __ ld(r, st_off, R1_SP); st_off -= wordSize; } else if (r_1->is_FloatRegister()) { FloatRegister f = r_1->as_FloatRegister(); __ lfd(f, st_off, R1_SP); st_off -= wordSize; } } if (regs2 != NULL) for (int i = 0; i < total_args; i++) { VMReg r_1 = regs2[i].first(); VMReg r_2 = regs2[i].second(); if (r_1->is_Register()) { Register r = r_1->as_Register(); __ ld(r, st_off, R1_SP); st_off -= wordSize; } else if (r_1->is_FloatRegister()) { FloatRegister f = r_1->as_FloatRegister(); __ lfd(f, st_off, R1_SP); st_off -= wordSize; } } __ pop_frame(); } // Restore the registers that might be holding a result. void RegisterSaver::restore_result_registers(MacroAssembler* masm, int frame_size_in const int regstosave_num = sizeof(RegisterSaver_LiveRegs) / sizeof(RegisterSaver::LiveRegType); const int register_save_size = regstosave_num * reg_size; // VS registers not relevant here. const int register_save_offset = frame_size_in_bytes - register_save_size; // restore all result registers (ints and floats) int offset = register_save_offset; for (int i = 0; i < regstosave_num; i++) { int reg_num = RegisterSaver_LiveRegs[i].reg_num; int reg_type = RegisterSaver_LiveRegs[i].reg_type; switch (reg_type) { case RegisterSaver::int_reg: { if (as_Register(reg_num)==R3_RET) // int result_reg __ ld(as_Register(reg_num), offset, R1_SP); break; } case RegisterSaver::float_reg: { if (as_FloatRegister(reg_num)==F1_RET) // float result_reg __ lfd(as_FloatRegister(reg_num), offset, R1_SP); break; } case RegisterSaver::special_reg: { // Special registers don't hold a result. break; } default: ShouldNotReachHere(); } offset += reg_size; } assert(offset == frame_size_in_bytes, "consistency check"); } // Is vector's size (in bytes) bigger than a size saved by default? bool SharedRuntime::is_wide_vector(int size) { // Note, MaxVectorSize == 8/16 on PPC64. assert(size <= (SuperwordUseVSX ? 16 : 8), "%d bytes vectors are not supported", size); return size > 8; } static int reg2slot(VMReg r) { return r->reg2stack() + SharedRuntime::out_preserve_stack_slots(); } static int reg2offset(VMReg r) { return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack } // --------------------------------------------------------------------------- // Read the array of BasicTypes from a signature, and compute where the // arguments should go. Values in the VMRegPair regs array refer to 4-byte // quantities. Values less than VMRegImpl::stack0 are registers, those above // refer to 4-byte stack slots. All stack slots are based off of the stack pointer // as framesizes are fixed. // VMRegImpl::stack0 refers to the first slot 0(sp). // and VMRegImpl::stack0+1 refers to the memory word 4-bytes higher. Register // up to Register::number_of_registers) are the 64-bit // integer registers. // Note: the INPUTS in sig_bt are in units of Java argument words, which are // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit // units regardless of build. Of course for i486 there is no 64 bit build // The Java calling convention is a "shifted" version of the C ABI. // By skipping the first C ABI register we can call non-static jni methods // with small numbers of arguments without having to shuffle the arguments // at all. Since we control the java ABI we ought to at least get some // advantage out of it. const VMReg java_iarg_reg[8] = { R3->as_VMReg(), R4->as_VMReg(), R5->as_VMReg(), R6->as_VMReg(), R7->as_VMReg(), R8->as_VMReg(), R9->as_VMReg(), R10->as_VMReg() }; const VMReg java_farg_reg[13] = { F1->as_VMReg(), F2->as_VMReg(), F3->as_VMReg(), F4->as_VMReg(), F5->as_VMReg(), F6->as_VMReg(), F7->as_VMReg(), F8->as_VMReg(), F9->as_VMReg(), F10->as_VMReg(), F11->as_VMReg(), F12->as_VMReg(), F13->as_VMReg() }; const int num_java_iarg_registers = sizeof(java_iarg_reg) / sizeof(java_iarg_reg[0]); const int num_java_farg_registers = sizeof(java_farg_reg) / sizeof(java_farg_reg[0]); STATIC_ASSERT(num_java_iarg_registers == Argument::n_int_register_parameters_j); STATIC_ASSERT(num_java_farg_registers == Argument::n_float_register_parameters_j); int SharedRuntime::java_calling_convention(const BasicType *sig_bt, VMRegPair *regs, int total_args_passed) { // C2c calling conventions for compiled-compiled calls. // Put 8 ints/longs into registers _AND_ 13 float/doubles into // registers _AND_ put the rest on the stack. const int inc_stk_for_intfloat = 1; // 1 slots for ints and floats const int inc_stk_for_longdouble = 2; // 2 slots for longs and doubles int i; VMReg reg; int stk = 0; int ireg = 0; int freg = 0; // We put the first 8 arguments into registers and the rest on the // stack, float arguments are already in their argument registers // due to c2c calling conventions (see calling_convention). for (int i = 0; i < total_args_passed; ++i) { switch(sig_bt[i]) { case T_BOOLEAN: case T_CHAR: case T_BYTE: case T_SHORT: case T_INT: if (ireg < num_java_iarg_registers) { // Put int/ptr in register reg = java_iarg_reg[ireg]; ++ireg; } else { // Put int/ptr on stack. reg = VMRegImpl::stack2reg(stk); stk += inc_stk_for_intfloat; } regs[i].set1(reg); break; case T_LONG: assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "expecting half"); if (ireg < num_java_iarg_registers) { // Put long in register. reg = java_iarg_reg[ireg]; ++ireg; } else { // Put long on stack. They must be aligned to 2 slots. if (stk & 0x1) ++stk; reg = VMRegImpl::stack2reg(stk); stk += inc_stk_for_longdouble; } regs[i].set2(reg); break; case T_OBJECT: case T_ARRAY: case T_ADDRESS: if (ireg < num_java_iarg_registers) { // Put ptr in register. reg = java_iarg_reg[ireg]; ++ireg; } else { // Put ptr on stack. Objects must be aligned to 2 slots too, // because "64-bit pointers record oop-ishness on 2 aligned // adjacent registers." (see OopFlow::build_oop_map). if (stk & 0x1) ++stk; reg = VMRegImpl::stack2reg(stk); stk += inc_stk_for_longdouble; } regs[i].set2(reg); break; case T_FLOAT: if (freg < num_java_farg_registers) { // Put float in register. reg = java_farg_reg[freg]; ++freg; } else { // Put float on stack. reg = VMRegImpl::stack2reg(stk); stk += inc_stk_for_intfloat; } regs[i].set1(reg); break; case T_DOUBLE: assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "expecting half"); if (freg < num_java_farg_registers) { // Put double in register. reg = java_farg_reg[freg]; ++freg; } else { // Put double on stack. They must be aligned to 2 slots. if (stk & 0x1) ++stk; reg = VMRegImpl::stack2reg(stk); stk += inc_stk_for_longdouble; } regs[i].set2(reg); break; case T_VOID: // Do not count halves. regs[i].set_bad(); break; default: ShouldNotReachHere(); } } return align_up(stk, 2); } #if defined(COMPILER1) || defined(COMPILER2) // Calling convention for calling C code. int SharedRuntime::c_calling_convention(const BasicType *sig_bt, VMRegPair *regs, VMRegPair *regs2, int total_args_passed) { // Calling conventions for C runtime calls and calls to JNI native methods. // // PPC64 convention: Hoist the first 8 int/ptr/long's in the first 8 // int regs, leaving int regs undefined if the arg is flt/dbl. Hoist // the first 13 flt/dbl's in the first 13 fp regs but additionally // copy flt/dbl to the stack if they are beyond the 8th argument. const VMReg iarg_reg[8] = { R3->as_VMReg(), R4->as_VMReg(), R5->as_VMReg(), R6->as_VMReg(), R7->as_VMReg(), R8->as_VMReg(), R9->as_VMReg(), R10->as_VMReg() }; const VMReg farg_reg[13] = { F1->as_VMReg(), F2->as_VMReg(), F3->as_VMReg(), F4->as_VMReg(), F5->as_VMReg(), F6->as_VMReg(), F7->as_VMReg(), F8->as_VMReg(), F9->as_VMReg(), F10->as_VMReg(), F11->as_VMReg(), F12->as_VMReg(), F13->as_VMReg() }; // Check calling conventions consistency. assert(sizeof(iarg_reg) / sizeof(iarg_reg[0]) == Argument::n_int_register_parameters sizeof(farg_reg) / sizeof(farg_reg[0]) == Argument::n_float_register_parameters_c, "consistency"); // `Stk' counts stack slots. Due to alignment, 32 bit values occupy // 2 such slots, like 64 bit values do. const int inc_stk_for_intfloat = 2; // 2 slots for ints and floats const int inc_stk_for_longdouble = 2; // 2 slots for longs and doubles int i; VMReg reg; // Leave room for C-compatible ABI_REG_ARGS. int stk = (frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_ int arg = 0; int freg = 0; // Avoid passing C arguments in the wrong stack slots. #if defined(ABI_ELFv2) assert((SharedRuntime::out_preserve_stack_slots() + stk) * VMRegImpl::stack_slot_siz "passing C arguments in wrong stack slots"); #else assert((SharedRuntime::out_preserve_stack_slots() + stk) * VMRegImpl::stack_slot_siz "passing C arguments in wrong stack slots"); #endif // We fill-out regs AND regs2 if an argument must be passed in a // register AND in a stack slot. If regs2 is NULL in such a // situation, we bail-out with a fatal error. for (int i = 0; i < total_args_passed; ++i, ++arg) { // Initialize regs2 to BAD. if (regs2 != NULL) regs2[i].set_bad(); switch(sig_bt[i]) { // // If arguments 0-7 are integers, they are passed in integer registers. // Argument i is placed in iarg_reg[i]. // case T_BOOLEAN: case T_CHAR: case T_BYTE: case T_SHORT: case T_INT: // We must cast ints to longs and use full 64 bit stack slots // here. Thus fall through, handle as long. case T_LONG: case T_OBJECT: case T_ARRAY: case T_ADDRESS: case T_METADATA: // Oops are already boxed if required (JNI). if (arg < Argument::n_int_register_parameters_c) { reg = iarg_reg[arg]; } else { reg = VMRegImpl::stack2reg(stk); stk += inc_stk_for_longdouble; } regs[i].set2(reg); break; // // Floats are treated differently from int regs: The first 13 float arguments // are passed in registers (not the float args among the first 13 args). // Thus argument i is NOT passed in farg_reg[i] if it is float. It is passed // in farg_reg[j] if argument i is the j-th float argument of this call. // case T_FLOAT: #if defined(LINUX) // Linux uses ELF ABI. Both original ELF and ELFv2 ABIs have float // in the least significant word of an argument slot. #if defined(VM_LITTLE_ENDIAN) #define FLOAT_WORD_OFFSET_IN_SLOT 0 #else #define FLOAT_WORD_OFFSET_IN_SLOT 1 #endif #elif defined(AIX) // Although AIX runs on big endian CPU, float is in the most // significant word of an argument slot. #define FLOAT_WORD_OFFSET_IN_SLOT 0 #else #error "unknown OS" #endif if (freg < Argument::n_float_register_parameters_c) { // Put float in register ... reg = farg_reg[freg]; ++freg; // Argument i for i > 8 is placed on the stack even if it's // placed in a register (if it's a float arg). Aix disassembly // shows that xlC places these float args on the stack AND in // a register. This is not documented, but we follow this // convention, too. if (arg >= Argument::n_regs_not_on_stack_c) { // ... and on the stack. guarantee(regs2 != NULL, "must pass float in register and stack slot"); VMReg reg2 = VMRegImpl::stack2reg(stk + FLOAT_WORD_OFFSET_IN_SLOT); regs2[i].set1(reg2); stk += inc_stk_for_intfloat; } } else { // Put float on stack. reg = VMRegImpl::stack2reg(stk + FLOAT_WORD_OFFSET_IN_SLOT); stk += inc_stk_for_intfloat; } regs[i].set1(reg); break; case T_DOUBLE: assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "expecting half"); if (freg < Argument::n_float_register_parameters_c) { // Put double in register ... reg = farg_reg[freg]; ++freg; // Argument i for i > 8 is placed on the stack even if it's // placed in a register (if it's a double arg). Aix disassembly // shows that xlC places these float args on the stack AND in // a register. This is not documented, but we follow this // convention, too. if (arg >= Argument::n_regs_not_on_stack_c) { // ... and on the stack. guarantee(regs2 != NULL, "must pass float in register and stack slot"); VMReg reg2 = VMRegImpl::stack2reg(stk); regs2[i].set2(reg2); stk += inc_stk_for_longdouble; } } else { // Put double on stack. reg = VMRegImpl::stack2reg(stk); stk += inc_stk_for_longdouble; } regs[i].set2(reg); break; case T_VOID: // Do not count halves. regs[i].set_bad(); --arg; break; default: ShouldNotReachHere(); } } return align_up(stk, 2); } #endif // COMPILER2 int SharedRuntime::vector_calling_convention(VMRegPair *regs, uint num_bits, uint total_args_passed) { Unimplemented(); return 0; } static address gen_c2i_adapter(MacroAssembler *masm, int total_args_passed, int comp_args_on_stack, const BasicType *sig_bt, const VMRegPair *regs, Label& call_interpreter, const Register& ientry) { address c2i_entrypoint; const Register sender_SP = R21_sender_SP; // == R21_tmp1 const Register code = R22_tmp2; //const Register ientry = R23_tmp3; const Register value_regs[] = { R24_tmp4, R25_tmp5, R26_tmp6 }; const int num_value_regs = sizeof(value_regs) / sizeof(Register); int value_regs_index = 0; const Register return_pc = R27_tmp7; const Register tmp = R28_tmp8; assert_different_registers(sender_SP, code, ientry, return_pc, tmp); // Adapter needs TOP_IJAVA_FRAME_ABI. const int adapter_size = frame::top_ijava_frame_abi_size + align_up(total_args_passed * wordSize, frame::alignment_in_bytes); // regular (verified) c2i entry point c2i_entrypoint = __ pc(); // Does compiled code exists? If yes, patch the caller's callsite. __ ld(code, method_(code)); __ cmpdi(CCR0, code, 0); __ ld(ientry, method_(interpreter_entry)); // preloaded __ beq(CCR0, call_interpreter); // Patch caller's callsite, method_(code) was not NULL which means that // compiled code exists. __ mflr(return_pc); __ std(return_pc, _abi0(lr), R1_SP); RegisterSaver::push_frame_and_save_argument_registers(masm, tmp, adapter_size, tota __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), R RegisterSaver::restore_argument_registers_and_pop_frame(masm, adapter_size, total_ __ ld(return_pc, _abi0(lr), R1_SP); __ ld(ientry, method_(interpreter_entry)); // preloaded __ mtlr(return_pc); // Call the interpreter. __ BIND(call_interpreter); __ mtctr(ientry); // Get a copy of the current SP for loading caller's arguments. __ mr(sender_SP, R1_SP); // Add space for the adapter. __ resize_frame(-adapter_size, R12_scratch2); int st_off = adapter_size - wordSize; // Write the args into the outgoing interpreter space. for (int i = 0; i < total_args_passed; i++) { VMReg r_1 = regs[i].first(); VMReg r_2 = regs[i].second(); if (!r_1->is_valid()) { assert(!r_2->is_valid(), ""); continue; } if (r_1->is_stack()) { Register tmp_reg = value_regs[value_regs_index]; value_regs_index = (value_regs_index + 1) % num_value_regs; // The calling convention produces OptoRegs that ignore the out // preserve area (JIT's ABI). We must account for it here. int ld_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl: if (!r_2->is_valid()) { __ lwz(tmp_reg, ld_off, sender_SP); } else { __ ld(tmp_reg, ld_off, sender_SP); } // Pretend stack targets were loaded into tmp_reg. r_1 = tmp_reg->as_VMReg(); } if (r_1->is_Register()) { Register r = r_1->as_Register(); if (!r_2->is_valid()) { __ stw(r, st_off, R1_SP); st_off-=wordSize; } else { // Longs are given 2 64-bit slots in the interpreter, but the // data is passed in only 1 slot. if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { DEBUG_ONLY( __ li(tmp, 0); __ std(tmp, st_off, R1_SP); ) st_off-=wordSize; } __ std(r, st_off, R1_SP); st_off-=wordSize; } } else { assert(r_1->is_FloatRegister(), ""); FloatRegister f = r_1->as_FloatRegister(); if (!r_2->is_valid()) { __ stfs(f, st_off, R1_SP); st_off-=wordSize; } else { // In 64bit, doubles are given 2 64-bit slots in the interpreter, but the // data is passed in only 1 slot. // One of these should get known junk... DEBUG_ONLY( __ li(tmp, 0); __ std(tmp, st_off, R1_SP); ) st_off-=wordSize; __ stfd(f, st_off, R1_SP); st_off-=wordSize; } } } // Jump to the interpreter just as if interpreter was doing it. __ load_const_optimized(R25_templateTableBase, (address)Interpreter::dispatch_tabl // load TOS __ addi(R15_esp, R1_SP, st_off); // Frame_manager expects initial_caller_sp (= SP without resize by c2i) in R21_tmp1. assert(sender_SP == R21_sender_SP, "passing initial caller's SP in wrong register") __ bctr(); return c2i_entrypoint; } void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm, int total_args_passed, int comp_args_on_stack, const BasicType *sig_bt, const VMRegPair *regs) { // Load method's entry-point from method. __ ld(R12_scratch2, in_bytes(Method::from_compiled_offset()), R19_method); __ mtctr(R12_scratch2); // We will only enter here from an interpreted frame and never from after // passing thru a c2i. Azul allowed this but we do not. If we lose the // race and use a c2i we will remain interpreted for the race loser(s). // This removes all sorts of headaches on the x86 side and also eliminates // the possibility of having c2i -> i2c -> c2i -> ... endless transitions. // Note: r13 contains the senderSP on entry. We must preserve it since // we may do a i2c -> c2i transition if we lose a race where compiled // code goes non-entrant while we get args ready. // In addition we use r13 to locate all the interpreter args as // we must align the stack to 16 bytes on an i2c entry else we // lose alignment we expect in all compiled code and register // save code can segv when fxsave instructions find improperly // aligned stack pointer. const Register ld_ptr = R15_esp; const Register value_regs[] = { R22_tmp2, R23_tmp3, R24_tmp4, R25_tmp5, R26_tmp6 }; const int num_value_regs = sizeof(value_regs) / sizeof(Register); int value_regs_index = 0; int ld_offset = total_args_passed*wordSize; // Cut-out for having no stack args. Since up to 2 int/oop args are passed // in registers, we will occasionally have no stack args. int comp_words_on_stack = 0; if (comp_args_on_stack) { // Sig words on the stack are greater-than VMRegImpl::stack0. Those in // registers are below. By subtracting stack0, we either get a negative // number (all values in registers) or the maximum stack slot accessed. // Convert 4-byte c2 stack slots to words. comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordS // Round up to miminum stack alignment, in wordSize. comp_words_on_stack = align_up(comp_words_on_stack, 2); __ resize_frame(-comp_words_on_stack * wordSize, R11_scratch1); } // Now generate the shuffle code. Pick up all register args and move the // rest through register value=Z_R12. BLOCK_COMMENT("Shuffle arguments"); for (int i = 0; i < total_args_passed; i++) { if (sig_bt[i] == T_VOID) { assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); continue; } // Pick up 0, 1 or 2 words from ld_ptr. assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), "scrambled load targets?"); VMReg r_1 = regs[i].first(); VMReg r_2 = regs[i].second(); if (!r_1->is_valid()) { assert(!r_2->is_valid(), ""); continue; } if (r_1->is_FloatRegister()) { if (!r_2->is_valid()) { __ lfs(r_1->as_FloatRegister(), ld_offset, ld_ptr); ld_offset-=wordSize; } else { // Skip the unused interpreter slot. __ lfd(r_1->as_FloatRegister(), ld_offset-wordSize, ld_ptr); ld_offset-=2*wordSize; } } else { Register r; if (r_1->is_stack()) { // Must do a memory to memory move thru "value". r = value_regs[value_regs_index]; value_regs_index = (value_regs_index + 1) % num_value_regs; } else { r = r_1->as_Register(); } if (!r_2->is_valid()) { // Not sure we need to do this but it shouldn't hurt. if (is_reference_type(sig_bt[i]) || sig_bt[i] == T_ADDRESS) { __ ld(r, ld_offset, ld_ptr); ld_offset-=wordSize; } else { __ lwz(r, ld_offset, ld_ptr); ld_offset-=wordSize; } } else { // In 64bit, longs are given 2 64-bit slots in the interpreter, but the // data is passed in only 1 slot. if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { ld_offset-=wordSize; } __ ld(r, ld_offset, ld_ptr); ld_offset-=wordSize; } if (r_1->is_stack()) { // Now store value where the compiler expects it int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots())*VMRegImpl: if (sig_bt[i] == T_INT || sig_bt[i] == T_FLOAT ||sig_bt[i] == T_BOOLEAN || sig_bt[i] == T_SHORT || sig_bt[i] == T_CHAR || sig_bt[i] == T_BYTE) { __ stw(r, st_off, R1_SP); } else { __ std(r, st_off, R1_SP); } } } } __ push_cont_fastpath(); // Set JavaThread::_cont_fastpath to the sp of the oldest interpre BLOCK_COMMENT("Store method"); // Store method into thread->callee_target. // We might end up in handle_wrong_method if the callee is // deoptimized as we race thru here. If that happens we don't want // to take a safepoint because the caller frame will look // interpreted and arguments are now "compiled" so it is much better // to make this transition invisible to the stack walking // code. Unfortunately if we try and find the callee by normal means // a safepoint is possible. So we stash the desired callee in the // thread and the vm will find there should this case occur. __ std(R19_method, thread_(callee_target)); // Jump to the compiled code just as if compiled code was doing it. __ bctr(); } AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, int total_args_passed, int comp_args_on_stack, const BasicType *sig_bt, const VMRegPair *regs, AdapterFingerPrint* fingerprint) { address i2c_entry; address c2i_unverified_entry; address c2i_entry; // entry: i2c __ align(CodeEntryAlignment); i2c_entry = __ pc(); gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs); // entry: c2i unverified __ align(CodeEntryAlignment); BLOCK_COMMENT("c2i unverified entry"); c2i_unverified_entry = __ pc(); // inline_cache contains a compiledICHolder const Register ic = R19_method; const Register ic_klass = R11_scratch1; const Register receiver_klass = R12_scratch2; const Register code = R21_tmp1; const Register ientry = R23_tmp3; assert_different_registers(ic, ic_klass, receiver_klass, R3_ARG1, code, ientry); assert(R11_scratch1 == R11, "need prologue scratch register"); Label call_interpreter; assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes "klass offset should reach into any page"); // Check for NULL argument if we don't have implicit null checks. if (!ImplicitNullChecks || !os::zero_page_read_protected()) { if (TrapBasedNullChecks) { __ trap_null_check(R3_ARG1); } else { Label valid; __ cmpdi(CCR0, R3_ARG1, 0); __ bne_predict_taken(CCR0, valid); // We have a null argument, branch to ic_miss_stub. __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type); __ BIND(valid); } } // Assume argument is not NULL, load klass from receiver. __ load_klass(receiver_klass, R3_ARG1); __ ld(ic_klass, CompiledICHolder::holder_klass_offset(), ic); if (TrapBasedICMissChecks) { __ trap_ic_miss_check(receiver_klass, ic_klass); } else { Label valid; __ cmpd(CCR0, receiver_klass, ic_klass); __ beq_predict_taken(CCR0, valid); // We have an unexpected klass, branch to ic_miss_stub. __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type); __ BIND(valid); } // Argument is valid and klass is as expected, continue. // Extract method from inline cache, verified entry point needs it. __ ld(R19_method, CompiledICHolder::holder_metadata_offset(), ic); assert(R19_method == ic, "the inline cache register is dead here"); __ ld(code, method_(code)); __ cmpdi(CCR0, code, 0); __ ld(ientry, method_(interpreter_entry)); // preloaded __ beq_predict_taken(CCR0, call_interpreter); // Branch to ic_miss_stub. __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_ca // entry: c2i c2i_entry = __ pc(); // Class initialization barrier for static methods address c2i_no_clinit_check_entry = NULL; if (VM_Version::supports_fast_class_init_checks()) { Label L_skip_barrier; { // Bypass the barrier for non-static methods __ lwz(R0, in_bytes(Method::access_flags_offset()), R19_method); __ andi_(R0, R0, JVM_ACC_STATIC); __ beq(CCR0, L_skip_barrier); // non-static } Register klass = R11_scratch1; __ load_method_holder(klass, R19_method); __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/); __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0); __ mtctr(klass); __ bctr(); __ bind(L_skip_barrier); c2i_no_clinit_check_entry = __ pc(); } BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); bs->c2i_entry_barrier(masm, /* tmp register*/ ic_klass, /* tmp register*/ receiver_klass, gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, call_inter return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unver c2i_no_clinit_check_entry); } // An oop arg. Must pass a handle not the oop itself. static void object_move(MacroAssembler* masm, int frame_size_in_slots, OopMap* oop_map, int oop_handle_offset, bool is_receiver, int* receiver_offset, VMRegPair src, VMRegPair dst, Register r_caller_sp, Register r_temp_1, Register r_temp_2) { assert(!is_receiver || (is_receiver && (*receiver_offset == -1)), "receiver has already been moved"); // We must pass a handle. First figure out the location we use as a handle. if (src.first()->is_stack()) { // stack to stack or reg const Register r_handle = dst.first()->is_stack() ? r_temp_1 : dst.first()->as_Register(); Label skip; const int oop_slot_in_callers_frame = reg2slot(src.first()); guarantee(!is_receiver, "expecting receiver in register"); oop_map->set_oop(VMRegImpl::stack2reg(oop_slot_in_callers_frame + frame_size_in_slo __ addi(r_handle, r_caller_sp, reg2offset(src.first())); __ ld( r_temp_2, reg2offset(src.first()), r_caller_sp); __ cmpdi(CCR0, r_temp_2, 0); __ bne(CCR0, skip); // Use a NULL handle if oop is NULL. __ li(r_handle, 0); __ bind(skip); if (dst.first()->is_stack()) { // stack to stack __ std(r_handle, reg2offset(dst.first()), R1_SP); } else { // stack to reg // Nothing to do, r_handle is already the dst register. } } else { // reg to stack or reg const Register r_oop = src.first()->as_Register(); const Register r_handle = dst.first()->is_stack() ? r_temp_1 : dst.first()->as_Register(); const int oop_slot = (r_oop->encoding()-R3_ARG1->encoding()) * VMRegImpl::slots_per_word + oop_handle_offset; // in slots const int oop_offset = oop_slot * VMRegImpl::stack_slot_size; Label skip; if (is_receiver) { *receiver_offset = oop_offset; } oop_map->set_oop(VMRegImpl::stack2reg(oop_slot)); __ std( r_oop, oop_offset, R1_SP); __ addi(r_handle, R1_SP, oop_offset); __ cmpdi(CCR0, r_oop, 0); __ bne(CCR0, skip); // Use a NULL handle if oop is NULL. __ li(r_handle, 0); __ bind(skip); if (dst.first()->is_stack()) { // reg to stack __ std(r_handle, reg2offset(dst.first()), R1_SP); } else { // reg to reg // Nothing to do, r_handle is already the dst register. } } } static void int_move(MacroAssembler*masm, VMRegPair src, VMRegPair dst, Register r_caller_sp, Register r_temp) { assert(src.first()->is_valid(), "incoming must be int"); assert(dst.first()->is_valid() && dst.second() == dst.first()->next(), "outgoing must be if (src.first()->is_stack()) { if (dst.first()->is_stack()) { // stack to stack __ lwa(r_temp, reg2offset(src.first()), r_caller_sp); __ std(r_temp, reg2offset(dst.first()), R1_SP); } else { // stack to reg __ lwa(dst.first()->as_Register(), reg2offset(src.first()), r_caller_sp); } } else if (dst.first()->is_stack()) { // reg to stack __ extsw(r_temp, src.first()->as_Register()); __ std(r_temp, reg2offset(dst.first()), R1_SP); } else { // reg to reg __ extsw(dst.first()->as_Register(), src.first()->as_Register()); } } static void long_move(MacroAssembler*masm, VMRegPair src, VMRegPair dst, Register r_caller_sp, Register r_temp) { assert(src.first()->is_valid() && src.second() == src.first()->next(), "incoming must be assert(dst.first()->is_valid() && dst.second() == dst.first()->next(), "outgoing must be if (src.first()->is_stack()) { if (dst.first()->is_stack()) { // stack to stack __ ld( r_temp, reg2offset(src.first()), r_caller_sp); __ std(r_temp, reg2offset(dst.first()), R1_SP); } else { // stack to reg __ ld(dst.first()->as_Register(), reg2offset(src.first()), r_caller_sp); } } else if (dst.first()->is_stack()) { // reg to stack __ std(src.first()->as_Register(), reg2offset(dst.first()), R1_SP); } else { // reg to reg if (dst.first()->as_Register() != src.first()->as_Register()) __ mr(dst.first()->as_Register(), src.first()->as_Register()); } } static void float_move(MacroAssembler*masm, VMRegPair src, VMRegPair dst, Register r_caller_sp, Register r_temp) { assert(src.first()->is_valid() && !src.second()->is_valid(), "incoming must be float"); assert(dst.first()->is_valid() && !dst.second()->is_valid(), "outgoing must be float"); if (src.first()->is_stack()) { if (dst.first()->is_stack()) { // stack to stack __ lwz(r_temp, reg2offset(src.first()), r_caller_sp); __ stw(r_temp, reg2offset(dst.first()), R1_SP); } else { // stack to reg __ lfs(dst.first()->as_FloatRegister(), reg2offset(src.first()), r_caller_sp); } } else if (dst.first()->is_stack()) { // reg to stack __ stfs(src.first()->as_FloatRegister(), reg2offset(dst.first()), R1_SP); } else { // reg to reg if (dst.first()->as_FloatRegister() != src.first()->as_FloatRegister()) __ fmr(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister()); } } static void double_move(MacroAssembler*masm, VMRegPair src, VMRegPair dst, Register r_caller_sp, Register r_temp) { assert(src.first()->is_valid() && src.second() == src.first()->next(), "incoming must be assert(dst.first()->is_valid() && dst.second() == dst.first()->next(), "outgoing must be if (src.first()->is_stack()) { if (dst.first()->is_stack()) { // stack to stack __ ld( r_temp, reg2offset(src.first()), r_caller_sp); __ std(r_temp, reg2offset(dst.first()), R1_SP); } else { // stack to reg __ lfd(dst.first()->as_FloatRegister(), reg2offset(src.first()), r_caller_sp); } } else if (dst.first()->is_stack()) { // reg to stack __ stfd(src.first()->as_FloatRegister(), reg2offset(dst.first()), R1_SP); } else { // reg to reg if (dst.first()->as_FloatRegister() != src.first()->as_FloatRegister()) __ fmr(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister()); } } void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int f switch (ret_type) { case T_BOOLEAN: case T_CHAR: case T_BYTE: case T_SHORT: case T_INT: __ stw (R3_RET, frame_slots*VMRegImpl::stack_slot_size, R1_SP); break; case T_ARRAY: case T_OBJECT: case T_LONG: __ std (R3_RET, frame_slots*VMRegImpl::stack_slot_size, R1_SP); break; case T_FLOAT: __ stfs(F1_RET, frame_slots*VMRegImpl::stack_slot_size, R1_SP); break; case T_DOUBLE: __ stfd(F1_RET, frame_slots*VMRegImpl::stack_slot_size, R1_SP); break; case T_VOID: break; default: ShouldNotReachHere(); break; } } void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, i switch (ret_type) { case T_BOOLEAN: case T_CHAR: case T_BYTE: case T_SHORT: case T_INT: __ lwz(R3_RET, frame_slots*VMRegImpl::stack_slot_size, R1_SP); break; case T_ARRAY: case T_OBJECT: case T_LONG: __ ld (R3_RET, frame_slots*VMRegImpl::stack_slot_size, R1_SP); break; case T_FLOAT: __ lfs(F1_RET, frame_slots*VMRegImpl::stack_slot_size, R1_SP); break; case T_DOUBLE: __ lfd(F1_RET, frame_slots*VMRegImpl::stack_slot_size, R1_SP); break; case T_VOID: break; default: ShouldNotReachHere(); break; } } static void verify_oop_args(MacroAssembler* masm, const methodHandle& method, const BasicType* sig_bt, const VMRegPair* regs) { Register temp_reg = R19_method; // not part of any compiled calling seq if (VerifyOops) { for (int i = 0; i < method->size_of_parameters(); i++) { if (is_reference_type(sig_bt[i])) { VMReg r = regs[i].first(); assert(r->is_valid(), "bad oop arg"); if (r->is_stack()) { __ ld(temp_reg, reg2offset(r), R1_SP); __ verify_oop(temp_reg, FILE_AND_LINE); } else { __ verify_oop(r->as_Register(), FILE_AND_LINE); } } } } } static void gen_special_dispatch(MacroAssembler* masm, const methodHandle& method, const BasicType* sig_bt, const VMRegPair* regs) { verify_oop_args(masm, method, sig_bt, regs); vmIntrinsics::ID iid = method->intrinsic_id(); // Now write the args into the outgoing interpreter space bool has_receiver = false; Register receiver_reg = noreg; int member_arg_pos = -1; Register member_reg = noreg; int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); if (ref_kind != 0) { member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument member_reg = R19_method; // known to be free at this point has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); } else if (iid == vmIntrinsics::_invokeBasic) { has_receiver = true; } else if (iid == vmIntrinsics::_linkToNative) { member_arg_pos = method->size_of_parameters() - 1; // trailing NativeEntryPoint argument member_reg = R19_method; // known to be free at this point } else { fatal("unexpected intrinsic id %d", vmIntrinsics::as_int(iid)); } if (member_reg != noreg) { // Load the member_arg into register, if necessary. SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); VMReg r = regs[member_arg_pos].first(); if (r->is_stack()) { __ ld(member_reg, reg2offset(r), R1_SP); } else { // no data motion is needed member_reg = r->as_Register(); } } if (has_receiver) { // Make sure the receiver is loaded into a register. assert(method->size_of_parameters() > 0, "oob"); assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); VMReg r = regs[0].first(); assert(r->is_valid(), "bad receiver arg"); if (r->is_stack()) { // Porting note: This assumes that compiled calling conventions always // pass the receiver oop in a register. If this is not true on some // platform, pick a temp and load the receiver from stack. fatal("receiver always in a register"); receiver_reg = R11_scratch1; // TODO (hs24): is R11_scratch1 really free at this point? __ ld(receiver_reg, reg2offset(r), R1_SP); } else { // no data motion is needed receiver_reg = r->as_Register(); } } // Figure out which address we are really jumping to: MethodHandles::generate_method_handle_dispatch(masm, iid, receiver_reg, member_reg, /*for_compiler_entry:*/ true); } //---------------------------- continuation_enter_setup -------------------------- // // Frame setup. // // Arguments: // None. // // Results: // R1_SP: pointer to blank ContinuationEntry in the pushed frame. // // Kills: // R0, R20 // static OopMap* continuation_enter_setup(MacroAssembler* masm, int& framesize_word assert(ContinuationEntry::size() % VMRegImpl::stack_slot_size == 0, ""); assert(in_bytes(ContinuationEntry::cont_offset()) % VMRegImpl::stack_slot_size == 0, assert(in_bytes(ContinuationEntry::chunk_offset()) % VMRegImpl::stack_slot_size == 0 const int frame_size_in_bytes = (int)ContinuationEntry::size(); assert(is_aligned(frame_size_in_bytes, frame::alignment_in_bytes), "alignment erro framesize_words = frame_size_in_bytes / wordSize; DEBUG_ONLY(__ block_comment("setup {")); // Save return pc and push entry frame const Register return_pc = R20; __ mflr(return_pc); __ std(return_pc, _abi0(lr), R1_SP); // SP->lr = return_pc __ push_frame(frame_size_in_bytes , R0); // SP -= frame_size_in_bytes OopMap* map = new OopMap((int)frame_size_in_bytes / VMRegImpl::stack_slot_size, 0 /* arg_ __ ld_ptr(R0, JavaThread::cont_entry_offset(), R16_thread); __ st_ptr(R1_SP, JavaThread::cont_entry_offset(), R16_thread); __ st_ptr(R0, ContinuationEntry::parent_offset(), R1_SP); DEBUG_ONLY(__ block_comment("} setup")); return map; } //---------------------------- fill_continuation_entry --------------------------- // // Initialize the new ContinuationEntry. // // Arguments: // R1_SP: pointer to blank Continuation entry // reg_cont_obj: pointer to the continuation // reg_flags: flags // // Results: // R1_SP: pointer to filled out ContinuationEntry // // Kills: // R8_ARG6, R9_ARG7, R10_ARG8 // static void fill_continuation_entry(MacroAssembler* masm, Register reg_cont_obj, Regis assert_different_registers(reg_cont_obj, reg_flags); Register zero = R8_ARG6; Register tmp2 = R9_ARG7; Register tmp3 = R10_ARG8; DEBUG_ONLY(__ block_comment("fill {")); #ifdef ASSERT __ load_const_optimized(tmp2, ContinuationEntry::cookie_value()); __ stw(tmp2, in_bytes(ContinuationEntry::cookie_offset()), R1_SP); #endif //ASSERT __ li(zero, 0); __ st_ptr(reg_cont_obj, ContinuationEntry::cont_offset(), R1_SP); __ stw(reg_flags, in_bytes(ContinuationEntry::flags_offset()), R1_SP); __ st_ptr(zero, ContinuationEntry::chunk_offset(), R1_SP); __ stw(zero, in_bytes(ContinuationEntry::argsize_offset()), R1_SP); __ stw(zero, in_bytes(ContinuationEntry::pin_count_offset()), R1_SP); __ ld_ptr(tmp2, JavaThread::cont_fastpath_offset(), R16_thread); __ ld(tmp3, in_bytes(JavaThread::held_monitor_count_offset()), R16_thread); __ st_ptr(tmp2, ContinuationEntry::parent_cont_fastpath_offset(), R1_SP); __ std(tmp3, in_bytes(ContinuationEntry::parent_held_monitor_count_offset()), R1_SP __ st_ptr(zero, JavaThread::cont_fastpath_offset(), R16_thread); __ std(zero, in_bytes(JavaThread::held_monitor_count_offset()), R16_thread); DEBUG_ONLY(__ block_comment("} fill")); } //---------------------------- continuation_enter_cleanup ------------------------ // // Copy corresponding attributes from the top ContinuationEntry to the JavaThread // before deleting it. // // Arguments: // R1_SP: pointer to the ContinuationEntry // // Results: // None. // // Kills: // R8_ARG6, R9_ARG7, R10_ARG8 // static void continuation_enter_cleanup(MacroAssembler* masm) { Register tmp1 = R8_ARG6; Register tmp2 = R9_ARG7; Register tmp3 = R10_ARG8; #ifdef ASSERT __ block_comment("clean {"); __ ld_ptr(tmp1, JavaThread::cont_entry_offset(), R16_thread); __ cmpd(CCR0, R1_SP, tmp1); __ asm_assert_eq(FILE_AND_LINE ": incorrect R1_SP"); #endif __ ld_ptr(tmp1, ContinuationEntry::parent_cont_fastpath_offset(), R1_SP); __ ld(tmp2, in_bytes(ContinuationEntry::parent_held_monitor_count_offset()), R1_SP) __ ld_ptr(tmp3, ContinuationEntry::parent_offset(), R1_SP); __ st_ptr(tmp1, JavaThread::cont_fastpath_offset(), R16_thread); __ std(tmp2, in_bytes(JavaThread::held_monitor_count_offset()), R16_thread); __ st_ptr(tmp3, JavaThread::cont_entry_offset(), R16_thread); DEBUG_ONLY(__ block_comment("} clean")); } static void check_continuation_enter_argument(VMReg actual_vmreg, Register expected_reg, const char* name) { assert(!actual_vmreg->is_stack(), "%s cannot be on stack", name); assert(actual_vmreg->as_Register() == expected_reg, "%s is in unexpected register: %s instead of %s", name, actual_vmreg->as_Register()->name(), expected_reg->name()); } static void gen_continuation_enter(MacroAssembler* masm, const VMRegPair* regs, int& exception_offset, OopMapSet* oop_maps, int& frame_complete, int& framesize_words, int& interpreted_entry_offset, int& compiled_entry_offset) { // enterSpecial(Continuation c, boolean isContinue, boolean isVirtualThread) int pos_cont_obj = 0; int pos_is_cont = 1; int pos_is_virtual = 2; // The platform-specific calling convention may present the arguments in various registers. // To simplify the rest of the code, we expect the arguments to reside at these known // registers, and we additionally check the placement here in case calling convention ever // changes. Register reg_cont_obj = R3_ARG1; Register reg_is_cont = R4_ARG2; Register reg_is_virtual = R5_ARG3; check_continuation_enter_argument(regs[pos_cont_obj].first(), reg_cont_obj, "Conti check_continuation_enter_argument(regs[pos_is_cont].first(), reg_is_cont, "isConti check_continuation_enter_argument(regs[pos_is_virtual].first(), reg_is_virtual, "i address resolve_static_call = SharedRuntime::get_resolve_static_call_stub(); address start = __ pc(); Label L_thaw, L_exit; // i2i entry used at interp_only_mode only interpreted_entry_offset = __ pc() - start; { #ifdef ASSERT Label is_interp_only; __ lwz(R0, in_bytes(JavaThread::interp_only_mode_offset()), R16_thread); __ cmpwi(CCR0, R0, 0); __ bne(CCR0, is_interp_only); __ stop("enterSpecial interpreter entry called when not in interp_only_mode"); __ bind(is_interp_only); #endif // Read interpreter arguments into registers (this is an ad-hoc i2c adapter) __ ld(reg_cont_obj, Interpreter::stackElementSize*3, R15_esp); __ lwz(reg_is_cont, Interpreter::stackElementSize*2, R15_esp); __ lwz(reg_is_virtual, Interpreter::stackElementSize*1, R15_esp); __ push_cont_fastpath(); OopMap* map = continuation_enter_setup(masm, framesize_words); // The frame is complete here, but we only record it for the compiled entry, so the frame would app // but that's okay because at the very worst we'll miss an async sample, but we're in interp_only fill_continuation_entry(masm, reg_cont_obj, reg_is_virtual); --> -------------------- --> maximum size reached --> -------------------- ¤ Dauer der Verarbeitung: 0.39 Sekunden (vorverarbeitet) ¤ |
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