| products/sources/formale sprachen/Java/openjdk-20-36_src/test/hotspot/gtest/aarch64/ |
|
Quellcode-Bibliothek© Kompilation durch diese Firma[Weder Korrektheit noch Funktionsfähigkeit der Software werden zugesichert.]Datei: Sprache: C |
|
||||||
|
// BEGIN Generated code -- do not edit
// Generated by aarch64-asmtest.py Label back, forth; __ bind(back); // ArithOp __ add(r26, r23, r13, Assembler::LSL, 32); // add x26, x23, x13, LSL #32 __ sub(r12, r24, r9, Assembler::LSR, 37); // sub x12, x24, x9, LSR #37 __ adds(r28, r15, r8, Assembler::ASR, 39); // adds x28, x15, x8, ASR #39 __ subs(r7, r28, r30, Assembler::ASR, 57); // subs x7, x28, x30, ASR #57 __ addw(r9, r22, r27, Assembler::ASR, 15); // add w9, w22, w27, ASR #15 __ subw(r3, r13, r17, Assembler::ASR, 30); // sub w3, w13, w17, ASR #30 __ addsw(r14, r26, r8, Assembler::ASR, 17); // adds w14, w26, w8, ASR #17 __ subsw(r0, r22, r12, Assembler::ASR, 21); // subs w0, w22, w12, ASR #21 __ andr(r0, r15, r26, Assembler::LSL, 20); // and x0, x15, x26, LSL #20 __ orr(r26, r5, r17, Assembler::LSL, 61); // orr x26, x5, x17, LSL #61 __ eor(r24, r13, r2, Assembler::LSL, 32); // eor x24, x13, x2, LSL #32 __ ands(r28, r3, r17, Assembler::ASR, 35); // ands x28, x3, x17, ASR #35 __ andw(r25, r16, r29, Assembler::LSR, 18); // and w25, w16, w29, LSR #18 __ orrw(r13, r17, r11, Assembler::LSR, 9); // orr w13, w17, w11, LSR #9 __ eorw(r5, r5, r17, Assembler::LSR, 15); // eor w5, w5, w17, LSR #15 __ andsw(r2, r23, r27, Assembler::ASR, 26); // ands w2, w23, w27, ASR #26 __ bic(r27, r28, r16, Assembler::LSR, 45); // bic x27, x28, x16, LSR #45 __ orn(r8, r25, r26, Assembler::ASR, 37); // orn x8, x25, x26, ASR #37 __ eon(r29, r17, r13, Assembler::LSR, 63); // eon x29, x17, x13, LSR #63 __ bics(r28, r24, r2, Assembler::LSR, 31); // bics x28, x24, x2, LSR #31 __ bicw(r19, r26, r7, Assembler::ASR, 3); // bic w19, w26, w7, ASR #3 __ ornw(r6, r24, r10, Assembler::ASR, 3); // orn w6, w24, w10, ASR #3 __ eonw(r4, r21, r1, Assembler::LSR, 29); // eon w4, w21, w1, LSR #29 __ bicsw(r16, r21, r0, Assembler::LSR, 19); // bics w16, w21, w0, LSR #19 // AddSubImmOp __ addw(r17, r12, 379u); // add w17, w12, #379 __ addsw(r30, r1, 22u); // adds w30, w1, #22 __ subw(r29, r5, 126u); // sub w29, w5, #126 __ subsw(r6, r24, 960u); // subs w6, w24, #960 __ add(r0, r13, 104u); // add x0, x13, #104 __ adds(r8, r6, 663u); // adds x8, x6, #663 __ sub(r10, r5, 516u); // sub x10, x5, #516 __ subs(r1, r3, 1012u); // subs x1, x3, #1012 // LogicalImmOp __ andw(r6, r11, 4294049777ull); // and w6, w11, #0xfff1fff1 __ orrw(r28, r5, 4294966791ull); // orr w28, w5, #0xfffffe07 __ eorw(r1, r20, 134217216ull); // eor w1, w20, #0x7fffe00 __ andsw(r7, r17, 1048576ull); // ands w7, w17, #0x100000 __ andr(r14, r12, 9223372036854775808ull); // and x14, x12, #0x8000000000000000 __ orr(r9, r11, 562675075514368ull); // orr x9, x11, #0x1ffc000000000 __ eor(r17, r0, 18014398509481728ull); // eor x17, x0, #0x3fffffffffff00 __ ands(r1, r8, 18446744073705357315ull); // ands x1, x8, #0xffffffffffc00003 // AbsOp __ b(__ pc()); // b . __ b(back); // b back __ b(forth); // b forth __ bl(__ pc()); // bl . __ bl(back); // bl back __ bl(forth); // bl forth // RegAndAbsOp __ cbzw(r10, __ pc()); // cbz w10, . __ cbzw(r10, back); // cbz w10, back __ cbzw(r10, forth); // cbz w10, forth __ cbnzw(r8, __ pc()); // cbnz w8, . __ cbnzw(r8, back); // cbnz w8, back __ cbnzw(r8, forth); // cbnz w8, forth __ cbz(r11, __ pc()); // cbz x11, . __ cbz(r11, back); // cbz x11, back __ cbz(r11, forth); // cbz x11, forth __ cbnz(r29, __ pc()); // cbnz x29, . __ cbnz(r29, back); // cbnz x29, back __ cbnz(r29, forth); // cbnz x29, forth __ adr(r19, __ pc()); // adr x19, . __ adr(r19, back); // adr x19, back __ adr(r19, forth); // adr x19, forth __ _adrp(r19, __ pc()); // adrp x19, . // RegImmAbsOp __ tbz(r22, 6, __ pc()); // tbz x22, #6, . __ tbz(r22, 6, back); // tbz x22, #6, back __ tbz(r22, 6, forth); // tbz x22, #6, forth __ tbnz(r12, 11, __ pc()); // tbnz x12, #11, . __ tbnz(r12, 11, back); // tbnz x12, #11, back __ tbnz(r12, 11, forth); // tbnz x12, #11, forth // MoveWideImmOp __ movnw(r0, 6301, 0); // movn w0, #6301, lsl 0 __ movzw(r7, 20886, 0); // movz w7, #20886, lsl 0 __ movkw(r27, 18617, 0); // movk w27, #18617, lsl 0 __ movn(r12, 22998, 16); // movn x12, #22998, lsl 16 __ movz(r20, 1532, 16); // movz x20, #1532, lsl 16 __ movk(r8, 5167, 32); // movk x8, #5167, lsl 32 // BitfieldOp __ sbfm(r15, r17, 24, 28); // sbfm x15, x17, #24, #28 __ bfmw(r15, r9, 14, 25); // bfm w15, w9, #14, #25 __ ubfmw(r27, r25, 6, 31); // ubfm w27, w25, #6, #31 __ sbfm(r19, r2, 23, 31); // sbfm x19, x2, #23, #31 __ bfm(r12, r21, 10, 6); // bfm x12, x21, #10, #6 __ ubfm(r22, r0, 26, 16); // ubfm x22, x0, #26, #16 // ExtractOp __ extrw(r3, r3, r20, 27); // extr w3, w3, w20, #27 __ extr(r8, r30, r3, 54); // extr x8, x30, x3, #54 // CondBranchOp __ br(Assembler::EQ, __ pc()); // b.EQ . __ br(Assembler::EQ, back); // b.EQ back __ br(Assembler::EQ, forth); // b.EQ forth __ br(Assembler::NE, __ pc()); // b.NE . __ br(Assembler::NE, back); // b.NE back __ br(Assembler::NE, forth); // b.NE forth __ br(Assembler::HS, __ pc()); // b.HS . __ br(Assembler::HS, back); // b.HS back __ br(Assembler::HS, forth); // b.HS forth __ br(Assembler::CS, __ pc()); // b.CS . __ br(Assembler::CS, back); // b.CS back __ br(Assembler::CS, forth); // b.CS forth __ br(Assembler::LO, __ pc()); // b.LO . __ br(Assembler::LO, back); // b.LO back __ br(Assembler::LO, forth); // b.LO forth __ br(Assembler::CC, __ pc()); // b.CC . __ br(Assembler::CC, back); // b.CC back __ br(Assembler::CC, forth); // b.CC forth __ br(Assembler::MI, __ pc()); // b.MI . __ br(Assembler::MI, back); // b.MI back __ br(Assembler::MI, forth); // b.MI forth __ br(Assembler::PL, __ pc()); // b.PL . __ br(Assembler::PL, back); // b.PL back __ br(Assembler::PL, forth); // b.PL forth __ br(Assembler::VS, __ pc()); // b.VS . __ br(Assembler::VS, back); // b.VS back __ br(Assembler::VS, forth); // b.VS forth __ br(Assembler::VC, __ pc()); // b.VC . __ br(Assembler::VC, back); // b.VC back __ br(Assembler::VC, forth); // b.VC forth __ br(Assembler::HI, __ pc()); // b.HI . __ br(Assembler::HI, back); // b.HI back __ br(Assembler::HI, forth); // b.HI forth __ br(Assembler::LS, __ pc()); // b.LS . __ br(Assembler::LS, back); // b.LS back __ br(Assembler::LS, forth); // b.LS forth __ br(Assembler::GE, __ pc()); // b.GE . __ br(Assembler::GE, back); // b.GE back __ br(Assembler::GE, forth); // b.GE forth __ br(Assembler::LT, __ pc()); // b.LT . __ br(Assembler::LT, back); // b.LT back __ br(Assembler::LT, forth); // b.LT forth __ br(Assembler::GT, __ pc()); // b.GT . __ br(Assembler::GT, back); // b.GT back __ br(Assembler::GT, forth); // b.GT forth __ br(Assembler::LE, __ pc()); // b.LE . __ br(Assembler::LE, back); // b.LE back __ br(Assembler::LE, forth); // b.LE forth __ br(Assembler::AL, __ pc()); // b.AL . __ br(Assembler::AL, back); // b.AL back __ br(Assembler::AL, forth); // b.AL forth __ br(Assembler::NV, __ pc()); // b.NV . __ br(Assembler::NV, back); // b.NV back __ br(Assembler::NV, forth); // b.NV forth // ImmOp __ svc(12999); // svc #12999 __ hvc(2665); // hvc #2665 __ smc(9002); // smc #9002 __ brk(14843); // brk #14843 __ hlt(25964); // hlt #25964 // Op __ nop(); // nop __ yield(); // yield __ wfe(); // wfe __ sev(); // sev __ sevl(); // sevl __ autia1716(); // autia1716 __ autiasp(); // autiasp __ autiaz(); // autiaz __ autib1716(); // autib1716 __ autibsp(); // autibsp __ autibz(); // autibz __ pacia1716(); // pacia1716 __ paciasp(); // paciasp __ paciaz(); // paciaz __ pacib1716(); // pacib1716 __ pacibsp(); // pacibsp __ pacibz(); // pacibz __ eret(); // eret __ drps(); // drps __ isb(); // isb // PostfixExceptionOp __ wfi(); // wfi __ xpaclri(); // xpaclri // SystemOp __ dsb(Assembler::ST); // dsb ST __ dmb(Assembler::OSHST); // dmb OSHST // OneRegOp __ br(r16); // br x16 __ blr(r20); // blr x20 __ paciza(r10); // paciza x10 __ pacizb(r27); // pacizb x27 __ pacdza(r8); // pacdza x8 __ pacdzb(r0); // pacdzb x0 __ autiza(r1); // autiza x1 __ autizb(r21); // autizb x21 __ autdza(r17); // autdza x17 __ autdzb(r29); // autdzb x29 __ xpacd(r29); // xpacd x29 __ braaz(r28); // braaz x28 __ brabz(r1); // brabz x1 __ blraaz(r23); // blraaz x23 __ blrabz(r21); // blrabz x21 // PostfixExceptionOneRegOp __ xpaci(r20); // xpaci x20 // LoadStoreExclusiveOp __ stxr(r22, r27, r19); // stxr w22, x27, [x19] __ stlxr(r11, r16, r6); // stlxr w11, x16, [x6] __ ldxr(r17, r0); // ldxr x17, [x0] __ ldaxr(r4, r10); // ldaxr x4, [x10] __ stlr(r24, r22); // stlr x24, [x22] __ ldar(r10, r19); // ldar x10, [x19] // LoadStoreExclusiveOp __ stxrw(r1, r5, r30); // stxr w1, w5, [x30] __ stlxrw(r8, r12, r17); // stlxr w8, w12, [x17] __ ldxrw(r9, r14); // ldxr w9, [x14] __ ldaxrw(r7, r1); // ldaxr w7, [x1] __ stlrw(r5, r16); // stlr w5, [x16] __ ldarw(r2, r12); // ldar w2, [x12] // LoadStoreExclusiveOp __ stxrh(r10, r12, r3); // stxrh w10, w12, [x3] __ stlxrh(r28, r14, r26); // stlxrh w28, w14, [x26] __ ldxrh(r30, r10); // ldxrh w30, [x10] __ ldaxrh(r14, r21); // ldaxrh w14, [x21] __ stlrh(r13, r9); // stlrh w13, [x9] __ ldarh(r22, r27); // ldarh w22, [x27] // LoadStoreExclusiveOp __ stxrb(r28, r19, r11); // stxrb w28, w19, [x11] __ stlxrb(r30, r19, r2); // stlxrb w30, w19, [x2] __ ldxrb(r2, r23); // ldxrb w2, [x23] __ ldaxrb(r1, r0); // ldaxrb w1, [x0] __ stlrb(r12, r16); // stlrb w12, [x16] __ ldarb(r13, r15); // ldarb w13, [x15] // LoadStoreExclusiveOp __ ldxp(r17, r21, r13); // ldxp x17, x21, [x13] __ ldaxp(r11, r30, r8); // ldaxp x11, x30, [x8] __ stxp(r24, r13, r11, r1); // stxp w24, x13, x11, [x1] __ stlxp(r26, r21, r27, r13); // stlxp w26, x21, x27, [x13] // LoadStoreExclusiveOp __ ldxpw(r20, r3, r12); // ldxp w20, w3, [x12] __ ldaxpw(r6, r1, r29); // ldaxp w6, w1, [x29] __ stxpw(r6, r4, r11, r16); // stxp w6, w4, w11, [x16] __ stlxpw(r4, r30, r12, r21); // stlxp w4, w30, w12, [x21] // base_plus_unscaled_offset // LoadStoreOp __ str(r6, Address(r27, 97)); // str x6, [x27, 97] __ strw(r17, Address(r10, 45)); // str w17, [x10, 45] __ strb(r26, Address(r22, -29)); // strb w26, [x22, -29] __ strh(r21, Address(r10, -50)); // strh w21, [x10, -50] __ ldr(r14, Address(r24, 125)); // ldr x14, [x24, 125] __ ldrw(r7, Address(r24, -16)); // ldr w7, [x24, -16] __ ldrb(r8, Address(r2, 13)); // ldrb w8, [x2, 13] __ ldrh(r30, Address(r25, -61)); // ldrh w30, [x25, -61] __ ldrsb(r3, Address(r12, -14)); // ldrsb x3, [x12, -14] __ ldrsh(r10, Address(r17, -28)); // ldrsh x10, [x17, -28] __ ldrshw(r21, Address(r3, -5)); // ldrsh w21, [x3, -5] __ ldrsw(r2, Address(r25, 23)); // ldrsw x2, [x25, 23] __ ldrd(v25, Address(r1, -69)); // ldr d25, [x1, -69] __ ldrs(v29, Address(r27, 6)); // ldr s29, [x27, 6] __ strd(v29, Address(r12, 41)); // str d29, [x12, 41] __ strs(v2, Address(r22, -115)); // str s2, [x22, -115] // pre // LoadStoreOp __ str(r26, Address(__ pre(r5, 3))); // str x26, [x5, 3]! __ strw(r20, Address(__ pre(r5, -103))); // str w20, [x5, -103]! __ strb(r8, Address(__ pre(r12, -25))); // strb w8, [x12, -25]! __ strh(r20, Address(__ pre(r2, -57))); // strh w20, [x2, -57]! __ ldr(r14, Address(__ pre(r29, -234))); // ldr x14, [x29, -234]! __ ldrw(r13, Address(__ pre(r29, 4))); // ldr w13, [x29, 4]! __ ldrb(r24, Address(__ pre(r19, -9))); // ldrb w24, [x19, -9]! __ ldrh(r3, Address(__ pre(r27, -19))); // ldrh w3, [x27, -19]! __ ldrsb(r17, Address(__ pre(r1, -5))); // ldrsb x17, [x1, -5]! __ ldrsh(r17, Address(__ pre(r19, -13))); // ldrsh x17, [x19, -13]! __ ldrshw(r21, Address(__ pre(r11, -26))); // ldrsh w21, [x11, -26]! __ ldrsw(r1, Address(__ pre(r9, -60))); // ldrsw x1, [x9, -60]! __ ldrd(v26, Address(__ pre(r23, -247))); // ldr d26, [x23, -247]! __ ldrs(v22, Address(__ pre(r21, -127))); // ldr s22, [x21, -127]! __ strd(v13, Address(__ pre(r7, -216))); // str d13, [x7, -216]! __ strs(v12, Address(__ pre(r13, -104))); // str s12, [x13, -104]! // post // LoadStoreOp __ str(r20, Address(__ post(r5, -237))); // str x20, [x5], -237 __ strw(r29, Address(__ post(r28, -74))); // str w29, [x28], -74 __ strb(r4, Address(__ post(r24, -22))); // strb w4, [x24], -22 __ strh(r13, Address(__ post(r9, -21))); // strh w13, [x9], -21 __ ldr(r26, Address(__ post(r7, -55))); // ldr x26, [x7], -55 __ ldrw(r13, Address(__ post(r3, -115))); // ldr w13, [x3], -115 __ ldrb(r1, Address(__ post(r5, 12))); // ldrb w1, [x5], 12 __ ldrh(r8, Address(__ post(r13, -34))); // ldrh w8, [x13], -34 __ ldrsb(r23, Address(__ post(r20, -27))); // ldrsb x23, [x20], -27 __ ldrsh(r20, Address(__ post(r6, -2))); // ldrsh x20, [x6], -2 __ ldrshw(r9, Address(__ post(r17, -42))); // ldrsh w9, [x17], -42 __ ldrsw(r21, Address(__ post(r6, -30))); // ldrsw x21, [x6], -30 __ ldrd(v16, Address(__ post(r22, -29))); // ldr d16, [x22], -29 __ ldrs(v9, Address(__ post(r11, -3))); // ldr s9, [x11], -3 __ strd(v22, Address(__ post(r26, 60))); // str d22, [x26], 60 __ strs(v16, Address(__ post(r29, -2))); // str s16, [x29], -2 // base_plus_reg // LoadStoreOp __ str(r1, Address(r22, r4, Address::sxtw(0))); // str x1, [x22, w4, sxtw #0] __ strw(r23, Address(r30, r13, Address::lsl(2))); // str w23, [x30, x13, lsl #2] __ strb(r12, Address(r11, r12, Address::uxtw(0))); // strb w12, [x11, w12, uxtw #0] __ strh(r25, Address(r12, r0, Address::lsl(1))); // strh w25, [x12, x0, lsl #1] __ ldr(r17, Address(r7, r0, Address::uxtw(3))); // ldr x17, [x7, w0, uxtw #3] __ ldrw(r1, Address(r19, r14, Address::uxtw(2))); // ldr w1, [x19, w14, uxtw #2] __ ldrb(r12, Address(r2, r9, Address::lsl(0))); // ldrb w12, [x2, x9, lsl #0] __ ldrh(r22, Address(r9, r27, Address::sxtw(0))); // ldrh w22, [x9, w27, sxtw #0] __ ldrsb(r21, Address(r12, r15, Address::sxtx(0))); // ldrsb x21, [x12, x15, sxtx #0] __ ldrsh(r28, Address(r6, r16, Address::lsl(1))); // ldrsh x28, [x6, x16, lsl #1] __ ldrshw(r25, Address(r17, r22, Address::sxtw(0))); // ldrsh w25, [x17, w22, sxtw #0] __ ldrsw(r4, Address(r17, r29, Address::sxtx(0))); // ldrsw x4, [x17, x29, sxtx #0] __ ldrd(v5, Address(r1, r3, Address::sxtx(3))); // ldr d5, [x1, x3, sxtx #3] __ ldrs(v24, Address(r17, r13, Address::uxtw(2))); // ldr s24, [x17, w13, uxtw #2] __ strd(v17, Address(r17, r23, Address::sxtx(3))); // str d17, [x17, x23, sxtx #3] __ strs(v17, Address(r30, r5, Address::sxtw(2))); // str s17, [x30, w5, sxtw #2] // base_plus_scaled_offset // LoadStoreOp __ str(r29, Address(r11, 14160)); // str x29, [x11, 14160] __ strw(r28, Address(r21, 7752)); // str w28, [x21, 7752] __ strb(r28, Address(r2, 1746)); // strb w28, [x2, 1746] __ strh(r0, Address(r28, 3296)); // strh w0, [x28, 3296] __ ldr(r25, Address(r7, 15408)); // ldr x25, [x7, 15408] __ ldrw(r0, Address(r3, 6312)); // ldr w0, [x3, 6312] __ ldrb(r30, Address(r5, 1992)); // ldrb w30, [x5, 1992] __ ldrh(r14, Address(r23, 3194)); // ldrh w14, [x23, 3194] __ ldrsb(r10, Address(r19, 1786)); // ldrsb x10, [x19, 1786] __ ldrsh(r29, Address(r17, 3482)); // ldrsh x29, [x17, 3482] __ ldrshw(r25, Address(r30, 3362)); // ldrsh w25, [x30, 3362] __ ldrsw(r17, Address(r2, 7512)); // ldrsw x17, [x2, 7512] __ ldrd(v15, Address(r16, 15176)); // ldr d15, [x16, 15176] __ ldrs(v12, Address(r30, 6220)); // ldr s12, [x30, 6220] __ strd(v1, Address(r1, 15216)); // str d1, [x1, 15216] __ strs(v5, Address(r11, 7832)); // str s5, [x11, 7832] // pcrel // LoadStoreOp __ ldr(r17, back); // ldr x17, back __ ldrw(r2, back); // ldr w2, back // LoadStoreOp __ prfm(Address(r25, 111)); // prfm PLDL1KEEP, [x25, 111] // LoadStoreOp __ prfm(back); // prfm PLDL1KEEP, back // LoadStoreOp __ prfm(Address(r14, r27, Address::uxtw(0))); // prfm PLDL1KEEP, [x14, w27, uxtw #0] // LoadStoreOp __ prfm(Address(r14, 12328)); // prfm PLDL1KEEP, [x14, 12328] // AddSubCarryOp __ adcw(r0, r25, r15); // adc w0, w25, w15 __ adcsw(r1, r24, r3); // adcs w1, w24, w3 __ sbcw(r17, r24, r20); // sbc w17, w24, w20 __ sbcsw(r11, r0, r13); // sbcs w11, w0, w13 __ adc(r28, r10, r7); // adc x28, x10, x7 __ adcs(r4, r15, r16); // adcs x4, x15, x16 __ sbc(r2, r12, r20); // sbc x2, x12, x20 __ sbcs(r29, r13, r13); // sbcs x29, x13, x13 // AddSubExtendedOp __ addw(r14, r6, r12, ext::uxtx, 3); // add w14, w6, w12, uxtx #3 __ addsw(r17, r25, r30, ext::uxtw, 4); // adds w17, w25, w30, uxtw #4 __ sub(r0, r17, r14, ext::uxtb, 1); // sub x0, x17, x14, uxtb #1 __ subsw(r9, r24, r29, ext::sxtx, 1); // subs w9, w24, w29, sxtx #1 __ add(r1, r22, r0, ext::sxtw, 2); // add x1, x22, x0, sxtw #2 __ adds(r12, r28, r22, ext::uxth, 3); // adds x12, x28, x22, uxth #3 __ sub(r10, r12, r17, ext::uxtw, 4); // sub x10, x12, x17, uxtw #4 __ subs(r15, r28, r10, ext::sxtw, 3); // subs x15, x28, x10, sxtw #3 // ConditionalCompareOp __ ccmnw(r19, r23, 2u, Assembler::LE); // ccmn w19, w23, #2, LE __ ccmpw(r17, r9, 6u, Assembler::LO); // ccmp w17, w9, #6, LO __ ccmn(r21, r8, 2u, Assembler::CC); // ccmn x21, x8, #2, CC __ ccmp(r19, r5, 1u, Assembler::MI); // ccmp x19, x5, #1, MI // ConditionalCompareImmedOp __ ccmnw(r22, 17, 12, Assembler::HI); // ccmn w22, #17, #12, HI __ ccmpw(r17, 7, 3, Assembler::HS); // ccmp w17, #7, #3, HS __ ccmn(r16, 28, 5, Assembler::LT); // ccmn x16, #28, #5, LT __ ccmp(r22, 3, 5, Assembler::LS); // ccmp x22, #3, #5, LS // ConditionalSelectOp __ cselw(r29, r26, r12, Assembler::LT); // csel w29, w26, w12, LT __ csincw(r27, r10, r15, Assembler::CC); // csinc w27, w10, w15, CC __ csinvw(r21, r28, r30, Assembler::LS); // csinv w21, w28, w30, LS __ csnegw(r9, r27, r30, Assembler::CC); // csneg w9, w27, w30, CC __ csel(r29, r15, r29, Assembler::LE); // csel x29, x15, x29, LE __ csinc(r25, r21, r4, Assembler::EQ); // csinc x25, x21, x4, EQ __ csinv(r17, r21, r29, Assembler::VS); // csinv x17, x21, x29, VS __ csneg(r21, r20, r6, Assembler::HI); // csneg x21, x20, x6, HI // TwoRegOp __ rbitw(r30, r3); // rbit w30, w3 __ rev16w(r21, r19); // rev16 w21, w19 __ revw(r11, r24); // rev w11, w24 __ clzw(r0, r27); // clz w0, w27 __ clsw(r25, r14); // cls w25, w14 __ rbit(r3, r14); // rbit x3, x14 __ rev16(r17, r7); // rev16 x17, x7 __ rev32(r15, r24); // rev32 x15, x24 __ rev(r28, r17); // rev x28, x17 __ clz(r25, r2); // clz x25, x2 __ cls(r26, r28); // cls x26, x28 __ pacia(r5, r25); // pacia x5, x25 __ pacib(r26, r27); // pacib x26, x27 __ pacda(r16, r17); // pacda x16, x17 __ pacdb(r6, r21); // pacdb x6, x21 __ autia(r12, r0); // autia x12, x0 __ autib(r4, r12); // autib x4, x12 __ autda(r27, r17); // autda x27, x17 __ autdb(r28, r28); // autdb x28, x28 __ braa(r2, r17); // braa x2, x17 __ brab(r10, r15); // brab x10, x15 __ blraa(r14, r14); // blraa x14, x14 __ blrab(r3, r25); // blrab x3, x25 // ThreeRegOp __ udivw(r15, r19, r14); // udiv w15, w19, w14 __ sdivw(r5, r16, r4); // sdiv w5, w16, w4 __ lslvw(r26, r25, r4); // lslv w26, w25, w4 __ lsrvw(r2, r2, r12); // lsrv w2, w2, w12 __ asrvw(r29, r17, r8); // asrv w29, w17, w8 __ rorvw(r7, r3, r4); // rorv w7, w3, w4 __ udiv(r25, r4, r26); // udiv x25, x4, x26 __ sdiv(r25, r4, r17); // sdiv x25, x4, x17 __ lslv(r0, r26, r17); // lslv x0, x26, x17 __ lsrv(r23, r15, r21); // lsrv x23, x15, x21 __ asrv(r28, r17, r27); // asrv x28, x17, x27 __ rorv(r10, r3, r0); // rorv x10, x3, x0 __ umulh(r7, r25, r9); // umulh x7, x25, x9 __ smulh(r6, r15, r29); // smulh x6, x15, x29 // FourRegMulOp __ maddw(r15, r10, r2, r17); // madd w15, w10, w2, w17 __ msubw(r7, r11, r11, r23); // msub w7, w11, w11, w23 __ madd(r7, r29, r23, r14); // madd x7, x29, x23, x14 __ msub(r27, r11, r11, r4); // msub x27, x11, x11, x4 __ smaddl(r24, r12, r15, r14); // smaddl x24, w12, w15, x14 __ smsubl(r20, r11, r28, r13); // smsubl x20, w11, w28, x13 __ umaddl(r11, r12, r23, r30); // umaddl x11, w12, w23, x30 __ umsubl(r26, r14, r9, r13); // umsubl x26, w14, w9, x13 // ThreeRegFloatOp __ fabds(v10, v7, v5); // fabd s10, s7, s5 __ fmuls(v29, v15, v3); // fmul s29, s15, s3 __ fdivs(v11, v12, v15); // fdiv s11, s12, s15 __ fadds(v30, v30, v17); // fadd s30, s30, s17 __ fsubs(v19, v20, v15); // fsub s19, s20, s15 __ fabdd(v15, v9, v21); // fabd d15, d9, d21 __ fmuld(v2, v9, v27); // fmul d2, d9, d27 __ fdivd(v7, v29, v30); // fdiv d7, d29, d30 __ faddd(v17, v1, v2); // fadd d17, d1, d2 __ fsubd(v6, v10, v3); // fsub d6, d10, d3 // FourRegFloatOp __ fmadds(v24, v11, v7, v1); // fmadd s24, s11, s7, s1 __ fmsubs(v11, v0, v3, v17); // fmsub s11, s0, s3, s17 __ fnmadds(v28, v6, v22, v6); // fnmadd s28, s6, s22, s6 __ fnmadds(v0, v27, v26, v2); // fnmadd s0, s27, s26, s2 __ fmaddd(v5, v7, v28, v11); // fmadd d5, d7, d28, d11 __ fmsubd(v25, v13, v11, v23); // fmsub d25, d13, d11, d23 __ fnmaddd(v19, v8, v17, v21); // fnmadd d19, d8, d17, d21 __ fnmaddd(v25, v20, v19, v17); // fnmadd d25, d20, d19, d17 // TwoRegFloatOp __ fmovs(v2, v29); // fmov s2, s29 __ fabss(v22, v8); // fabs s22, s8 __ fnegs(v21, v19); // fneg s21, s19 __ fsqrts(v20, v11); // fsqrt s20, s11 __ fcvts(v17, v20); // fcvt d17, s20 __ fcvtsh(v6, v15); // fcvt h6, s15 __ fcvths(v3, v3); // fcvt s3, h3 __ fmovd(v28, v3); // fmov d28, d3 __ fabsd(v27, v14); // fabs d27, d14 __ fnegd(v14, v10); // fneg d14, d10 __ fsqrtd(v12, v11); // fsqrt d12, d11 __ fcvtd(v17, v10); // fcvt s17, d10 // FloatConvertOp __ fcvtzsw(r25, v7); // fcvtzs w25, s7 __ fcvtzs(r7, v14); // fcvtzs x7, s14 __ fcvtzdw(r28, v0); // fcvtzs w28, d0 __ fcvtzd(r22, v0); // fcvtzs x22, d0 __ scvtfws(v12, r23); // scvtf s12, w23 __ scvtfs(v13, r13); // scvtf s13, x13 __ scvtfwd(v7, r14); // scvtf d7, w14 __ scvtfd(v7, r8); // scvtf d7, x8 __ fcvtassw(r20, v17); // fcvtas w20, s17 __ fcvtasd(r28, v30); // fcvtas x28, d30 __ fcvtmssw(r16, v2); // fcvtms w16, s2 __ fcvtmsd(r9, v16); // fcvtms x9, d16 __ fmovs(r20, v29); // fmov w20, s29 __ fmovd(r4, v1); // fmov x4, d1 __ fmovs(v26, r24); // fmov s26, w24 __ fmovd(v23, r14); // fmov d23, x14 // TwoRegFloatOp __ fcmps(v21, v12); // fcmp s21, s12 __ fcmpd(v5, v12); // fcmp d5, d12 __ fcmps(v24, 0.0); // fcmp s24, #0.0 __ fcmpd(v24, 0.0); // fcmp d24, #0.0 // LoadStorePairOp __ stpw(r27, r21, Address(r16, 128)); // stp w27, w21, [x16, #128] __ ldpw(r17, r13, Address(r22, 32)); // ldp w17, w13, [x22, #32] __ ldpsw(r6, r13, Address(r17, -16)); // ldpsw x6, x13, [x17, #-16] __ stp(r28, r26, Address(r17, -160)); // stp x28, x26, [x17, #-160] __ ldp(r21, r6, Address(r13, -192)); // ldp x21, x6, [x13, #-192] // LoadStorePairOp __ stpw(r26, r23, Address(__ pre(r19, 16))); // stp w26, w23, [x19, #16]! __ ldpw(r4, r16, Address(__ pre(r10, 128))); // ldp w4, w16, [x10, #128]! __ ldpsw(r14, r4, Address(__ pre(r23, -96))); // ldpsw x14, x4, [x23, #-96]! __ stp(r29, r12, Address(__ pre(r16, 32))); // stp x29, x12, [x16, #32]! __ ldp(r26, r17, Address(__ pre(r27, 96))); // ldp x26, x17, [x27, #96]! // LoadStorePairOp __ stpw(r6, r0, Address(__ post(r4, -96))); // stp w6, w0, [x4], #-96 __ ldpw(r2, r30, Address(__ post(r14, 0))); // ldp w2, w30, [x14], #0 __ ldpsw(r23, r24, Address(__ post(r7, -256))); // ldpsw x23, x24, [x7], #-256 __ stp(r0, r26, Address(__ post(r5, 128))); // stp x0, x26, [x5], #128 __ ldp(r6, r11, Address(__ post(r15, -160))); // ldp x6, x11, [x15], #-160 // LoadStorePairOp __ stnpw(r25, r8, Address(r2, -128)); // stnp w25, w8, [x2, #-128] __ ldnpw(r30, r14, Address(r1, -208)); // ldnp w30, w14, [x1, #-208] __ stnp(r22, r0, Address(r13, -144)); // stnp x22, x0, [x13, #-144] __ ldnp(r3, r12, Address(r27, 0)); // ldnp x3, x12, [x27, #0] // LdStNEONOp __ ld1(v10, __ T8B, Address(r0)); // ld1 {v10.8B}, [x0] __ ld1(v12, v13, __ T16B, Address(__ post(r17, 32))); // ld1 {v12.16B, v13.16B}, [x17], 32 __ ld1(v10, v11, v12, __ T1D, Address(__ post(r24, r2))); // ld1 {v10.1D, v11.1D, v12.1D}, [x2 __ ld1(v8, v9, v10, v11, __ T8H, Address(__ post(r17, 64))); // ld1 {v8.8H, v9.8H, v10.8H, v11. __ ld1r(v23, __ T8B, Address(r30)); // ld1r {v23.8B}, [x30] __ ld1r(v22, __ T4S, Address(__ post(r2, 4))); // ld1r {v22.4S}, [x2], 4 __ ld1r(v30, __ T1D, Address(__ post(r30, r15))); // ld1r {v30.1D}, [x30], x15 __ ld2(v20, v21, __ T2D, Address(r5)); // ld2 {v20.2D, v21.2D}, [x5] __ ld2(v24, v25, __ T4H, Address(__ post(r9, 16))); // ld2 {v24.4H, v25.4H}, [x9], 16 __ ld2r(v16, v17, __ T16B, Address(r12)); // ld2r {v16.16B, v17.16B}, [x12] __ ld2r(v23, v24, __ T2S, Address(__ post(r7, 8))); // ld2r {v23.2S, v24.2S}, [x7], 8 __ ld2r(v26, v27, __ T2D, Address(__ post(r16, r3))); // ld2r {v26.2D, v27.2D}, [x16], x3 __ ld3(v25, v26, v27, __ T4S, Address(__ post(r11, r7))); // ld3 {v25.4S, v26.4S, v27.4S}, [x1 __ ld3(v30, v31, v0, __ T2S, Address(r12)); // ld3 {v30.2S, v31.2S, v0.2S}, [x12] __ ld3r(v15, v16, v17, __ T8H, Address(r9)); // ld3r {v15.8H, v16.8H, v17.8H}, [x9] __ ld3r(v30, v31, v0, __ T4S, Address(__ post(r6, 12))); // ld3r {v30.4S, v31.4S, v0.4S}, [x6] __ ld3r(v7, v8, v9, __ T1D, Address(__ post(r23, r13))); // ld3r {v7.1D, v8.1D, v9.1D}, [x23], __ ld4(v4, v5, v6, v7, __ T8H, Address(__ post(r6, 64))); // ld4 {v4.8H, v5.8H, v6.8H, v7.8H}, [ __ ld4(v4, v5, v6, v7, __ T8B, Address(__ post(r19, r15))); // ld4 {v4.8B, v5.8B, v6.8B, v7.8B} __ ld4r(v25, v26, v27, v28, __ T8B, Address(r14)); // ld4r {v25.8B, v26.8B, v27.8B, v28.8B}, [ __ ld4r(v26, v27, v28, v29, __ T4H, Address(__ post(r28, 8))); // ld4r {v26.4H, v27.4H, v28.4H __ ld4r(v25, v26, v27, v28, __ T2S, Address(__ post(r5, r6))); // ld4r {v25.2S, v26.2S, v27.2S // NEONReduceInstruction __ addv(v14, __ T8B, v15); // addv b14, v15.8B __ addv(v10, __ T16B, v11); // addv b10, v11.16B __ addv(v13, __ T4H, v14); // addv h13, v14.4H __ addv(v14, __ T8H, v15); // addv h14, v15.8H __ addv(v20, __ T4S, v21); // addv s20, v21.4S __ smaxv(v1, __ T8B, v2); // smaxv b1, v2.8B __ smaxv(v22, __ T16B, v23); // smaxv b22, v23.16B __ smaxv(v30, __ T4H, v31); // smaxv h30, v31.4H __ smaxv(v14, __ T8H, v15); // smaxv h14, v15.8H __ smaxv(v2, __ T4S, v3); // smaxv s2, v3.4S __ fmaxv(v6, __ T4S, v7); // fmaxv s6, v7.4S __ sminv(v3, __ T8B, v4); // sminv b3, v4.8B __ uminv(v7, __ T8B, v8); // uminv b7, v8.8B __ sminv(v24, __ T16B, v25); // sminv b24, v25.16B __ uminv(v0, __ T16B, v1); // uminv b0, v1.16B __ sminv(v27, __ T4H, v28); // sminv h27, v28.4H __ uminv(v29, __ T4H, v30); // uminv h29, v30.4H __ sminv(v5, __ T8H, v6); // sminv h5, v6.8H __ uminv(v5, __ T8H, v6); // uminv h5, v6.8H __ sminv(v29, __ T4S, v30); // sminv s29, v30.4S __ uminv(v11, __ T4S, v12); // uminv s11, v12.4S __ fminv(v25, __ T4S, v26); // fminv s25, v26.4S __ fmaxp(v0, v1, __ S); // fmaxp s0, v1.2S __ fmaxp(v30, v31, __ D); // fmaxp d30, v31.2D __ fminp(v0, v1, __ S); // fminp s0, v1.2S __ fminp(v17, v18, __ D); // fminp d17, v18.2D // TwoRegNEONOp __ absr(v28, __ T8B, v29); // abs v28.8B, v29.8B __ absr(v25, __ T16B, v26); // abs v25.16B, v26.16B __ absr(v9, __ T4H, v10); // abs v9.4H, v10.4H __ absr(v25, __ T8H, v26); // abs v25.8H, v26.8H __ absr(v12, __ T2S, v13); // abs v12.2S, v13.2S __ absr(v15, __ T4S, v16); // abs v15.4S, v16.4S __ absr(v11, __ T2D, v12); // abs v11.2D, v12.2D __ fabs(v10, __ T2S, v11); // fabs v10.2S, v11.2S __ fabs(v17, __ T4S, v18); // fabs v17.4S, v18.4S __ fabs(v24, __ T2D, v25); // fabs v24.2D, v25.2D __ fneg(v21, __ T2S, v22); // fneg v21.2S, v22.2S __ fneg(v23, __ T4S, v24); // fneg v23.4S, v24.4S __ fneg(v0, __ T2D, v1); // fneg v0.2D, v1.2D __ fsqrt(v16, __ T2S, v17); // fsqrt v16.2S, v17.2S __ fsqrt(v10, __ T4S, v11); // fsqrt v10.4S, v11.4S __ fsqrt(v6, __ T2D, v7); // fsqrt v6.2D, v7.2D __ notr(v28, __ T8B, v29); // not v28.8B, v29.8B __ notr(v6, __ T16B, v7); // not v6.16B, v7.16B // ThreeRegNEONOp __ andr(v5, __ T8B, v6, v7); // and v5.8B, v6.8B, v7.8B __ andr(v5, __ T16B, v6, v7); // and v5.16B, v6.16B, v7.16B __ orr(v20, __ T8B, v21, v22); // orr v20.8B, v21.8B, v22.8B __ orr(v17, __ T16B, v18, v19); // orr v17.16B, v18.16B, v19.16B __ eor(v15, __ T8B, v16, v17); // eor v15.8B, v16.8B, v17.8B __ eor(v17, __ T16B, v18, v19); // eor v17.16B, v18.16B, v19.16B __ addv(v29, __ T8B, v30, v31); // add v29.8B, v30.8B, v31.8B __ addv(v26, __ T16B, v27, v28); // add v26.16B, v27.16B, v28.16B __ addv(v28, __ T4H, v29, v30); // add v28.4H, v29.4H, v30.4H __ addv(v1, __ T8H, v2, v3); // add v1.8H, v2.8H, v3.8H __ addv(v27, __ T2S, v28, v29); // add v27.2S, v28.2S, v29.2S __ addv(v0, __ T4S, v1, v2); // add v0.4S, v1.4S, v2.4S __ addv(v20, __ T2D, v21, v22); // add v20.2D, v21.2D, v22.2D __ fadd(v28, __ T2S, v29, v30); // fadd v28.2S, v29.2S, v30.2S __ fadd(v15, __ T4S, v16, v17); // fadd v15.4S, v16.4S, v17.4S __ fadd(v12, __ T2D, v13, v14); // fadd v12.2D, v13.2D, v14.2D __ subv(v10, __ T8B, v11, v12); // sub v10.8B, v11.8B, v12.8B __ subv(v28, __ T16B, v29, v30); // sub v28.16B, v29.16B, v30.16B __ subv(v28, __ T4H, v29, v30); // sub v28.4H, v29.4H, v30.4H __ subv(v19, __ T8H, v20, v21); // sub v19.8H, v20.8H, v21.8H __ subv(v22, __ T2S, v23, v24); // sub v22.2S, v23.2S, v24.2S __ subv(v10, __ T4S, v11, v12); // sub v10.4S, v11.4S, v12.4S __ subv(v4, __ T2D, v5, v6); // sub v4.2D, v5.2D, v6.2D __ fsub(v30, __ T2S, v31, v0); // fsub v30.2S, v31.2S, v0.2S __ fsub(v20, __ T4S, v21, v22); // fsub v20.4S, v21.4S, v22.4S __ fsub(v8, __ T2D, v9, v10); // fsub v8.2D, v9.2D, v10.2D __ mulv(v30, __ T8B, v31, v0); // mul v30.8B, v31.8B, v0.8B __ mulv(v17, __ T16B, v18, v19); // mul v17.16B, v18.16B, v19.16B __ mulv(v10, __ T4H, v11, v12); // mul v10.4H, v11.4H, v12.4H __ mulv(v27, __ T8H, v28, v29); // mul v27.8H, v28.8H, v29.8H __ mulv(v2, __ T2S, v3, v4); // mul v2.2S, v3.2S, v4.2S __ mulv(v24, __ T4S, v25, v26); // mul v24.4S, v25.4S, v26.4S __ fabd(v4, __ T2S, v5, v6); // fabd v4.2S, v5.2S, v6.2S __ fabd(v3, __ T4S, v4, v5); // fabd v3.4S, v4.4S, v5.4S __ fabd(v8, __ T2D, v9, v10); // fabd v8.2D, v9.2D, v10.2D __ fmul(v22, __ T2S, v23, v24); // fmul v22.2S, v23.2S, v24.2S __ fmul(v17, __ T4S, v18, v19); // fmul v17.4S, v18.4S, v19.4S __ fmul(v13, __ T2D, v14, v15); // fmul v13.2D, v14.2D, v15.2D __ mlav(v4, __ T4H, v5, v6); // mla v4.4H, v5.4H, v6.4H __ mlav(v28, __ T8H, v29, v30); // mla v28.8H, v29.8H, v30.8H __ mlav(v23, __ T2S, v24, v25); // mla v23.2S, v24.2S, v25.2S __ mlav(v21, __ T4S, v22, v23); // mla v21.4S, v22.4S, v23.4S __ fmla(v25, __ T2S, v26, v27); // fmla v25.2S, v26.2S, v27.2S __ fmla(v24, __ T4S, v25, v26); // fmla v24.4S, v25.4S, v26.4S __ fmla(v3, __ T2D, v4, v5); // fmla v3.2D, v4.2D, v5.2D __ mlsv(v23, __ T4H, v24, v25); // mls v23.4H, v24.4H, v25.4H __ mlsv(v26, __ T8H, v27, v28); // mls v26.8H, v27.8H, v28.8H __ mlsv(v23, __ T2S, v24, v25); // mls v23.2S, v24.2S, v25.2S __ mlsv(v14, __ T4S, v15, v16); // mls v14.4S, v15.4S, v16.4S __ fmls(v21, __ T2S, v22, v23); // fmls v21.2S, v22.2S, v23.2S __ fmls(v3, __ T4S, v4, v5); // fmls v3.4S, v4.4S, v5.4S __ fmls(v23, __ T2D, v24, v25); // fmls v23.2D, v24.2D, v25.2D __ fdiv(v8, __ T2S, v9, v10); // fdiv v8.2S, v9.2S, v10.2S __ fdiv(v24, __ T4S, v25, v26); // fdiv v24.4S, v25.4S, v26.4S __ fdiv(v19, __ T2D, v20, v21); // fdiv v19.2D, v20.2D, v21.2D __ maxv(v15, __ T8B, v16, v17); // smax v15.8B, v16.8B, v17.8B __ maxv(v16, __ T16B, v17, v18); // smax v16.16B, v17.16B, v18.16B __ maxv(v2, __ T4H, v3, v4); // smax v2.4H, v3.4H, v4.4H __ maxv(v1, __ T8H, v2, v3); // smax v1.8H, v2.8H, v3.8H __ maxv(v0, __ T2S, v1, v2); // smax v0.2S, v1.2S, v2.2S __ maxv(v24, __ T4S, v25, v26); // smax v24.4S, v25.4S, v26.4S __ smaxp(v4, __ T8B, v5, v6); // smaxp v4.8B, v5.8B, v6.8B __ smaxp(v3, __ T16B, v4, v5); // smaxp v3.16B, v4.16B, v5.16B __ smaxp(v11, __ T4H, v12, v13); // smaxp v11.4H, v12.4H, v13.4H __ smaxp(v30, __ T8H, v31, v0); // smaxp v30.8H, v31.8H, v0.8H __ smaxp(v27, __ T2S, v28, v29); // smaxp v27.2S, v28.2S, v29.2S __ smaxp(v9, __ T4S, v10, v11); // smaxp v9.4S, v10.4S, v11.4S __ fmax(v25, __ T2S, v26, v27); // fmax v25.2S, v26.2S, v27.2S __ fmax(v2, __ T4S, v3, v4); // fmax v2.4S, v3.4S, v4.4S __ fmax(v12, __ T2D, v13, v14); // fmax v12.2D, v13.2D, v14.2D __ minv(v17, __ T8B, v18, v19); // smin v17.8B, v18.8B, v19.8B __ minv(v30, __ T16B, v31, v0); // smin v30.16B, v31.16B, v0.16B __ minv(v1, __ T4H, v2, v3); // smin v1.4H, v2.4H, v3.4H __ minv(v12, __ T8H, v13, v14); // smin v12.8H, v13.8H, v14.8H __ minv(v28, __ T2S, v29, v30); // smin v28.2S, v29.2S, v30.2S __ minv(v0, __ T4S, v1, v2); // smin v0.4S, v1.4S, v2.4S __ sminp(v17, __ T8B, v18, v19); // sminp v17.8B, v18.8B, v19.8B __ sminp(v12, __ T16B, v13, v14); // sminp v12.16B, v13.16B, v14.16B __ sminp(v17, __ T4H, v18, v19); // sminp v17.4H, v18.4H, v19.4H __ sminp(v21, __ T8H, v22, v23); // sminp v21.8H, v22.8H, v23.8H __ sminp(v12, __ T2S, v13, v14); // sminp v12.2S, v13.2S, v14.2S __ sminp(v27, __ T4S, v28, v29); // sminp v27.4S, v28.4S, v29.4S __ fmin(v29, __ T2S, v30, v31); // fmin v29.2S, v30.2S, v31.2S __ fmin(v30, __ T4S, v31, v0); // fmin v30.4S, v31.4S, v0.4S __ fmin(v1, __ T2D, v2, v3); // fmin v1.2D, v2.2D, v3.2D __ cmeq(v25, __ T8B, v26, v27); // cmeq v25.8B, v26.8B, v27.8B __ cmeq(v27, __ T16B, v28, v29); // cmeq v27.16B, v28.16B, v29.16B __ cmeq(v4, __ T4H, v5, v6); // cmeq v4.4H, v5.4H, v6.4H __ cmeq(v29, __ T8H, v30, v31); // cmeq v29.8H, v30.8H, v31.8H __ cmeq(v3, __ T2S, v4, v5); // cmeq v3.2S, v4.2S, v5.2S __ cmeq(v6, __ T4S, v7, v8); // cmeq v6.4S, v7.4S, v8.4S __ cmeq(v29, __ T2D, v30, v31); // cmeq v29.2D, v30.2D, v31.2D __ fcmeq(v25, __ T2S, v26, v27); // fcmeq v25.2S, v26.2S, v27.2S __ fcmeq(v17, __ T4S, v18, v19); // fcmeq v17.4S, v18.4S, v19.4S __ fcmeq(v8, __ T2D, v9, v10); // fcmeq v8.2D, v9.2D, v10.2D __ cmgt(v7, __ T8B, v8, v9); // cmgt v7.8B, v8.8B, v9.8B __ cmgt(v12, __ T16B, v13, v14); // cmgt v12.16B, v13.16B, v14.16B __ cmgt(v0, __ T4H, v1, v2); // cmgt v0.4H, v1.4H, v2.4H __ cmgt(v19, __ T8H, v20, v21); // cmgt v19.8H, v20.8H, v21.8H __ cmgt(v1, __ T2S, v2, v3); // cmgt v1.2S, v2.2S, v3.2S __ cmgt(v23, __ T4S, v24, v25); // cmgt v23.4S, v24.4S, v25.4S __ cmgt(v2, __ T2D, v3, v4); // cmgt v2.2D, v3.2D, v4.2D __ cmhi(v0, __ T8B, v1, v2); // cmhi v0.8B, v1.8B, v2.8B __ cmhi(v8, __ T16B, v9, v10); // cmhi v8.16B, v9.16B, v10.16B __ cmhi(v23, __ T4H, v24, v25); // cmhi v23.4H, v24.4H, v25.4H __ cmhi(v25, __ T8H, v26, v27); // cmhi v25.8H, v26.8H, v27.8H __ cmhi(v15, __ T2S, v16, v17); // cmhi v15.2S, v16.2S, v17.2S __ cmhi(v29, __ T4S, v30, v31); // cmhi v29.4S, v30.4S, v31.4S __ cmhi(v3, __ T2D, v4, v5); // cmhi v3.2D, v4.2D, v5.2D __ cmhs(v10, __ T8B, v11, v12); // cmhs v10.8B, v11.8B, v12.8B __ cmhs(v22, __ T16B, v23, v24); // cmhs v22.16B, v23.16B, v24.16B __ cmhs(v10, __ T4H, v11, v12); // cmhs v10.4H, v11.4H, v12.4H __ cmhs(v4, __ T8H, v5, v6); // cmhs v4.8H, v5.8H, v6.8H __ cmhs(v17, __ T2S, v18, v19); // cmhs v17.2S, v18.2S, v19.2S __ cmhs(v1, __ T4S, v2, v3); // cmhs v1.4S, v2.4S, v3.4S __ cmhs(v11, __ T2D, v12, v13); // cmhs v11.2D, v12.2D, v13.2D __ fcmgt(v7, __ T2S, v8, v9); // fcmgt v7.2S, v8.2S, v9.2S __ fcmgt(v10, __ T4S, v11, v12); // fcmgt v10.4S, v11.4S, v12.4S __ fcmgt(v15, __ T2D, v16, v17); // fcmgt v15.2D, v16.2D, v17.2D __ cmge(v16, __ T8B, v17, v18); // cmge v16.8B, v17.8B, v18.8B __ cmge(v2, __ T16B, v3, v4); // cmge v2.16B, v3.16B, v4.16B __ cmge(v9, __ T4H, v10, v11); // cmge v9.4H, v10.4H, v11.4H __ cmge(v11, __ T8H, v12, v13); // cmge v11.8H, v12.8H, v13.8H __ cmge(v12, __ T2S, v13, v14); // cmge v12.2S, v13.2S, v14.2S __ cmge(v14, __ T4S, v15, v16); // cmge v14.4S, v15.4S, v16.4S __ cmge(v13, __ T2D, v14, v15); // cmge v13.2D, v14.2D, v15.2D __ fcmge(v2, __ T2S, v3, v4); // fcmge v2.2S, v3.2S, v4.2S __ fcmge(v6, __ T4S, v7, v8); // fcmge v6.4S, v7.4S, v8.4S __ fcmge(v19, __ T2D, v20, v21); // fcmge v19.2D, v20.2D, v21.2D __ facgt(v25, __ T2S, v26, v27); // facgt v25.2S, v26.2S, v27.2S __ facgt(v15, __ T4S, v16, v17); // facgt v15.4S, v16.4S, v17.4S __ facgt(v4, __ T2D, v5, v6); // facgt v4.2D, v5.2D, v6.2D // SVEComparisonWithZero __ sve_fcm(Assembler::EQ, p1, __ S, p4, z4, 0.0); // fcmeq p1.s, p4/z, z4.s, #0.0 __ sve_fcm(Assembler::GT, p10, __ D, p2, z16, 0.0); // fcmgt p10.d, p2/z, z16.d, #0.0 __ sve_fcm(Assembler::GE, p10, __ S, p6, z22, 0.0); // fcmge p10.s, p6/z, z22.s, #0.0 __ sve_fcm(Assembler::LT, p11, __ S, p2, z28, 0.0); // fcmlt p11.s, p2/z, z28.s, #0.0 __ sve_fcm(Assembler::LE, p12, __ S, p7, z1, 0.0); // fcmle p12.s, p7/z, z1.s, #0.0 __ sve_fcm(Assembler::NE, p5, __ S, p0, z15, 0.0); // fcmne p5.s, p0/z, z15.s, #0.0 // SpecialCases __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0 __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp] __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3] __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5] __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp] __ dup(v0, __ T16B, zr); // dup v0.16b, wzr __ dup(v0, __ S, v1); // dup s0, v1.s[0] __ mov(v1, __ D, 0, zr); // mov v1.d[0], xzr __ mov(v1, __ S, 1, zr); // mov v1.s[1], wzr __ mov(v1, __ H, 2, zr); // mov v1.h[2], wzr __ mov(v1, __ B, 3, zr); // mov v1.b[3], wzr __ smov(r0, v1, __ S, 0); // smov x0, v1.s[0] __ smov(r0, v1, __ H, 1); // smov x0, v1.h[1] __ smov(r0, v1, __ B, 2); // smov x0, v1.b[2] __ umov(r0, v1, __ D, 0); // umov x0, v1.d[0] __ umov(r0, v1, __ S, 1); // umov w0, v1.s[1] __ umov(r0, v1, __ H, 2); // umov w0, v1.h[2] __ umov(r0, v1, __ B, 3); // umov w0, v1.b[3] __ fmovhid(r0, v1); // fmov x0, v1.d[1] __ fmovs(v9, __ T2S, 0.5f); // fmov v9.2s, 0.5 __ fmovd(v14, __ T2D, 0.5f); // fmov v14.2d, 0.5 __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0 __ fcvtzs(v0, __ T2S, v1); // fcvtzs v0.2s, v1.2s __ fcvtas(v2, __ T4S, v3); // fcvtas v2.4s, v3.4s __ fcvtms(v4, __ T2D, v5); // fcvtms v4.2d, v5.2d __ sve_cpy(z0, __ S, p0, v1); // mov z0.s, p0/m, s1 __ sve_cpy(z0, __ B, p0, 127, true); // mov z0.b, p0/m, 127 __ sve_cpy(z1, __ H, p0, -128, true); // mov z1.h, p0/m, -128 __ sve_cpy(z2, __ S, p0, 32512, true); // mov z2.s, p0/m, 32512 __ sve_cpy(z5, __ D, p0, -32768, false); // mov z5.d, p0/z, -32768 __ sve_cpy(z10, __ B, p0, -1, false); // mov z10.b, p0/z, -1 __ sve_cpy(z11, __ S, p0, -1, false); // mov z11.s, p0/z, -1 __ sve_inc(r0, __ S); // incw x0 __ sve_dec(r1, __ H); // dech x1 __ sve_lsl(z0, __ B, z1, 7); // lsl z0.b, z1.b, #7 __ sve_lsl(z21, __ H, z1, 15); // lsl z21.h, z1.h, #15 __ sve_lsl(z0, __ S, z1, 31); // lsl z0.s, z1.s, #31 __ sve_lsl(z0, __ D, z1, 63); // lsl z0.d, z1.d, #63 __ sve_lsr(z0, __ B, z1, 7); // lsr z0.b, z1.b, #7 __ sve_asr(z0, __ H, z11, 15); // asr z0.h, z11.h, #15 __ sve_lsr(z30, __ S, z1, 31); // lsr z30.s, z1.s, #31 __ sve_asr(z0, __ D, z1, 63); // asr z0.d, z1.d, #63 __ sve_lsl(z0, __ B, p0, 0); // lsl z0.b, p0/m, z0.b, #0 __ sve_lsl(z0, __ B, p0, 5); // lsl z0.b, p0/m, z0.b, #5 __ sve_lsl(z1, __ H, p1, 15); // lsl z1.h, p1/m, z1.h, #15 __ sve_lsl(z2, __ S, p2, 31); // lsl z2.s, p2/m, z2.s, #31 __ sve_lsl(z3, __ D, p3, 63); // lsl z3.d, p3/m, z3.d, #63 __ sve_lsr(z0, __ B, p0, 1); // lsr z0.b, p0/m, z0.b, #1 __ sve_lsr(z0, __ B, p0, 8); // lsr z0.b, p0/m, z0.b, #8 __ sve_lsr(z1, __ H, p1, 15); // lsr z1.h, p1/m, z1.h, #15 __ sve_lsr(z2, __ S, p2, 7); // lsr z2.s, p2/m, z2.s, #7 __ sve_lsr(z2, __ S, p2, 31); // lsr z2.s, p2/m, z2.s, #31 __ sve_lsr(z3, __ D, p3, 63); // lsr z3.d, p3/m, z3.d, #63 __ sve_asr(z0, __ B, p0, 1); // asr z0.b, p0/m, z0.b, #1 __ sve_asr(z0, __ B, p0, 7); // asr z0.b, p0/m, z0.b, #7 __ sve_asr(z1, __ H, p1, 5); // asr z1.h, p1/m, z1.h, #5 __ sve_asr(z1, __ H, p1, 15); // asr z1.h, p1/m, z1.h, #15 __ sve_asr(z2, __ S, p2, 31); // asr z2.s, p2/m, z2.s, #31 __ sve_asr(z3, __ D, p3, 63); // asr z3.d, p3/m, z3.d, #63 __ sve_addvl(sp, r0, 31); // addvl sp, x0, #31 __ sve_addpl(r1, sp, -32); // addpl x1, sp, -32 __ sve_cntp(r8, __ B, p0, p1); // cntp x8, p0, p1.b __ sve_dup(z0, __ B, 127); // dup z0.b, 127 __ sve_dup(z1, __ H, -128); // dup z1.h, -128 __ sve_dup(z2, __ S, 32512); // dup z2.s, 32512 __ sve_dup(z7, __ D, -32768); // dup z7.d, -32768 __ sve_dup(z10, __ B, -1); // dup z10.b, -1 __ sve_dup(z11, __ S, -1); // dup z11.s, -1 __ sve_ld1b(z0, __ B, p0, Address(sp)); // ld1b {z0.b}, p0/z, [sp] __ sve_ld1b(z0, __ H, p1, Address(sp)); // ld1b {z0.h}, p1/z, [sp] __ sve_ld1b(z0, __ S, p2, Address(sp, r8)); // ld1b {z0.s}, p2/z, [sp, x8] __ sve_ld1b(z0, __ D, p3, Address(sp, 7)); // ld1b {z0.d}, p3/z, [sp, #7, MUL VL] __ sve_ld1h(z10, __ H, p1, Address(sp, -8)); // ld1h {z10.h}, p1/z, [sp, #-8, MUL VL] __ sve_ld1w(z20, __ S, p2, Address(r0, 7)); // ld1w {z20.s}, p2/z, [x0, #7, MUL VL] __ sve_ld1b(z30, __ B, p3, Address(sp, r8)); // ld1b {z30.b}, p3/z, [sp, x8] __ sve_ld1w(z0, __ S, p4, Address(sp, r28)); // ld1w {z0.s}, p4/z, [sp, x28, LSL #2] __ sve_ld1d(z11, __ D, p5, Address(r0, r1)); // ld1d {z11.d}, p5/z, [x0, x1, LSL #3] __ sve_st1b(z22, __ B, p6, Address(sp)); // st1b {z22.b}, p6, [sp] __ sve_st1b(z31, __ B, p7, Address(sp, -8)); // st1b {z31.b}, p7, [sp, #-8, MUL VL] __ sve_st1b(z0, __ H, p1, Address(sp)); // st1b {z0.h}, p1, [sp] --> -------------------- --> maximum size reached --> -------------------- ¤ Dauer der Verarbeitung: 0.28 Sekunden (vorverarbeitet) ¤ |
Haftungshinweis
Die Informationen auf dieser Webseite wurden
nach bestem Wissen sorgfältig zusammengestellt. Es wird jedoch weder Vollständigkeit, noch Richtigkeit,
noch Qualität der bereit gestellten Informationen zugesichert.
Bemerkung:Die farbliche Syntaxdarstellung ist noch experimentell.Bot Zugriff |
