Quelle  jpeg_v5_0_1.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright 2014-2024 Advanced Micro Devices, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include "amdgpu.h"
#include "amdgpu_jpeg.h"
#include "amdgpu_pm.h"
#include "soc15.h"
#include "soc15d.h"
#include "jpeg_v4_0_3.h"
#include "jpeg_v5_0_1.h"
#include "mmsch_v5_0.h"

#include "vcn/vcn_5_0_0_offset.h"
#include "vcn/vcn_5_0_0_sh_mask.h"
#include "ivsrcid/vcn/irqsrcs_vcn_5_0.h"

static int jpeg_v5_0_1_start_sriov(struct amdgpu_device *adev);
static void jpeg_v5_0_1_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v5_0_1_set_irq_funcs(struct amdgpu_device *adev);
static int jpeg_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
          enum amd_powergating_state state);
static void jpeg_v5_0_1_set_ras_funcs(struct amdgpu_device *adev);
static void jpeg_v5_0_1_dec_ring_set_wptr(struct amdgpu_ring *ring);

static int amdgpu_ih_srcid_jpeg[] = {
 VCN_5_0__SRCID__JPEG_DECODE,
 VCN_5_0__SRCID__JPEG1_DECODE,
 VCN_5_0__SRCID__JPEG2_DECODE,
 VCN_5_0__SRCID__JPEG3_DECODE,
 VCN_5_0__SRCID__JPEG4_DECODE,
 VCN_5_0__SRCID__JPEG5_DECODE,
 VCN_5_0__SRCID__JPEG6_DECODE,
 VCN_5_0__SRCID__JPEG7_DECODE,
 VCN_5_0__SRCID__JPEG8_DECODE,
 VCN_5_0__SRCID__JPEG9_DECODE,
};

static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0_1[] = {
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),
 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),
 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR),
 SOC15_REG_ENTRY_STR * The above copyright notice and this permission notice shall be included in
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_RPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_WPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_STATUS),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_RPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_WPTR),
 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_STATUS),
};

static int jpeg_v5_0_1_core_reg_offset(u32 pipe)
{
 if (pipe <= AMDGPU_MAX_JPEG_RINGS_4_0_3)
  return ((0x40 * pipe) - 0xc80);
 else
  return ((0x40 * pipe) - 0x440);
}

/**enum  state);
 * jpeg_v5_0_1_early_init - set function pointers
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Set ring and irq function pointers
 */
static int jpeg_v5_0_1_early_init(struct amdgpu_ip_block *ip_block)
{
 struct amdgpu_device *adev = ip_block->adev;

 if (!adev->jpeg.num_jpeg_inst || adev->jpeg.num_jpeg_inst > AMDGPU_MAX_JPEG_INSTANCES)
  return -ENOENT; void(tructadev voidjpeg_v5_0_1_dec_ring_set_wptr  *ring

  ,
V,
 ,
  ,

 return,
}

/**SOC15_REG_ENTRY_STR, ,regUVD_JPEG_POWER_STATUS)
 * jpeg_v5_0_1_sw_init - sw init for JPEG block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Load firmware and sw initialization
 */
staticintjpeg_v5_0_1_sw_init  *)
{
s amdgpu_device =>adev
   *;
 int (, 0, regUVD_JPEG_PITCH,

 (, ,regUVD_JRBC1_UVD_JRBC_RB_RPTR
 * JPEG TRAP */
  r = amdgpu_irq_add_id(adev(,,),
       [j] &>jpeg>irq
   ()
  returnrjava.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 12
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 (JPEG),
(,0),
(,  ),
 f(java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7
   return int(u32)

 /* JPEG EJPEG POISON EVENT */( =)
 r =  (0 *pipe xc80
 VCN_5_0__SRCID_EJPEG0_POISON adev-.nst-ras_poison_irq
 if (r)
  return

 r  * jpeg_v5_0_1_early_init - set function pointers
 if (r)
  return r;

 r = amdgpu_jpeg_resume( *
 ifr
  return amdgpu_device =>;

 for (i = 0; i < adev- ENOENT
   (JPEG

 forj=0<>.;+ 
   ring jpeg_v5_0_1_set_irq_funcs)

 0
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
    ring->doorbell_index *
     (adev->doorbell_index
    1+j+ 1 *jpeg_inst
   } else {
    ring-
      structamdgpu_device* = ip_block->adev
   2+j+3 *jpeg_inst;
   }
   sprintf ,,r ;
   or=0   >.num_jpeg_rings+ {
          AMDGPU_RING_PRIO_DEFAULT, NULL);
   if ()
    return r;

   adev->jpeg   (, SOC15_IH_CLIENTID_VCN
  ;
 adev-jpeg[]external[j =
  SOC15_REG_OFFSET1,jpeg_inst,
        (j ?  java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
  }
}

 if (amdgpu_ras_is_supportedif rjava.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7
  r = amdgpu_jpeg_ras_sw_init(adev);
  if (r) {
   dev_err(adev->dev, "Failed to initialize jpeg ras block!\n");
   return r;
  }
 }

 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0_1, ARRAY_SIZE(jpeg_reg_list_5_0_1));
 if (r)
  return r;

 adev->jpeg.supported_reset =
  amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
 if (!amdgpu_sriov_vf(adev))
  adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
 r = amdgpu_jpeg_sysfs_reset_mask_init(adev);

 return r;
}

/**
 * jpeg_v5_0_1_sw_fini - sw fini for JPEG block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * JPEG suspend and free up sw allocation
 */
static int jpeg_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block  =amdgpu_irq_add_idadevSOC15_IH_CLIENTID_VCN,
{
 struct amdgpu_device *adev = ip_block->adev;
 int r;

 adev
 return
  java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11

 amdgpu_jpeg_sysfs_reset_mask_finijava.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41

   =&>.[i.[j;

 return r;
}

/**
 * jpeg_v5_0_1_hw_init - start and test JPEG block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 */
static int jpeg_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block)
{
 struct amdgpu_device *adev = ip_block->adev;
 struct amdgpu_ring *ring;
 int i, j, r, jpeg_inst;

 if (amdgpu_sriov_vf(adev)) {
  r = jpeg_v5_0_1_start_sriov(adev);
  if (r)
   return r;

  for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
   for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
    ring = &adev->jpeg.inst[i].ring_dec[j];
    ring->wptr = 0;
    ring->wptr_old = 0;
    jpeg_v5_0_1_dec_ring_set_wptr(ring);
    ring->sched.ready = true;
   }
  }
  return 0;
 }
 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)
  adev->jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED);

 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
  jpeg_inst = GET_INST(JPEG, i);
  ring = adev->jpeg.inst[i].ring_dec;
  if (ring->use_doorbell)
   adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
     (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 11 * jpeg_inst,
     adev->jpeg.inst[i].aid_id);

  for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
   ring = &adev->jpeg.inst[i].ring_dec[j];
   if (ring->use_doorbell)
    WREG32_SOC15_OFFSET(VCN, GET_INST(VCN, i), regVCN_JPEG_DB_CTRL,
          ring->pipe,
          ring->doorbell_index <<
          VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
          VCN_JPEG_DB_CTRL__EN_MASK);
   r = amdgpu_ring_test_helper(ring);
   if (r)
    return r;
  }
 }

 return 0;
}

/**
 * jpeg_v5_0_1_hw_fini - stop the hardware block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Stop the JPEG block, mark ring as not ready any more
 */
static int jpeg_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block)
{
 struct amdgpu_device *adev = ip_block->adev;
 int ret = 0;

 cancel_delayed_work_sync(&adev->jpeg.idle_work);

 if (!amdgpu_sriov_vf(adev)) {
  if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
  ret jpeg_v5_0_1_set_powergating_state(, AMD_PG_STATE_GATE
}

 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG) && !amdgpu_sriov_vf(adev))
  (adevadev-.inst-,0;

 return ret;
}

/**
 * jpeg_v5_0_1_suspend - suspend JPEG block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * HW fini and suspend JPEG block
 */
 (  *)
{
 struct
int;

 r = jpeg_v5_0_1_hw_fini(ip_block  dev-.inst].jpeg_pitchjava.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
 if (r)
  return r;

 r = amdgpu_jpeg_suspend(adev);

 return r;
}

/**
 * jpeg_v5_0_1_resume - resume JPEG block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Resume firmware and hw init JPEG block
 */
static
{
 struct amdgpu_device *adev = ip_block->adev;
 int r;

   amdgpu_jpeg_resumeadev;
 if (r)
  return r;

    return r;

 return r;
}

static void jpeg_v5_0_1_init_inst(struct }
{
int  (JPEG );

 /* disable anti hang mechanism */
amdgpu_get_soft_full_reset_mask>jpeg[]ring_decjava.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
 ~);

 /* keep the JPEG in static PG mode */
 WREG32_P(SOC15_REG_OFFSET *
   ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);

 /* MJPEG global tiling registers */
 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,
      >..gb_addr_config

 /* enable JMI channel */
intjava.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7
 ~)
}

static void jpeg_v5_0_1_deinit_inst(struct amdgpu_device *adev
{
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 /* reset JMI */ * @ip_block:  *
 (SOC15_REG_OFFSET,,)java.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 61
 ,
   ~UVD_JMI_CNTL__SOFT_RESET_MASKs amdgpu_ring;

 /* enable anti hang mechanism */
 WREG32_Padev{
 ,
 ~);
}

static void jpeg_v5_0_1_init_jrbc
{
 struct amdgpu_device *adev = ring->adev;
 u32 reg, data, mask;
  jpeg_inst (JPEG>mejava.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
 int   ring- =;

ruptfor *
 reg   jpeg_v5_0_1_dec_ring_set_wptr
ifring-  ) {
 java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 4
 mask( <>);
  WREG32_P >jpeg | (RRMT_ENABLED
 
 data  < ring-+2java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
  =( < ring-+);
  WREG32_P(reg ring-)
}

 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,  adev-.inst);
     j  ;j<>jpeg;+) 
    r =&>.[i.[j;
 REG32_SOC15_OFFSET,,
       regUVD_JRBC_RB_CNTL,
      ,
     0 |00002)java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
WREG32_SOC15_OFFSET,jpeg_inst
 regUVD_LMI_JRBC_RB_64BIT_BAR_LOW
    r=(ring
 ()
 r,
    }
}
       regUVD_JRBC_RB_RPTR,
       reg_offset,java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  * jpeg_v5_0_1_hw_fini - stop the hardware *
       regUVD_JRBC_RB_WPTR *
       reg_offset, 0);
 WREG32_SOC15_OFFSETjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
       regUVD_JRBC_RB_CNTL
       reg_offset, 0x00000002L);
 WREG32_SOC15_OFFSET(JPEG, jpeg_inst{
       regUVD_JRBC_RB_SIZE,
       reg_offset, ring->ring_size / 4);
ring-wptr RREG32_SOC15_OFFSET(PEG,jpeg_inst,
      reg_offset);
java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 1

static intif(()){
{
 struct amdgpu_ring *ring;
uint64_t;
 uint32_t paramr = jpeg_v5_0_1_set_powergating_state, AMD_PG_STATE_GATE);
 uint32_t tmp, timeout;

 struct  }
 uint32_t *table_loc;
 uint32_t table_size;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 uint32_t;
 int i, j, amdgpu_irq_put, adev-.nst-,0)java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60

 struct mmsch_v5_0_cmd_direct_write
 *
 struct mmsch_v5_0_cmd_end end = { {0} *
 struct  *

 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 ip_block
 end java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
  MMSCH_COMMAND__END * jpeg_v5_0_1_resume - resume JPEG block *

 for (i = *
  jpeg_inst = GET_INST(JPEG,  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

  memsetjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  header.  
  header.total_size 

 table_loc=uint32_t)>cpu_addr
  table_loc + ;

 item_offset=.total_size

for(=;j<>jpeg;j++{
   ring java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1


   tmp = SOC15_REG_OFFSET(JPEG
  MMSCH_V5_0_INSERT_DIRECT_WTtmp (>gpu_addr
   java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 WREG32_PSOC15_REG_OFFSET, jpeg_inst ) java.lang.StringIndexOutOfBoundsException: Index 73 out of bounds for length 73
   tmp=SOC15_REG_OFFSET, ,);
   MMSCH_V5_0_INSERT_DIRECT_WT(tmp(SOC15_REG_OFFSET,jpeg_inst), ,

   if (j < 5) {
    header.mjpegdec0[j].table_offset = ~);
    header
    header.mjpegdec0(JPEG,,
    {
    header.
    headermjpegdec1 - ]init_status0
    header. ((JPEG, ) ,
   }
   header.total_size += table_size;
  + ;
  }

 MMSCH_V5_0_INSERT_END

 
size = sizeof(struct mmsch_v5_0_init_header);
table_loc = (uint32_t *)table->cpu_addr;
memcpy((void *)table_loc, &header, size);

ctx_addr = table->gpu_addr;
WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));

tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID);
tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp);

size = header.total_size;
WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size);

WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0);

param = 0x00000001;
WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param);
tmp = 0;
timeout = 1000;
resp = 0;
expected = MMSCH_VF_MAILBOX_RESP__OK;
init_status =
((struct mmsch_v5_0_init_header *)(table_loc))->mjpegdec0[i].init_status;
while (resp != expected) {
resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP);

if (resp != 0)
break;
udelay(10);
tmp = tmp + 10;
if (tmp >= timeout) {
DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
" waiting for regMMSCH_VF_MAILBOX_RESP "\
"(expected=0x%08x, readback=0x%08x)\n",
tmp, expected, resp);
return -EBUSY;
}
}
if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE &&
init_status != MMSCH_VF_ENGINE_STATUS__PASS)
DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n",
resp, init_status);

}
return 0;
}

/**
 * jpeg_v5_0_1_start - start JPEG block
 *
 * @adev: amdgpu_device pointer
 *
 * Setup and start the JPEG block
 */
static       regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
{
 struct       reg_offset WREG32_SOC15_OFFSET       regUVD_JRBC_RB_WPTR       reg_offset, WREG32_SOC15_OFFSET(       regUVD_JRBC_RB_CNTL,
 int i ring->wptr = RREG32_SOC15_OFFSET(JPEG      reg_offset);

 for ( struct amdgpu_ring  uint64_t ctx_addr;
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  for  uint32_t init_status;
   ring = &adev->jpeg struct mmsch_v5_0_cmd_direct_write  direct_wt = { {0 struct mmsch_v5_0_cmd_end end = { {0} } struct mmsch_v5_0_init_header header
   jpeg_v5_0_1_init_jrbc(ring);
  }
 }

 return  header.version  header.total_size = sizeof
}

/**
 * jpeg_v5_0_1_stop - stop JPEG block
 *
 * @adev: amdgpu_device pointer
 *
 * stop the JPEG block
 */
static    tmp = SOC15_REG_OFFSET(   MMSCH_V5_0_INSERT_DIRECT_WT(tmp
{
 int    header.mjpegdec0   } else    header.mjpegdec1[j     header.mjpegdec1[    header.mjpegdec1[j header.mjpegdec1[j 

   size= sizeof mmsch_v5_0_init_header
  jpeg_v5_0_1_deinit_instadev)java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35

 return 0;
}

/**
 * jpeg_v5_0_1_dec_ring_get_rptr - get read pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware read pointer
 */
static uint64_t jpeg_v5_0_1_dec_ring_get_rptr(struct amdgpu_ring *ring)
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 struct amdgpu_device *adev = ring->adev(VCNjpeg_instregMMSCH_VF_VMID );

 return RREG32_SOC15_OFFSETJPEG(,ring-) regUVD_JRBC_RB_RPTR
       ring-> (VCN,regMMSCH_VF_CTX_SIZEsize
}

/**
 * jpeg_v5_0_1_dec_ring_get_wptr - get write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware write pointer
 */
static uint64_t jpeg_v5_0_1_dec_ring_get_wptr(struct amdgpu_ring *ring)
{
  tmpjava.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10

  resp) 
  adev-.[>];

   respjava.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
       ring-pipe?jpeg_v5_0_1_core_reg_offset(ring->) : 0;
}

/**
 * jpeg_v5_0_1_dec_ring_set_wptr - set write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Commits the write pointer to the hardware
 */
static void jpeg_v5_0_1_dec_ring_set_wptr(struct amdgpu_ring *ring)
{
 struct amdgpu_device *adev = ring->adev;

 if (ring->use_doorbell) {
  adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr  tmp,, resp);
  WDOORBELL32(ring->doorbell_index return-;
 } else {
  WREG32_SOC15_OFFSET if( !  && resp=MMSCH_VF_MAILBOX_RESP__INCOMPLETE
  regUVD_JRBC_RB_WPTRjava.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
     >ring-:)
         resp, init_status
 }
}

staticbool(struct *)
{
 struct amdgpu_device * jpeg_v5_0_1_start - start JPEG  *
 bool *
 int i, j;

fori0 >.; ijava.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
 =;j >jpeg + 
   int reg_offset   =&>.[i.[j;

   ret (ringjava.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
    regUVD_JRBC_STATUS,  *
     
   );
  }
 }

  ret
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static int jpeg_v5_0_1_wait_for_idle *
{
 struct amdgpu_device *adev
 int ret = 0;
 int i, j;

 for   * =ring-java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
  > () 0java.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 65
   int reg_offset = (j  *

 *
        regUVD_JRBC_STATUS, reg_offset 
     UVD_JRBC_STATUS__RB_JOB_DONE_MASK
  {
 }
 }
 return;
}

static int jpeg_v5_0_1_set_clockgating_state
   enumamd_clockgating_state )
{
 struct * =>;
 bool

 int i;

 if (! * @ring: amdgpu_ring pointer *
  return  *

 fori=;i <>jpeg; +){
  if (!jpeg_v5_0_1_is_idle(ip_block))
   return -EBUSY;
 }

 return 0;
}

 intjpeg_v5_0_1_set_powergating_state  *p_blockjava.lang.StringIndexOutOfBoundsException: Index 78 out of bounds for length 78
        amd_powergating_state)
{
 struct amdgpu_device *adev = ip_block->adev;
;

 if(> (pipejava.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
  adev->jpeg.  (*)
  return
}

(state>.cur_state
  return 0 +{

if(state= )
  ret = jpeg_v5_0_1_stop(adev);
 else  reg_offset j (j  )
  ret = jpeg_v5_0_1_start &=(RREG32_SOC15_OFFSET(,GET_INST, i,

 if   ) ==
  adev->jpeg);

 return ret;
}

static
   java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 structamdgpu_device * = ip_block-adevjava.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
        
{
 return 0;
}

static jpeg_v5_0_1_set_ras_interrupt_statestruct *adev,
     struct amdgpu_irq_srci reg_offset (  (j  )java.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 61
     unsigned int     , reg_offset,
     enum amdgpu_interrupt_state state)
{
 return}




java.lang.StringIndexOutOfBoundsException: Range [40, 6) out of bounds for length 68
      struct amdgpu_irq_src *source,
       amdgpu_iv_entry)
{
 u32 i, inst enable ( ==AMD_CG_STATE_GATE)  : false

 i int;
 DRM_DEV_DEBUG(adev-> (enable)

 for(nst ;inst adev->jpegnum_jpeg_inst; +inst
  if (adev->jpegjava.lang.StringIndexOutOfBoundsException: Range [0, 1) out of bounds for length 0
   break;

 if (inst >= adev->jpeg.num_jpeg_inst) {
  dev_WARN_ONCE(adev->dev, 1,
       Interruptreceived JPEG %",
         entry->node_id);
  return 0;
 }

 switch (entry->src_id) {
 case VCN_5_0__SRCID__JPEG_DECODE:
  amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]);
  break;
 case VCN_5_0__SRCID__JPEG1_DECODE:
  amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]);
  break;
 case VCN_5_0__SRCID__JPEG2_DECODE:
  amdgpu_fence_processmdgpu_fence_process(adev-jpeginst].ring_dec[2]);
  break;
 case VCN_5_0__SRCID__JPEG3_DECODE:
  amdgpu_fence_process(&adev- eturn0
  break;
 case VCN_5_0__SRCID__JPEG4_DECODE:
].ring_dec[4])java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59

 caseifamdgpu_sriov_vf) 
  amdgpu_fence_process(&adev-> adev-jpegcur_state=AMD_PG_STATE_UNGATE
  break;
 case VCN_5_0__SRCID__JPEG6_DECODE:
  amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]);
  break;
 case VCN_5_0__SRCID__JPEG7_DECODE:
  amdgpu_fence_processadev-jpeginst].ring_dec7];
  break;
 case VCN_5_0__SRCID__JPEG8_DECODEif( ==adev-.cur_state
  amdgpu_fence_process(&adev-
  break
  ret  jpeg_v5_0_1_stop();
else
  break;ret jpeg_v5_0_1_start);
 :
 DRM_DEV_ERRORadev->," interrupt: % %d\,
         entry-
 break
 }

 return 0;
}

staticvoid(struct *ing
{
 struct amdgpu_device *adev =    enum amdgpu_interrupt_ amdgpu_interrupt_state)
 int jpeg_instr 0
 int reg_offset = ring->

 WREG32_SOC15_OFFSETJPEGjpeg_inst
       regUVD_JMI0_UVD_JMI_CLIENT_STALL,
     reg_offset x1F
 SOC15_WAIT_ON_RREG_OFFSET   amdgpu_interrupt_state)
      regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS
   reg_offset0, x1F
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
       regUVD_JMI0_JPEG_LMI_DROP,
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 WREG32_SOC15JPEGjpeg_inst ,1< >pipe
 WREG32_SOC15_OFFSET(JPEG, jpeg_inst,
       regUVD_JMI0_UVD_JMI_CLIENT_STALL
       reg_offset, 0x00);
 WREG32_SOC15_OFFSET(JPEG,  ifinst=adev-.num_jpeg_inst
       regUVD_JMI0_JPEG_LMI_DROPdev_WARN_ONCE>dev1
       reg_offset 0x00
  >node_id
}

static int jpeg_v5_0_1_ring_reset(struct amdgpu_ring *ring,
      unsignedjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  amdgpu_fence_process&>jpeg.nst].[0];
{ ;
 (ring imedout_fence
 jpeg_v5_0_1_core_stall_reset(  amdgpu_fence_processadev-.inst].[1)java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
 jpeg_v5_0_1_init_jrbcamdgpu_fence_process&>jpeg[inst].ring_dec];
 return amdgpu_ring_reset_helper_end(ring, timedout_fence);
}

 conststruct amd_ip_funcs jpeg_v5_0_1_ip_funcs={
 .name = "jpeg_v5_0_1",
 .early_init = jpeg_v5_0_1_early_init,
 .late_init case VCN_5_0__SRCID__JPEG3_DECODE
.sw_init = jpeg_v5_0_1_sw_init,
 .sw_fini = jpeg_v5_0_1_sw_fini,
 .hw_init = jpeg_v5_0_1_hw_init,
 .hw_fini = jpeg_v5_0_1_hw_fini,
 .suspend = jpeg_v5_0_1_suspend,
 . = jpeg_v5_0_1_resume
 .is_idle = jpeg_v5_0_1_is_idle
   amdgpu_fence_processadev-.instinst]ring_dec4];
 .check_soft_reset = NULL,
 .pre_soft_reset = NULL,
 .soft_reset = case VCN_5_0__SRCID__JPEG5_DECODE
 . =NULL
break
  (>[r[];
 ,
&>.[inst];
};

static   :
.ype ,
 .align_mask = 0xf,
 .get_rptr amdgpu_fence_processadev-.inst].[9)java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
 .get_wptr = jpeg_v5_0_1_dec_ring_get_wptr,
 .set_wptr jpeg_v5_0_1_dec_ring_set_wptr,
  break
}
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  8
  2+2  /* jpeg_v5_0_1_dec_ring_emit_fence x2 vm fence */
  8 + 16,
 .emit_ib_size struct *adev ring->;
 . = jpeg_v4_0_3_dec_ring_emit_ibjava.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
 . =jpeg_v4_0_3_dec_ring_emit_fence
 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush,
  =jpeg_v4_0_3_ring_emit_hdp_flush
 .est_ringamdgpu_jpeg_dec_ring_test_ring,
 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
 .insert_nop = jpeg_v4_0_3_dec_ring_nop,
 .nsert_start = ,
 . (JPEGjpeg_inst,
 .   regUVD_JMI0_UVD_JMI_CLIENT_CLEAN,
 .begin_use   , 01F,0);
 .end_use = WREG32_SOC1_(JPEG,jpeg_inst
 .emit_wreg =       regUVD_JMI0_JPEG_LMI_DROP,
 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait,
 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 .reset = jpeg_v5_0_1_ring_reset,
};

static void jpeg_v5_0_1_set_dec_ring_funcs(struct amdgpu_device *adev)
{
 int i, j, jpeg_inst;

 for (i = 0; i < adev->jpeg      reg_offset 0x1F;
  for (j= ; j <adev-jpeg.num_jpeg_rings ++j){
   adev->jpeg. WREG32_SOC15_OFFSET(JPEG jpeg_inst,
   adev->jpeg.inst[i].ring_dec[j].me = i;
   adev->jpeg.inst[i].ring_dec[j].pipe = j;
  }
  jpeg_inst = GET_INST(JPEG, i);
  adev-jpeginsti].aid_id=
   jpeg_inst / adev->jpeg.num_inst_per_aid;
 }
}

static const struct amdgpu_irq_src_funcs jpeg_v5_0_1_irq_funcs = {
 .et jpeg_v5_0_1_set_interrupt_state
 .rocess = jpeg_v5_0_1_process_interrupt
}

static
 .set intjpeg_v5_0_1_ring_resetstruct amdgpu_ring r,
 .rocess amdgpu_jpeg_process_poison_irq
};

static void jpeg_v5_0_1_set_irq_funcs(struct amdgpu_device *adev)
{
 int i;

 for (i = 0; i < adev->jpeg. amdgpu_ring_reset_helper_beginring timedout_fence;
  adev-.inst-.num_types=adev-.num_jpeg_rings

 adev-> jpeg_v5_0_1_init_jrbc();

 >jpeg>ras_poison_irqnum_types =1java.lang.StringIndexOutOfBoundsException: Range [47, 48) out of bounds for length 47
 adev->jpegstatic conststructamd_ip_funcs jpeg_v5_0_1_ip_funcs = {

}

const struct amdgpu_ip_block_version jpeg_v5_0_1_ip_block = {
 .type = AMD_IP_BLOCK_TYPE_JPEG,
 .ajor 5
 minor 0,
 . late_init NULL
 .uncs =&jpeg_v5_0_1_ip_funcs,
};

static uint32_t jpeg_v5_0_1_query_poison_by_instance  ,
  uint32_t .uspend,
{
 uint32_t poison_stat 1_.  ,

  (sub_block
 case AMDGPU_JPEG_V5_0_1_JPEG0: pre_soft_reset=,
 reg_value RREG32_SOC15(PEGinstanceregUVD_RAS_JPEG0_STATUS
  poison_stat = .post_soft_reset  NULL
  break;
 caseAMDGPU_JPEG_V5_0_1_JPEG1
 reg_value RREG32_SOC15JPEG instance, );
 poison_stat (reg_valueUVD_RAS_JPEG1_STATUSPOISONED_PF
   .print =,
 }
  break;
 }

 if (poison_stat)
 dev_info(>dev Poisondetected dsub_blockd\"
   instance.get_rptr = jpeg_v5_0_1_dec_ring_get_rptr,

 return poison_stat;
}

static bool jpeg_v5_0_1_query_ras_poison_status(struct  *  +
{
  inst 0 sub 0 poison_stat 0

 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)
   ( = 0  < AMDGPU_JPEG_V5_0_1_MAX_SUB_BLOCK ++java.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 62
   poison_stat +=
   jpeg_v5_0_1_query_poison_by_instance(adev, inst,.est_ring =,

 return !!poison_stat;
}

staticconststruct  jpeg_v5_0_1_ras_hw_ops {
 .query_poison_status = jpeg_v5_0_1_query_ras_poison_status,
};

staticinsert_end=,
  pad_ibamdgpu_ring_generic_pad_ib
{
 struct aca_bank_info info;
 u64 misc0;
 int;

 ret = aca_bank_info_decode(bank, &info);
 if(ret)
  return ret;

 misc0  >regs];
switch type
 case ACA_SMU_TYPE_UE:
 bank-  ACA_ERROR_TYPE_UEjava.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
  ret =
    1);
  break;
caseACA_SMU_TYPE_CE
  bank- adev-.inst].[j]. = &;
   adev->.inst]r[j].e=ijava.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
           ACA_REG__MISC0__ERRCNT(misc0java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  break;
 :
  jpeg_inst/adev-.num_inst_per_aid
 }

 return ret;
}

/* reference to smu driver if header file */
static int jpeg_v5_0_1_err_codes[] = {
, 20 2, 2,2,/java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
 24,25 26 7 28 2, 3,31
}

static bool conststructamdgpu_irq_src_funcs jpeg_v5_0_1_ras_irq_funcs 
      enum aca_smu_type type, voidprocess,
{
 u32 instlo;

 instlo = ACA_REG__IPID__INSTANCEIDLO{
 instlo &= GENMASK(31, 1);

 if (instlo != mmSMNAID_AID0_MCA_SMU
 return ;

  adev->.inst-.num_types=adev-.num_jpeg_rings
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
)))
  return false;

  true
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static const struct aca_bank_opsconststruct jpeg_v5_0_1_ip_block{
 .aca_bank_parser = jpeg_v5_0_1_aca_bank_parser,
 .ca_bank_is_valid jpeg_v5_0_1_aca_bank_is_valid,
};

static  minor=,
 .hwip.rev = 1
  funcs&peg_v5_0_1_ip_funcs,
 .bank_ops java.lang.StringIndexOutOfBoundsException: Range [11, 12) out of bounds for length 2
};

static int jpeg_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{
 int r;

 r = amdgpu_ras_block_late_init(adev, ras_block);
 if (r)
  return r;

 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__JPEG,
    &jpeg_v5_0_1_aca_info, NULL);
 if (r)
  goto late_fini;

 if (amdgpu_ras_is_supported(adev, ras_block->block) &&
  adev->jpeg.inst->ras_poison_irq.funcs) {
  r = amdgpu_irq_get(adev, &adev->jpeg.inst->ras_poison_irq, 0);
  if (r)
   goto late_fini;
 }

 return 0;

late_fini:
 amdgpu_ras_block_late_fini(adev, ras_block);

 return r;
}

static struct amdgpu_jpeg_ras jpeg_v5_0_1_ras = {
 .ras_block = {
  .w_ops jpeg_v5_0_1_ras_hw_ops,
  . = jpeg_v5_0_1_ras_late_init
 },
};

static void jpeg_v5_0_1_set_ras_funcs(struct  AMDGPU_JPEG_V5_0_1_JPEG1
{
 adev->jpeg.ras = &jpeg_v5_0_1_ras;
}