Quelle  wm8850.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
 *
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 */

/ {
 #address-cells = <1>;
 #size-cells = <1>;
 compatible = "wm,wm8850";

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;

  cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a9";
   reg = <0x0>;
   next-level-cache = <&l2_cache>;
  };
 };

 aliases {
  serial0 = &uart0;
  serial1 = &uart1;
  serial2 = &uart2;
  serial3 = &uart3;
 };

 soc {
  #address-cells = <1>;
  #size-cells = <1>;
  compatible = "simple-bus";
  ranges;
  interrupt-parent = <&intc0>;

  intc0: interrupt-controller@d8140000 {
   compatible = "via,vt8500-intc";
   interrupt-controller;
   reg = <0xd8140000 0x10000>;
   #interrupt-cells = <1>;
  };

  /* Secondary IC cascaded to intc0 */
  intc1: interrupt-controller@d8150000 {
   compatible = "via,vt8500-intc";
   interrupt-controller;
   #interrupt-cells = <1>;
   reg = <0xD8150000 0x10000>;
   interrupts = <56 57 58 59 60 61 62 63>;
  };

  pinctrl: pinctrl@d8110000 {
   compatible = "wm,wm8850-pinctrl";
   reg = <0xd8110000 0x10000>;
   interrupt-controller;
   #interrupt-cells = <2>;
   gpio-controller;
   #gpio-cells = <2>;
  };

  chipid@d8120000 {
   compatible = "via,vt8500-scc-id";
   reg = <0xd8120000 0x4>;
  };

  pmc@d8130000 {
   compatible = "via,vt8500-pmc";
   reg = <0xd8130000 0x1000>;

   clocks {
    #address-cells = <1>;
    #size-cells = <0>;

    ref25: ref25M {
     #clock-cells = <0>;
     compatible = "fixed-clock";
     clock-frequency = <25000000>;
    };

    ref24: ref24M {
     #clock-cells = <0>;
     compatible = "fixed-clock";
     clock-frequency = <24000000>;
    };

    plla: plla {
     #clock-cells = <0>;
     compatible = "wm,wm8850-pll-clock";
     clocks = <&ref24>;
     reg = <0x200>;
    };

    pllb: pllb {
     #clock-cells = <0>;
     compatible = "wm,wm8850-pll-clock";
     clocks = <&ref24>;
     reg = <0x204>;
    };

    pllc: pllc {
     #clock-cells = <0>;
     compatible = "wm,wm8850-pll-clock";
     clocks = <&ref24>;
     reg = <0x208>;
    };

    plld: plld {
     #clock-cells = <0>;
     compatible = "wm,wm8850-pll-clock";
     clocks = <&ref24>;
     reg = <0x20c>;
    };

    plle: plle {
     #clock-cells = <0>;
     compatible = "wm,wm8850-pll-clock";
     clocks = <&ref24>;
     reg = <0x210>;
    };

    pllf: pllf {
     #clock-cells = <0>;
     compatible = "wm,wm8850-pll-clock";
     clocks = <&ref24>;
     reg = <0x214>;
    };

    pllg: pllg {
     #clock-cells = <0>;
     compatible = "wm,wm8850-pll-clock";
     clocks = <&ref24>;
     reg = <0x218>;
    };

    clkarm: arm {
     #clock-cells = <0>;
     compatible = "via,vt8500-device-clock";
     clocks = <&plla>;
     divisor-reg = <0x300>;
    };

    clkahb: ahb {
     #clock-cells = <0>;
     compatible = "via,vt8500-device-clock";
     clocks = <&pllb>;
     divisor-reg = <0x304>;
    };

    clkapb: apb {
     #clock-cells = <0>;
     compatible = "via,vt8500-device-clock";
     clocks = <&pllb>;
     divisor-reg = <0x320>;
    };

    clkddr: ddr {
     #clock-cells = <0>;
     compatible = "via,vt8500-device-clock";
     clocks = <&plld>;
     divisor-reg = <0x310>;
    };

    clkuart0: uart0 {
     #clock-cells = <0>;
     compatible = "via,vt8500-device-clock";
     clocks = <&ref24>;
     enable-reg = <0x254>;
     enable-bit = <24>;
    };

    clkuart1: uart1 {
     #clock-cells = <0>;
     compatible = "via,vt8500-device-clock";
     clocks = <&ref24>;
     enable-reg = <0x254>;
     enable-bit = <25>;
    };

                                clkuart2: uart2 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
                                        clocks = <&ref24>;
                                        enable-reg = <0x254>;
                                        enable-bit = <26>;
                                };

                                clkuart3: uart3 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
                                        clocks = <&ref24>;
                                        enable-reg = <0x254>;
                                        enable-bit = <27>;
                                };

    clkpwm: pwm {
     #clock-cells = <0>;
     compatible = "via,vt8500-device-clock";
     clocks = <&pllb>;
     divisor-reg = <0x350>;
     enable-reg = <0x250>;
     enable-bit = <17>;
    };

    clksdhc: sdhc {
     #clock-cells = <0>;
     compatible = "via,vt8500-device-clock";
     clocks = <&pllb>;
     divisor-reg = <0x330>;
     divisor-mask = <0x3f>;
     enable-reg = <0x250>;
     enable-bit = <0>;
    };
   };
  };

  fb: fb@d8051700 {
   compatible = "wm,wm8505-fb";
   reg = <0xd8051700 0x200>;
  };

  ge_rops@d8050400 {
   compatible = "wm,prizm-ge-rops";
   reg = <0xd8050400 0x100>;
  };

  pwm: pwm@d8220000 {
   #pwm-cells = <3>;
   compatible = "via,vt8500-pwm";
   reg = <0xd8220000 0x100>;
   clocks = <&clkpwm>;
  };

  timer@d8130100 {
   compatible = "via,vt8500-timer";
   reg = <0xd8130100 0x28>;
   interrupts = <36>, <37>, <38>, <39>;
  };

  usb@d8007900 {
   compatible = "via,vt8500-ehci";
   reg = <0xd8007900 0x200>;
   interrupts = <26>;
  };

  usb@d8007b00 {
   compatible = "platform-uhci";
   reg = <0xd8007b00 0x200>;
   interrupts = <26>;
  };

  usb@d8008d00 {
   compatible = "platform-uhci";
   reg = <0xd8008d00 0x200>;
   interrupts = <26>;
  };

  uart0: serial@d8200000 {
   compatible = "via,vt8500-uart";
   reg = <0xd8200000 0x1040>;
   interrupts = <32>;
   clocks = <&clkuart0>;
   status = "disabled";
  };

  uart1: serial@d82b0000 {
   compatible = "via,vt8500-uart";
   reg = <0xd82b0000 0x1040>;
   interrupts = <33>;
   clocks = <&clkuart1>;
   status = "disabled";
  };

                uart2: serial@d8210000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8210000 0x1040>;
                        interrupts = <47>;
                        clocks = <&clkuart2>;
   status = "disabled";
                };

                uart3: serial@d82c0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82c0000 0x1040>;
                        interrupts = <50>;
                        clocks = <&clkuart3>;
   status = "disabled";
                };

  rtc@d8100000 {
   compatible = "via,vt8500-rtc";
   reg = <0xd8100000 0x10000>;
   interrupts = <48>;
  };

  mmc@d800a000 {
   compatible = "wm,wm8505-sdhc";
   reg = <0xd800a000 0x1000>;
   interrupts = <20 21>;
   clocks = <&clksdhc>;
   bus-width = <4>;
   sdon-inverted;
  };

  ethernet@d8004000 {
   compatible = "via,vt8500-rhine";
   reg = <0xd8004000 0x100>;
   interrupts = <10>;
                };

  l2_cache: cache-controller@d9000000 {
   compatible = "arm,pl310-cache";
   reg = <0xd9000000 0x1000>;
   arm,double-linefill = <1>;
   arm,dynamic-clock-gating = <1>;
   arm,shared-override;
   arm,standby-mode = <1>;
   cache-level = <2>;
   cache-unified;
   prefetch-data = <1>;
   prefetch-instr = <1>;
  };
 };
};