/* * OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits - * these are reversed from the bits used on OMAP3+
*/ #define OMAP24XX_PWRDM_POWER_ON 0x0 #define OMAP24XX_PWRDM_POWER_RET 0x1 #define OMAP24XX_PWRDM_POWER_OFF 0x3
/* * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP * hardware register (which are specific to the OMAP2xxx SoCs) to * reset source ID bit shifts (which is an OMAP SoC-independent * enumeration)
*/ staticstruct prm_reset_src_map omap2xxx_prm_reset_src_map[] = {
{ OMAP_GLOBALCOLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
{ OMAP_GLOBALWARM_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
{ OMAP24XX_SECU_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
{ OMAP24XX_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
{ OMAP24XX_SECU_WD_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
{ OMAP24XX_EXTWMPU_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
{ -1, -1 },
};
/** * omap2xxx_prm_read_reset_sources - return the last SoC reset source * * Return a u32 representing the last reset sources of the SoC. The * returned reset source bits are standardized across OMAP SoCs.
*/ static u32 omap2xxx_prm_read_reset_sources(void)
{ struct prm_reset_src_map *p;
u32 r = 0;
u32 v;
v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
p = omap2xxx_prm_reset_src_map; while (p->reg_shift >= 0 && p->std_shift >= 0) { if (v & (1 << p->reg_shift))
r |= 1 << p->std_shift;
p++;
}
return r;
}
/** * omap2xxx_pwrst_to_common_pwrst - convert OMAP2xxx pwrst to common pwrst * @omap2xxx_pwrst: OMAP2xxx hardware power state to convert * * Return the common power state bits corresponding to the OMAP2xxx * hardware power state bits @omap2xxx_pwrst, or -EINVAL upon error.
*/ staticint omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst)
{
u8 pwrst;
switch (omap2xxx_pwrst) { case OMAP24XX_PWRDM_POWER_OFF:
pwrst = PWRDM_POWER_OFF; break; case OMAP24XX_PWRDM_POWER_RET:
pwrst = PWRDM_POWER_RET; break; case OMAP24XX_PWRDM_POWER_ON:
pwrst = PWRDM_POWER_ON; break; default: return -EINVAL;
}
return pwrst;
}
/** * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC * * Set the DPLL reset bit, which should reboot the SoC. This is the * recommended way to restart the SoC. No return value.
*/ staticvoid omap2xxx_prm_dpll_reset(void)
{
omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD,
OMAP2_RM_RSTCTRL); /* OCP barrier */
omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
}
/** * omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module * @module: PRM module to clear wakeups from * @regs: register offset to clear * @wkst_mask: wakeup status mask to clear * * Clears wakeup status bits for a given module, so that the device can * re-enter idle.
*/ staticint omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
{
u32 wkst;
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