Quelle  sa8775p.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2023, Linaro Limited
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
#include <dt-bindings/clock/qcom,sa8775p-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
 interrupt-parent = <&intc>;

 #address-cells = <2>;
 #size-cells = <2>;

 clocks {
  xo_board_clk: xo-board-clk {
   compatible = "fixed-clock";
   #clock-cells = <0>;
  };

  sleep_clk: sleep-clk {
   compatible = "fixed-clock";
   #clock-cells = <0>;
  };
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x0>;
   enable-method = "psci";
   power-domains = <&cpu_pd0>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   next-level-cache = <&l2_0>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
     <&epss_l3_cl0 MASTER_EPSS_L3_APPS
      &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
   l2_0: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
    l3_0: l3-cache {
     compatible = "cache";
     cache-level = <3>;
     cache-unified;
    };
   };
  };

  cpu1: cpu@100 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x100>;
   enable-method = "psci";
   power-domains = <&cpu_pd1>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   next-level-cache = <&l2_1>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
     <&epss_l3_cl0 MASTER_EPSS_L3_APPS
      &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
   l2_1: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu2: cpu@200 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x200>;
   enable-method = "psci";
   power-domains = <&cpu_pd2>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   next-level-cache = <&l2_2>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
     <&epss_l3_cl0 MASTER_EPSS_L3_APPS
      &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
   l2_2: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu3: cpu@300 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x300>;
   enable-method = "psci";
   power-domains = <&cpu_pd3>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   next-level-cache = <&l2_3>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
     <&epss_l3_cl0 MASTER_EPSS_L3_APPS
      &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>;
   l2_3: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu4: cpu@10000 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x10000>;
   enable-method = "psci";
   power-domains = <&cpu_pd4>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 1>;
   next-level-cache = <&l2_4>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
     <&epss_l3_cl1 MASTER_EPSS_L3_APPS
      &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
   l2_4: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_1>;
    l3_1: l3-cache {
     compatible = "cache";
     cache-level = <3>;
     cache-unified;
    };

   };
  };

  cpu5: cpu@10100 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x10100>;
   enable-method = "psci";
   power-domains = <&cpu_pd5>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 1>;
   next-level-cache = <&l2_5>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
     <&epss_l3_cl1 MASTER_EPSS_L3_APPS
      &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
   l2_5: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_1>;
   };
  };

  cpu6: cpu@10200 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x10200>;
   enable-method = "psci";
   power-domains = <&cpu_pd6>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 1>;
   next-level-cache = <&l2_6>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
     <&epss_l3_cl1 MASTER_EPSS_L3_APPS
      &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
   l2_6: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_1>;
   };
  };

  cpu7: cpu@10300 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x10300>;
   enable-method = "psci";
   power-domains = <&cpu_pd7>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 1>;
   next-level-cache = <&l2_7>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
     <&epss_l3_cl1 MASTER_EPSS_L3_APPS
      &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>;
   l2_7: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_1>;
   };
  };

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu0>;
    };

    core1 {
     cpu = <&cpu1>;
    };

    core2 {
     cpu = <&cpu2>;
    };

    core3 {
     cpu = <&cpu3>;
    };
   };

   cluster1 {
    core0 {
     cpu = <&cpu4>;
    };

    core1 {
     cpu = <&cpu5>;
    };

    core2 {
     cpu = <&cpu6>;
    };

    core3 {
     cpu = <&cpu7>;
    };
   };
  };

  idle-states {
   entry-method = "psci";

   gold_cpu_sleep_0: cpu-sleep-0 {
    compatible = "arm,idle-state";
    idle-state-name = "gold-power-collapse";
    arm,psci-suspend-param = <0x40000003>;
    entry-latency-us = <549>;
    exit-latency-us = <901>;
    min-residency-us = <1774>;
    local-timer-stop;
   };

   gold_rail_cpu_sleep_0: cpu-sleep-1 {
    compatible = "arm,idle-state";
    idle-state-name = "gold-rail-power-collapse";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <702>;
    exit-latency-us = <1061>;
    min-residency-us = <4488>;
    local-timer-stop;
   };
  };

  domain-idle-states {
   cluster_sleep_gold: cluster-sleep-0 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x41000044>;
    entry-latency-us = <2752>;
    exit-latency-us = <3048>;
    min-residency-us = <6118>;
   };

   cluster_sleep_apss_rsc_pc: cluster-sleep-1 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x42000144>;
    entry-latency-us = <3263>;
    exit-latency-us = <6562>;
    min-residency-us = <9987>;
   };
  };
 };

 cpu0_opp_table: opp-table-cpu0 {
  compatible = "operating-points-v2";
  opp-shared;

  opp-1267200000 {
   opp-hz = /bits/ 64 <1267200000>;
   opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
  };

  opp-1363200000 {
   opp-hz = /bits/ 64 <1363200000>;
   opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
  };

  opp-1459200000 {
   opp-hz = /bits/ 64 <1459200000>;
   opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
  };

  opp-1536000000 {
   opp-hz = /bits/ 64 <1536000000>;
   opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
  };

  opp-1632000000 {
   opp-hz = /bits/ 64 <1632000000>;
   opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
  };

  opp-1708800000 {
   opp-hz = /bits/ 64 <1708800000>;
   opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
  };

  opp-1785600000 {
   opp-hz = /bits/ 64 <1785600000>;
   opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
  };

  opp-1862400000 {
   opp-hz = /bits/ 64 <1862400000>;
   opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
  };

  opp-1939200000 {
   opp-hz = /bits/ 64 <1939200000>;
   opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
  };

  opp-2016000000 {
   opp-hz = /bits/ 64 <2016000000>;
   opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
  };

  opp-2112000000 {
   opp-hz = /bits/ 64 <2112000000>;
   opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
  };

  opp-2188800000 {
   opp-hz = /bits/ 64 <2188800000>;
   opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
  };

  opp-2265600000 {
   opp-hz = /bits/ 64 <2265600000>;
   opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
  };

  opp-2361600000 {
   opp-hz = /bits/ 64 <2361600000>;
   opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
  };

  opp-2457600000 {
   opp-hz = /bits/ 64 <2457600000>;
   opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
  };

  opp-2553600000 {
   opp-hz = /bits/ 64 <2553600000>;
   opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
  };
 };

 cpu4_opp_table: opp-table-cpu4 {
  compatible = "operating-points-v2";
  opp-shared;

  opp-1267200000 {
   opp-hz = /bits/ 64 <1267200000>;
   opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
  };

  opp-1363200000 {
   opp-hz = /bits/ 64 <1363200000>;
   opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
  };

  opp-1459200000 {
   opp-hz = /bits/ 64 <1459200000>;
   opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
  };

  opp-1536000000 {
   opp-hz = /bits/ 64 <1536000000>;
   opp-peak-kBps = <(1555200 * 4) (921600 * 32)>;
  };

  opp-1632000000 {
   opp-hz = /bits/ 64 <1632000000>;
   opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
  };

  opp-1708800000 {
   opp-hz = /bits/ 64 <1708800000>;
   opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
  };

  opp-1785600000 {
   opp-hz = /bits/ 64 <1785600000>;
   opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
  };

  opp-1862400000 {
   opp-hz = /bits/ 64 <1862400000>;
   opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
  };

  opp-1939200000 {
   opp-hz = /bits/ 64 <1939200000>;
   opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
  };

  opp-2016000000 {
   opp-hz = /bits/ 64 <2016000000>;
   opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>;
  };

  opp-2112000000 {
   opp-hz = /bits/ 64 <2112000000>;
   opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
  };

  opp-2188800000 {
   opp-hz = /bits/ 64 <2188800000>;
   opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
  };

  opp-2265600000 {
   opp-hz = /bits/ 64 <2265600000>;
   opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>;
  };

  opp-2361600000 {
   opp-hz = /bits/ 64 <2361600000>;
   opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
  };

  opp-2457600000 {
   opp-hz = /bits/ 64 <2457600000>;
   opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
  };

  opp-2553600000 {
   opp-hz = /bits/ 64 <2553600000>;
   opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>;
  };
 };

 dummy-sink {
  compatible = "arm,coresight-dummy-sink";

  in-ports {
   port {
    eud_in: endpoint {
     remote-endpoint =
     <&swao_rep_out1>;
    };
   };
  };
 };

 firmware {
  scm {
   compatible = "qcom,scm-sa8775p", "qcom,scm";
   qcom,dload-mode = <&tcsr 0x13000>;
   memory-region = <&tz_ffi_mem>;
  };
 };

 aggre1_noc: interconnect-aggre1-noc {
  compatible = "qcom,sa8775p-aggre1-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 aggre2_noc: interconnect-aggre2-noc {
  compatible = "qcom,sa8775p-aggre2-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 clk_virt: interconnect-clk-virt {
  compatible = "qcom,sa8775p-clk-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 config_noc: interconnect-config-noc {
  compatible = "qcom,sa8775p-config-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 dc_noc: interconnect-dc-noc {
  compatible = "qcom,sa8775p-dc-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 gem_noc: interconnect-gem-noc {
  compatible = "qcom,sa8775p-gem-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 gpdsp_anoc: interconnect-gpdsp-anoc {
  compatible = "qcom,sa8775p-gpdsp-anoc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 lpass_ag_noc: interconnect-lpass-ag-noc {
  compatible = "qcom,sa8775p-lpass-ag-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 mc_virt: interconnect-mc-virt {
  compatible = "qcom,sa8775p-mc-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 mmss_noc: interconnect-mmss-noc {
  compatible = "qcom,sa8775p-mmss-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 nspa_noc: interconnect-nspa-noc {
  compatible = "qcom,sa8775p-nspa-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 nspb_noc: interconnect-nspb-noc {
  compatible = "qcom,sa8775p-nspb-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 pcie_anoc: interconnect-pcie-anoc {
  compatible = "qcom,sa8775p-pcie-anoc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 system_noc: interconnect-system-noc {
  compatible = "qcom,sa8775p-system-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 /* Will be updated by the bootloader. */
 memory@80000000 {
  device_type = "memory";
  reg = <0x0 0x80000000 0x0 0x0>;
 };

 qup_opp_table_100mhz: opp-table-qup100mhz {
  compatible = "operating-points-v2";

  opp-100000000 {
   opp-hz = /bits/ 64 <100000000>;
   required-opps = <&rpmhpd_opp_svs_l1>;
  };
 };

 pmu {
  compatible = "arm,armv8-pmuv3";
  interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";

  cpu_pd0: power-domain-cpu0 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_0_pd>;
   domain-idle-states = <&gold_cpu_sleep_0>,
          <&gold_rail_cpu_sleep_0>;
  };

  cpu_pd1: power-domain-cpu1 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_0_pd>;
   domain-idle-states = <&gold_cpu_sleep_0>,
          <&gold_rail_cpu_sleep_0>;
  };

  cpu_pd2: power-domain-cpu2 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_0_pd>;
   domain-idle-states = <&gold_cpu_sleep_0>,
          <&gold_rail_cpu_sleep_0>;
  };

  cpu_pd3: power-domain-cpu3 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_0_pd>;
   domain-idle-states = <&gold_cpu_sleep_0>,
          <&gold_rail_cpu_sleep_0>;
  };

  cpu_pd4: power-domain-cpu4 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_1_pd>;
   domain-idle-states = <&gold_cpu_sleep_0>,
          <&gold_rail_cpu_sleep_0>;
  };

  cpu_pd5: power-domain-cpu5 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_1_pd>;
   domain-idle-states = <&gold_cpu_sleep_0>,
          <&gold_rail_cpu_sleep_0>;
  };

  cpu_pd6: power-domain-cpu6 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_1_pd>;
   domain-idle-states = <&gold_cpu_sleep_0>,
          <&gold_rail_cpu_sleep_0>;
  };

  cpu_pd7: power-domain-cpu7 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_1_pd>;
   domain-idle-states = <&gold_cpu_sleep_0>,
          <&gold_rail_cpu_sleep_0>;
  };

  cluster_0_pd: power-domain-cluster0 {
   #power-domain-cells = <0>;
   domain-idle-states = <&cluster_sleep_gold>;
   power-domains = <&system_pd>;
  };

  cluster_1_pd: power-domain-cluster1 {
   #power-domain-cells = <0>;
   domain-idle-states = <&cluster_sleep_gold>;
   power-domains = <&system_pd>;
  };

  system_pd: power-domain-system {
   #power-domain-cells = <0>;
   domain-idle-states = <&cluster_sleep_apss_rsc_pc>;
  };
 };

 reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  sail_ss_mem: sail-ss@80000000 {
   reg = <0x0 0x80000000 0x0 0x10000000>;
   no-map;
  };

  hyp_mem: hyp@90000000 {
   reg = <0x0 0x90000000 0x0 0x600000>;
   no-map;
  };

  xbl_boot_mem: xbl-boot@90600000 {
   reg = <0x0 0x90600000 0x0 0x200000>;
   no-map;
  };

  aop_image_mem: aop-image@90800000 {
   reg = <0x0 0x90800000 0x0 0x60000>;
   no-map;
  };

  aop_cmd_db_mem: aop-cmd-db@90860000 {
   compatible = "qcom,cmd-db";
   reg = <0x0 0x90860000 0x0 0x20000>;
   no-map;
  };

  uefi_log: uefi-log@908b0000 {
   reg = <0x0 0x908b0000 0x0 0x10000>;
   no-map;
  };

  ddr_training_checksum: ddr-training-checksum@908c0000 {
   reg = <0x0 0x908c0000 0x0 0x1000>;
   no-map;
  };

  reserved_mem: reserved@908f0000 {
   reg = <0x0 0x908f0000 0x0 0xe000>;
   no-map;
  };

  secdata_apss_mem: secdata-apss@908fe000 {
   reg = <0x0 0x908fe000 0x0 0x2000>;
   no-map;
  };

  smem_mem: smem@90900000 {
   compatible = "qcom,smem";
   reg = <0x0 0x90900000 0x0 0x200000>;
   no-map;
   hwlocks = <&tcsr_mutex 3>;
  };

  tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
   reg = <0x0 0x90c00000 0x0 0x100000>;
   no-map;
  };

  sail_mailbox_mem: sail-ss@90d00000 {
   reg = <0x0 0x90d00000 0x0 0x100000>;
   no-map;
  };

  sail_ota_mem: sail-ss@90e00000 {
   reg = <0x0 0x90e00000 0x0 0x300000>;
   no-map;
  };

  aoss_backup_mem: aoss-backup@91b00000 {
   reg = <0x0 0x91b00000 0x0 0x40000>;
   no-map;
  };

  cpucp_backup_mem: cpucp-backup@91b40000 {
   reg = <0x0 0x91b40000 0x0 0x40000>;
   no-map;
  };

  tz_config_backup_mem: tz-config-backup@91b80000 {
   reg = <0x0 0x91b80000 0x0 0x10000>;
   no-map;
  };

  ddr_training_data_mem: ddr-training-data@91b90000 {
   reg = <0x0 0x91b90000 0x0 0x10000>;
   no-map;
  };

  cdt_data_backup_mem: cdt-data-backup@91ba0000 {
   reg = <0x0 0x91ba0000 0x0 0x1000>;
   no-map;
  };

  tz_ffi_mem: tz-ffi@91c00000 {
   compatible = "shared-dma-pool";
   reg = <0x0 0x91c00000 0x0 0x1400000>;
   no-map;
  };

  lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
   reg = <0x0 0x93b00000 0x0 0xf00000>;
   no-map;
  };

  adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
   reg = <0x0 0x94a00000 0x0 0x800000>;
   no-map;
  };

  pil_camera_mem: pil-camera@95200000 {
   reg = <0x0 0x95200000 0x0 0x500000>;
   no-map;
  };

  pil_adsp_mem: pil-adsp@95c00000 {
   reg = <0x0 0x95c00000 0x0 0x1e00000>;
   no-map;
  };

  pil_gdsp0_mem: pil-gdsp0@97b00000 {
   reg = <0x0 0x97b00000 0x0 0x1e00000>;
   no-map;
  };

  pil_gdsp1_mem: pil-gdsp1@99900000 {
   reg = <0x0 0x99900000 0x0 0x1e00000>;
   no-map;
  };

  pil_cdsp0_mem: pil-cdsp0@9b800000 {
   reg = <0x0 0x9b800000 0x0 0x1e00000>;
   no-map;
  };

  pil_gpu_mem: pil-gpu@9d600000 {
   reg = <0x0 0x9d600000 0x0 0x2000>;
   no-map;
  };

  pil_cdsp1_mem: pil-cdsp1@9d700000 {
   reg = <0x0 0x9d700000 0x0 0x1e00000>;
   no-map;
  };

  pil_cvp_mem: pil-cvp@9f500000 {
   reg = <0x0 0x9f500000 0x0 0x700000>;
   no-map;
  };

  pil_video_mem: pil-video@9fc00000 {
   reg = <0x0 0x9fc00000 0x0 0x700000>;
   no-map;
  };

  audio_mdf_mem: audio-mdf-region@ae000000 {
   reg = <0x0 0xae000000 0x0 0x1000000>;
   no-map;
  };

  firmware_mem: firmware-region@b0000000 {
   reg = <0x0 0xb0000000 0x0 0x800000>;
   no-map;
  };

  hyptz_reserved_mem: hyptz-reserved@beb00000 {
   reg = <0x0 0xbeb00000 0x0 0x11500000>;
   no-map;
  };

  scmi_mem: scmi-region@d0000000 {
   reg = <0x0 0xd0000000 0x0 0x40000>;
   no-map;
  };

  firmware_logs_mem: firmware-logs@d0040000 {
   reg = <0x0 0xd0040000 0x0 0x10000>;
   no-map;
  };

  firmware_audio_mem: firmware-audio@d0050000 {
   reg = <0x0 0xd0050000 0x0 0x4000>;
   no-map;
  };

  firmware_reserved_mem: firmware-reserved@d0054000 {
   reg = <0x0 0xd0054000 0x0 0x9c000>;
   no-map;
  };

  firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
   reg = <0x0 0xd00f0000 0x0 0x10000>;
   no-map;
  };

  tags_mem: tags@d0100000 {
   reg = <0x0 0xd0100000 0x0 0x1200000>;
   no-map;
  };

  qtee_mem: qtee@d1300000 {
   reg = <0x0 0xd1300000 0x0 0x500000>;
   no-map;
  };

  deepsleep_backup_mem: deepsleep-backup@d1800000 {
   reg = <0x0 0xd1800000 0x0 0x100000>;
   no-map;
  };

  trusted_apps_mem: trusted-apps@d1900000 {
   reg = <0x0 0xd1900000 0x0 0x3800000>;
   no-map;
  };

  tz_stat_mem: tz-stat@db100000 {
   reg = <0x0 0xdb100000 0x0 0x100000>;
   no-map;
  };

  cpucp_fw_mem: cpucp-fw@db200000 {
   reg = <0x0 0xdb200000 0x0 0x100000>;
   no-map;
  };
 };

 smp2p-adsp {
  compatible = "qcom,smp2p";
  qcom,smem = <443>, <429>;
  interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <2>;

  smp2p_adsp_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_adsp_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-cdsp0 {
  compatible = "qcom,smp2p";
  qcom,smem = <94>, <432>;
  interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <5>;

  smp2p_cdsp0_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_cdsp0_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-cdsp1 {
  compatible = "qcom,smp2p";
  qcom,smem = <617>, <616>;
  interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <12>;

  smp2p_cdsp1_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_cdsp1_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-gpdsp0 {
  compatible = "qcom,smp2p";
  qcom,smem = <617>, <616>;
  interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <17>;

  smp2p_gpdsp0_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_gpdsp0_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-gpdsp1 {
  compatible = "qcom,smp2p";
  qcom,smem = <617>, <616>;
  interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <18>;

  smp2p_gpdsp1_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_gpdsp1_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 soc: soc@0 {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0 0 0 0 0x10 0>;

  gcc: clock-controller@100000 {
   compatible = "qcom,sa8775p-gcc";
   reg = <0x0 0x00100000 0x0 0xc7018>;
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&sleep_clk>,
     <0>,
     <0>,
     <0>,
     <&usb_0_qmpphy>,
     <&usb_1_qmpphy>,
     <0>,
     <0>,
     <0>,
     <&pcie0_phy>,
     <&pcie1_phy>,
     <0>,
     <0>,
     <0>;
   power-domains = <&rpmhpd SA8775P_CX>;
  };

  ipcc: mailbox@408000 {
   compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
   reg = <0x0 0x00408000 0x0 0x1000>;
   interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-controller;
   #interrupt-cells = <3>;
   #mbox-cells = <2>;
  };

  gpi_dma2: dma-controller@800000  {
   compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
   reg = <0x0 0x00800000 0x0 0x60000>;
   #dma-cells = <3>;
   interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
   dma-channels = <12>;
   dma-channel-mask = <0xfff>;
   iommus = <&apps_smmu 0x5b6 0x0>;
   status = "disabled";
  };

  qupv3_id_2: geniqup@8c0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0x0 0x008c0000 0x0 0x6000>;
   ranges;
   clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
   clock-names = "m-ahb", "s-ahb";
   iommus = <&apps_smmu 0x5a3 0x0>;
   #address-cells = <2>;
   #size-cells = <2>;
   status = "disabled";

   i2c14: i2c@880000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x880000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c14_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
           <&gpi_dma2 1 0 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi14: spi@880000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x880000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi14_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
           <&gpi_dma2 1 0 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart14: serial@880000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x00880000 0x0 0x4000>;
    interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart14_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };

   i2c15: i2c@884000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x884000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c15_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
           <&gpi_dma2 1 1 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi15: spi@884000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x884000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi15_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
           <&gpi_dma2 1 1 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart15: serial@884000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x00884000 0x0 0x4000>;
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart15_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };

   i2c16: i2c@888000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x888000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c16_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
           <&gpi_dma2 1 2 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi16: spi@888000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00888000 0x0 0x4000>;
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi16_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
           <&gpi_dma2 1 2 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart16: serial@888000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x00888000 0x0 0x4000>;
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart16_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };

   i2c17: i2c@88c000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x88c000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c17_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
           <&gpi_dma2 1 3 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi17: spi@88c000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x88c000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi17_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
           <&gpi_dma2 1 3 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart17: serial@88c000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x0088c000 0x0 0x4000>;
    interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart17_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };

   i2c18: i2c@890000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00890000 0x0 0x4000>;
    interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c18_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
           <&gpi_dma2 1 4 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi18: spi@890000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x890000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi18_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
           <&gpi_dma2 1 4 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart18: serial@890000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x00890000 0x0 0x4000>;
    interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart18_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };

   i2c19: i2c@894000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x894000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c19_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
           <&gpi_dma2 1 5 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi19: spi@894000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x894000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi19_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
           <&gpi_dma2 1 5 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart19: serial@894000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x00894000 0x0 0x4000>;
    interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart19_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };

   i2c20: i2c@898000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x898000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c20_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
           <&gpi_dma2 1 6 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi20: spi@898000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x898000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi20_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
           <&gpi_dma2 1 6 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart20: serial@898000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x00898000 0x0 0x4000>;
    interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart20_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };

  };

  gpi_dma0: dma-controller@900000  {
   compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
   reg = <0x0 0x00900000 0x0 0x60000>;
   #dma-cells = <3>;
   interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
   dma-channels = <12>;
   dma-channel-mask = <0xfff>;
   iommus = <&apps_smmu 0x416 0x0>;
   status = "disabled";
  };

  qupv3_id_0: geniqup@9c0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0x0 0x9c0000 0x0 0x6000>;
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   clock-names = "m-ahb", "s-ahb";
   clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
    <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
   iommus = <&apps_smmu 0x403 0x0>;
   status = "disabled";

   i2c0: i2c@980000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x980000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c0_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
           <&gpi_dma0 1 0 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi0: spi@980000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x980000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi0_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
         <&gpi_dma0 1 0 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart0: serial@980000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x980000 0x0 0x4000>;
    interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart0_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };

   i2c1: i2c@984000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x984000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c1_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
           <&gpi_dma0 1 1 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi1: spi@984000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x984000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi1_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
           <&gpi_dma0 1 1 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart1: serial@984000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x984000 0x0 0x4000>;
    interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart1_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };

   i2c2: i2c@988000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x988000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c2_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
           <&gpi_dma0 1 2 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi2: spi@988000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x988000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi2_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
           <&gpi_dma0 1 2 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart2: serial@988000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x988000 0x0 0x4000>;
    interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart2_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };

   i2c3: i2c@98c000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x98c000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c3_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
           <&gpi_dma0 1 3 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi3: spi@98c000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x98c000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi3_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
           <&gpi_dma0 1 3 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart3: serial@98c000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x98c000 0x0 0x4000>;
    interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart3_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };

   i2c4: i2c@990000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x990000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c4_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
           <&gpi_dma0 1 4 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi4: spi@990000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x990000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi4_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
           <&gpi_dma0 1 4 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart4: serial@990000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x990000 0x0 0x4000>;
    interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart4_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };

   i2c5: i2c@994000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x994000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c5_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
           <&gpi_dma0 1 5 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi5: spi@994000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x994000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi5_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
           <&gpi_dma0 1 5 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart5: serial@994000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x994000 0x0 0x4000>;
    interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart5_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    power-domains = <&rpmhpd SA8775P_CX>;
    status = "disabled";
   };
  };

  gpi_dma1: dma-controller@a00000  {
   compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
   reg = <0x0 0x00a00000 0x0 0x60000>;
   #dma-cells = <3>;
   interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
   iommus = <&apps_smmu 0x456 0x0>;
   dma-channels = <12>;
   dma-channel-mask = <0xfff>;
   status = "disabled";
  };

  qupv3_id_1: geniqup@ac0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0x0 0x00ac0000 0x0 0x6000>;
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   clock-names = "m-ahb", "s-ahb";
   clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
   iommus = <&apps_smmu 0x443 0x0>;
   status = "disabled";

   i2c7: i2c@a80000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0xa80000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c7_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
           <&gpi_dma1 1 0 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi7: spi@a80000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0xa80000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi7_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
           <&gpi_dma1 1 0 QCOM_GPI_SPI>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   uart7: serial@a80000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x00a80000 0x0 0x4000>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    pinctrl-0 = <&qup_uart7_default>;
    pinctrl-names = "default";
    interconnect-names = "qup-core", "qup-config";
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
    power-domains = <&rpmhpd SA8775P_CX>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    status = "disabled";
   };

   i2c8: i2c@a84000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0xa84000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_i2c8_default>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
      <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config",
           "qup-memory";
    power-domains = <&rpmhpd SA8775P_CX>;
    dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
           <&gpi_dma1 1 1 QCOM_GPI_I2C>;
    dma-names = "tx",
         "rx";
    status = "disabled";
   };

   spi8: spi@a84000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0xa84000 0x0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_spi8_default>;
    pinctrl-names = "default";
--> --------------------

--> maximum size reached

--> --------------------