| Quellcodebibliothek Statistik Leitseite products/Sources/formale Sprachen/C/Linux/arch/arm64/boot/dts/renesas/ (Open Source Betriebssystem Version 6.17.9©) Datei vom 24.10.2025 mit Größe 57 kB |
|
Quelle r8a779h0.dtsi Sprache: unbekannt |
|
|
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/* * Device Tree Source for the R-Car V4M (R8A779H0) SoC * * Copyright (C) 2023 Renesas Electronics Corp. */ #include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/renesas,r8a779h0-sysc.h> / { compatible = "renesas,r8a779h0"; #address-cells = <2>; #size-cells = <2>; /* External Audio clock - to be overridden by boards that provide it */ audio_clkin: audio_clkin { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* External CAN clock - to be overridden by boards that provide it */ can_clk: can-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <825000>; clock-latency-ns = <500000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <825000>; clock-latency-ns = <500000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&a76_0>; }; core1 { cpu = <&a76_1>; }; core2 { cpu = <&a76_2>; }; core3 { cpu = <&a76_3>; }; }; }; a76_0: cpu@0 { compatible = "arm,cortex-a76"; reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>; operating-points-v2 = <&cluster0_opp>; }; a76_1: cpu@100 { compatible = "arm,cortex-a76"; reg = <0x100>; device_type = "cpu"; power-domains = <&sysc R8A779H0_PD_A1E0D0C1>; next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>; operating-points-v2 = <&cluster0_opp>; }; a76_2: cpu@200 { compatible = "arm,cortex-a76"; reg = <0x200>; device_type = "cpu"; power-domains = <&sysc R8A779H0_PD_A1E0D0C2>; next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>; operating-points-v2 = <&cluster0_opp>; }; a76_3: cpu@300 { compatible = "arm,cortex-a76"; reg = <0x300>; device_type = "cpu"; power-domains = <&sysc R8A779H0_PD_A1E0D0C3>; next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>; operating-points-v2 = <&cluster0_opp>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010000>; local-timer-stop; entry-latency-us = <400>; exit-latency-us = <500>; min-residency-us = <4000>; }; }; L3_CA76: cache-controller { compatible = "cache"; power-domains = <&sysc R8A779H0_PD_A2E0D0>; cache-unified; cache-level = <3>; }; }; extal_clk: extal-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; bootph-all; }; extalr_clk: extalr-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; bootph-all; }; pcie0_clkref: pcie0-clkref { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; }; pmu-a76 { compatible = "arm,cortex-a76-pmu"; interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; /* External SCIF clocks - to be overridden by boards that provide them */ scif_clk: scif-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; scif_clk2: scif-clk2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; rwdt: watchdog@e6020000 { compatible = "renesas,r8a779h0-wdt", "renesas,rcar-gen4-wdt"; reg = <0 0xe6020000 0 0x0c>; interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 907>; status = "disabled"; }; pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a779h0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; bootph-all; }; gpio0: gpio@e6050180 { compatible = "renesas,gpio-r8a779h0", "renesas,rcar-gen4-gpio"; reg = <0 0xe6050180 0 0x54>; interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 0 19>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 915>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 915>; }; gpio1: gpio@e6050980 { compatible = "renesas,gpio-r8a779h0", "renesas,rcar-gen4-gpio"; reg = <0 0xe6050980 0 0x54>; interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 32 30>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 915>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 915>; }; gpio2: gpio@e6058180 { compatible = "renesas,gpio-r8a779h0", "renesas,rcar-gen4-gpio"; reg = <0 0xe6058180 0 0x54>; interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 64 20>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 916>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 916>; }; gpio3: gpio@e6058980 { compatible = "renesas,gpio-r8a779h0", "renesas,rcar-gen4-gpio"; reg = <0 0xe6058980 0 0x54>; interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 916>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 916>; }; gpio4: gpio@e6060180 { compatible = "renesas,gpio-r8a779h0", "renesas,rcar-gen4-gpio"; reg = <0 0xe6060180 0 0x54>; interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 128 25>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 917>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 917>; }; gpio5: gpio@e6060980 { compatible = "renesas,gpio-r8a779h0", "renesas,rcar-gen4-gpio"; reg = <0 0xe6060980 0 0x54>; interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 160 21>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 917>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 917>; }; gpio6: gpio@e6061180 { compatible = "renesas,gpio-r8a779h0", "renesas,rcar-gen4-gpio"; reg = <0 0xe6061180 0 0x54>; interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 192 21>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 917>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 917>; }; gpio7: gpio@e6061980 { compatible = "renesas,gpio-r8a779h0", "renesas,rcar-gen4-gpio"; reg = <0 0xe6061980 0 0x54>; interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 224 21>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 917>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 917>; }; cmt0: timer@e60f0000 { compatible = "renesas,r8a779h0-cmt0", "renesas,rcar-gen4-cmt0"; reg = <0 0xe60f0000 0 0x1004>; interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 910>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 910>; status = "disabled"; }; cmt1: timer@e6130000 { compatible = "renesas,r8a779h0-cmt1", "renesas,rcar-gen4-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 911>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 911>; status = "disabled"; }; cmt2: timer@e6140000 { compatible = "renesas,r8a779h0-cmt1", "renesas,rcar-gen4-cmt1"; reg = <0 0xe6140000 0 0x1004>; interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 912>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 912>; status = "disabled"; }; cmt3: timer@e6148000 { compatible = "renesas,r8a779h0-cmt1", "renesas,rcar-gen4-cmt1"; reg = <0 0xe6148000 0 0x1004>; interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 913>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 913>; status = "disabled"; }; cpg: clock-controller@e6150000 { compatible = "renesas,r8a779h0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; clocks = <&extal_clk>, <&extalr_clk>; clock-names = "extal", "extalr"; #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779h0-rst"; reg = <0 0xe6160000 0 0x4000>; bootph-all; }; sysc: system-controller@e6180000 { compatible = "renesas,r8a779h0-sysc"; reg = <0 0xe6180000 0 0x4000>; #power-domain-cells = <1>; }; tsc: thermal@e6198000 { compatible = "renesas,r8a779h0-thermal"; reg = <0 0xe6198000 0 0x200>, <0 0xe61a0000 0 0x200>; clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 919>; #thermal-sensor-cells = <1>; }; otp: otp@e61be000 { compatible = "renesas,r8a779h0-otp"; reg = <0 0xe61be000 0 0x1000>, <0 0xe61bf000 0 0x1000>; }; intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a779h0", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 611>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 611>; }; tmu0: timer@e61e0000 { compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; reg = <0 0xe61e0000 0 0x30>; interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 713>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 713>; status = "disabled"; }; tmu1: timer@e6fc0000 { compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 714>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 714>; status = "disabled"; }; tmu2: timer@e6fd0000 { compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 715>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 715>; status = "disabled"; }; tmu3: timer@e6fe0000 { compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; reg = <0 0xe6fe0000 0 0x30>; interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 716>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 716>; status = "disabled"; }; tmu4: timer@ffc00000 { compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; reg = <0 0xffc00000 0 0x30>; interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 717>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 717>; status = "disabled"; }; i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779h0", "renesas,rcar-gen4-i2c"; reg = <0 0xe6500000 0 0x40>; interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 518>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 518>; dmas = <&dmac1 0x91>, <&dmac1 0x90>, <&dmac2 0x91>, <&dmac2 0x90>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@e6508000 { compatible = "renesas,i2c-r8a779h0", "renesas,rcar-gen4-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 519>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 519>; dmas = <&dmac1 0x93>, <&dmac1 0x92>, <&dmac2 0x93>, <&dmac2 0x92>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@e6510000 { compatible = "renesas,i2c-r8a779h0", "renesas,rcar-gen4-i2c"; reg = <0 0xe6510000 0 0x40>; interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 520>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 520>; dmas = <&dmac1 0x95>, <&dmac1 0x94>, <&dmac2 0x95>, <&dmac2 0x94>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@e66d0000 { compatible = "renesas,i2c-r8a779h0", "renesas,rcar-gen4-i2c"; reg = <0 0xe66d0000 0 0x40>; interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 521>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 521>; dmas = <&dmac1 0x97>, <&dmac1 0x96>, <&dmac2 0x97>, <&dmac2 0x96>; dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a779h0", "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6540000 0 0x60>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 514>, <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 514>; dmas = <&dmac1 0x31>, <&dmac1 0x30>, <&dmac2 0x31>, <&dmac2 0x30>; dma-names = "tx", "rx", "tx", "rx"; status = "disabled"; }; hscif1: serial@e6550000 { compatible = "renesas,hscif-r8a779h0", "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6550000 0 0x60>; interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 515>, <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 515>; dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; dma-names = "tx", "rx", "tx", "rx"; status = "disabled"; }; hscif2: serial@e6560000 { compatible = "renesas,hscif-r8a779h0", "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6560000 0 0x60>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 516>, <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, <&scif_clk2>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 516>; dmas = <&dmac1 0x35>, <&dmac1 0x34>, <&dmac2 0x35>, <&dmac2 0x34>; dma-names = "tx", "rx", "tx", "rx"; status = "disabled"; }; hscif3: serial@e66a0000 { compatible = "renesas,hscif-r8a779h0", "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe66a0000 0 0x60>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 517>, <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 517>; dmas = <&dmac1 0x37>, <&dmac1 0x36>, <&dmac2 0x37>, <&dmac2 0x36>; dma-names = "tx", "rx", "tx", "rx"; status = "disabled"; }; pciec0: pcie@e65d0000 { compatible = "renesas,r8a779h0-pcie", "renesas,rcar-gen4-pcie"; reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>, <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, <0 0xfe000000 0 0x400000>; reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi", "dma", "sft_ce", "app"; clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; clock-names = "core", "ref"; power-domains = <&sysc R8A779H0_PD_A2PCIPHY>; resets = <&cpg 624>; reset-names = "pwr"; max-link-speed = <4>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>; bus-range = <0x00 0xff>; device_type = "pci"; ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>; dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; snps,enable-cdm-check; status = "disabled"; }; pciec0_ep: pcie-ep@e65d0000 { compatible = "renesas,r8a779h0-pcie-ep", "renesas,rcar-gen4-pcie-ep"; reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>, <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, <0 0xfe000000 0 0x400000>; reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dma", "sft_ce", "app"; clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; clock-names = "core", "ref"; power-domains = <&sysc R8A779H0_PD_A2PCIPHY>; resets = <&cpg 624>; reset-names = "pwr"; max-link-speed = <4>; num-lanes = <2>; max-functions = /bits/ 8 <2>; status = "disabled"; }; canfd: can@e6660000 { compatible = "renesas,r8a779h0-canfd", "renesas,rcar-gen4-canfd"; reg = <0 0xe6660000 0 0x8500>; interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 328>, <&cpg CPG_CORE R8A779H0_CLK_CANFD>, <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A779H0_CLK_CANFD>; assigned-clock-rates = <80000000>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 328>; status = "disabled"; channel0 { status = "disabled"; }; channel1 { status = "disabled"; }; channel2 { status = "disabled"; }; channel3 { status = "disabled"; }; }; avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779h0", "renesas,etheravb-rcar-gen4"; reg = <0 0xe6800000 0 0x1000>; interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15", "ch16", "ch17", "ch18", "ch19", "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 211>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 211>; phy-mode = "rgmii"; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_hc 0>; status = "disabled"; }; avb1: ethernet@e6810000 { compatible = "renesas,etheravb-r8a779h0", "renesas,etheravb-rcar-gen4"; reg = <0 0xe6810000 0 0x1000>; interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15", "ch16", "ch17", "ch18", "ch19", "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 212>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 212>; phy-mode = "rgmii"; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_hc 1>; status = "disabled"; }; avb2: ethernet@e6820000 { compatible = "renesas,etheravb-r8a779h0", "renesas,etheravb-rcar-gen4"; reg = <0 0xe6820000 0 0x1000>; interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15", "ch16", "ch17", "ch18", "ch19", "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 213>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 213>; phy-mode = "rgmii"; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_hc 2>; status = "disabled"; }; pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x10>; #pwm-cells = <2>; clocks = <&cpg CPG_MOD 628>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 628>; status = "disabled"; }; pwm1: pwm@e6e31000 { compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar"; reg = <0 0xe6e31000 0 0x10>; #pwm-cells = <2>; clocks = <&cpg CPG_MOD 628>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 628>; status = "disabled"; }; pwm2: pwm@e6e32000 { compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar"; reg = <0 0xe6e32000 0 0x10>; #pwm-cells = <2>; clocks = <&cpg CPG_MOD 628>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 628>; status = "disabled"; }; pwm3: pwm@e6e33000 { compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar"; reg = <0 0xe6e33000 0 0x10>; #pwm-cells = <2>; clocks = <&cpg CPG_MOD 628>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 628>; status = "disabled"; }; pwm4: pwm@e6e34000 { compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar"; reg = <0 0xe6e34000 0 0x10>; #pwm-cells = <2>; clocks = <&cpg CPG_MOD 628>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 628>; status = "disabled"; }; scif0: serial@e6e60000 { compatible = "renesas,scif-r8a779h0", "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>, <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 702>; dmas = <&dmac1 0x51>, <&dmac1 0x50>, <&dmac2 0x51>, <&dmac2 0x50>; dma-names = "tx", "rx", "tx", "rx"; status = "disabled"; }; scif1: serial@e6e68000 { compatible = "renesas,scif-r8a779h0", "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 703>; dmas = <&dmac1 0x53>, <&dmac1 0x52>, <&dmac2 0x53>, <&dmac2 0x52>; dma-names = "tx", "rx", "tx", "rx"; status = "disabled"; }; scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779h0", "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 704>, <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 704>; dmas = <&dmac1 0x57>, <&dmac1 0x56>, <&dmac2 0x57>, <&dmac2 0x56>; dma-names = "tx", "rx", "tx", "rx"; status = "disabled"; }; scif4: serial@e6c40000 { compatible = "renesas,scif-r8a779h0", "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 705>, <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, <&scif_clk2>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 705>; dmas = <&dmac1 0x59>, <&dmac1 0x58>, <&dmac2 0x59>, <&dmac2 0x58>; dma-names = "tx", "rx", "tx", "rx"; status = "disabled"; }; msiof0: spi@e6e90000 { compatible = "renesas,msiof-r8a779h0", "renesas,rcar-gen4-msiof"; reg = <0 0xe6e90000 0 0x0064>; interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 618>; dmas = <&dmac1 0x41>, <&dmac1 0x40>, <&dmac2 0x41>, <&dmac2 0x40>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 618>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof1: spi@e6ea0000 { compatible = "renesas,msiof-r8a779h0", "renesas,rcar-gen4-msiof"; reg = <0 0xe6ea0000 0 0x0064>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 619>; dmas = <&dmac1 0x43>, <&dmac1 0x42>, <&dmac2 0x43>, <&dmac2 0x42>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 619>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof2: spi@e6c00000 { compatible = "renesas,msiof-r8a779h0", "renesas,rcar-gen4-msiof"; reg = <0 0xe6c00000 0 0x0064>; interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 620>; dmas = <&dmac1 0x45>, <&dmac1 0x44>, <&dmac2 0x45>, <&dmac2 0x44>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 620>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof3: spi@e6c10000 { compatible = "renesas,msiof-r8a779h0", "renesas,rcar-gen4-msiof"; reg = <0 0xe6c10000 0 0x0064>; interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 621>; dmas = <&dmac1 0x47>, <&dmac1 0x46>, <&dmac2 0x47>, <&dmac2 0x46>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 621>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof4: spi@e6c20000 { compatible = "renesas,msiof-r8a779h0", "renesas,rcar-gen4-msiof"; reg = <0 0xe6c20000 0 0x0064>; interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 622>; dmas = <&dmac1 0x49>, <&dmac1 0x48>, <&dmac2 0x49>, <&dmac2 0x48>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 622>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; msiof5: spi@e6c28000 { compatible = "renesas,msiof-r8a779h0", "renesas,rcar-gen4-msiof"; reg = <0 0xe6c28000 0 0x0064>; interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 623>; dmas = <&dmac1 0x4b>, <&dmac1 0x4a>, <&dmac2 0x4b>, <&dmac2 0x4a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 623>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; vin00: video@e6ef0000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 730>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 730>; renesas,id = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin00isp0: endpoint@0 { reg = <0>; remote-endpoint = <&isp0vin00>; }; }; }; }; vin01: video@e6ef1000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 731>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 731>; renesas,id = <1>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin01isp0: endpoint@0 { reg = <0>; remote-endpoint = <&isp0vin01>; }; }; }; }; vin02: video@e6ef2000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 800>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 800>; renesas,id = <2>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin02isp0: endpoint@0 { reg = <0>; remote-endpoint = <&isp0vin02>; }; }; }; }; vin03: video@e6ef3000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6ef3000 0 0x1000>; interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 801>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 801>; renesas,id = <3>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin03isp0: endpoint@0 { reg = <0>; remote-endpoint = <&isp0vin03>; }; }; }; }; vin04: video@e6ef4000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6ef4000 0 0x1000>; interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 802>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 802>; renesas,id = <4>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin04isp0: endpoint@0 { reg = <0>; remote-endpoint = <&isp0vin04>; }; }; }; }; vin05: video@e6ef5000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6ef5000 0 0x1000>; interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 803>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 803>; renesas,id = <5>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin05isp0: endpoint@0 { reg = <0>; remote-endpoint = <&isp0vin05>; }; }; }; }; vin06: video@e6ef6000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6ef6000 0 0x1000>; interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 804>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 804>; renesas,id = <6>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin06isp0: endpoint@0 { reg = <0>; remote-endpoint = <&isp0vin06>; }; }; }; }; vin07: video@e6ef7000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6ef7000 0 0x1000>; interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 805>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 805>; renesas,id = <7>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin07isp0: endpoint@0 { reg = <0>; remote-endpoint = <&isp0vin07>; }; }; }; }; vin08: video@e6ef8000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6ef8000 0 0x1000>; interrupts = <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 806>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 806>; renesas,id = <8>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin08isp1: endpoint@1 { reg = <1>; remote-endpoint = <&isp1vin08>; }; }; }; }; vin09: video@e6ef9000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6ef9000 0 0x1000>; interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 807>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 807>; renesas,id = <9>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin09isp1: endpoint@1 { reg = <1>; remote-endpoint = <&isp1vin09>; }; }; }; }; vin10: video@e6efa000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6efa000 0 0x1000>; interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 808>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 808>; renesas,id = <10>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin10isp1: endpoint@1 { reg = <1>; remote-endpoint = <&isp1vin10>; }; }; }; }; vin11: video@e6efb000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6efb000 0 0x1000>; interrupts = <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 809>; renesas,id = <11>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin11isp1: endpoint@1 { reg = <1>; remote-endpoint = <&isp1vin11>; }; }; }; }; vin12: video@e6efc000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6efc000 0 0x1000>; interrupts = <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 810>; renesas,id = <12>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin12isp1: endpoint@1 { reg = <1>; remote-endpoint = <&isp1vin12>; }; }; }; }; vin13: video@e6efd000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6efd000 0 0x1000>; interrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 811>; renesas,id = <13>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin13isp1: endpoint@1 { reg = <1>; remote-endpoint = <&isp1vin13>; }; }; }; }; vin14: video@e6efe000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6efe000 0 0x1000>; interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 812>; renesas,id = <14>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin14isp1: endpoint@1 { reg = <1>; remote-endpoint = <&isp1vin14>; }; }; }; }; vin15: video@e6eff000 { compatible = "renesas,vin-r8a779h0", "renesas,rcar-gen4-vin"; reg = <0 0xe6eff000 0 0x1000>; interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 813>; renesas,id = <15>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; vin15isp1: endpoint@1 { reg = <1>; remote-endpoint = <&isp1vin15>; }; }; }; }; dmac1: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779h0", "renesas,rcar-gen4-dmac"; reg = <0 0xe7350000 0 0x1000>, <0 0xe7300000 0 0x10000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 709>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 709>; #dma-cells = <1>; dma-channels = <16>; iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac2: dma-controller@e7351000 { compatible = "renesas,dmac-r8a779h0", "renesas,rcar-gen4-dmac"; reg = <0 0xe7351000 0 0x1000>, <0 0xe7310000 0 0x10000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7"; clocks = <&cpg CPG_MOD 710>; clock-names = "fck"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 710>; #dma-cells = <1>; dma-channels = <8>; iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, <&ipmmu_ds0 22>, <&ipmmu_ds0 23>; }; rcar_sound: sound@ec400000 { compatible = "renesas,rcar_sound-r8a779h0", "renesas,rcar_sound-gen4"; reg = <0 0xec400000 0 0x40000>, <0 0xec540000 0 0x1000>, <0 0xec541000 0 0x050>, <0 0xec5a0000 0 0x020>; reg-names = "sdmc", "ssiu", "ssi", "adg"; clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>; clock-names = "ssiu.0", "ssi.0", "clkin"; /* #clock-cells is fixed */ #clock-cells = <0>; /* #sound-dai-cells is fixed */ #sound-dai-cells = <0>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 2926>, <&cpg 2927>; reset-names = "ssiu.0", "ssi.0"; status = "disabled"; rcar_sound,ssiu { ssiu00: ssiu-0 { dmas = <&dmac1 0x6e>, <&dmac1 0x6f>; dma-names = "tx", "rx"; }; ssiu01: ssiu-1 { dmas = <&dmac1 0x6c>, <&dmac1 0x6d>; dma-names = "tx", "rx"; }; ssiu02: ssiu-2 { dmas = <&dmac1 0x6a>, <&dmac1 0x6b>; dma-names = "tx", "rx"; }; ssiu03: ssiu-3 { dmas = <&dmac1 0x68>, <&dmac1 0x69>; dma-names = "tx", "rx"; }; ssiu04: ssiu-4 { dmas = <&dmac1 0x66>, <&dmac1 0x67>; dma-names = "tx", "rx"; }; ssiu05: ssiu-5 { dmas = <&dmac1 0x64>, <&dmac1 0x65>; dma-names = "tx", "rx"; }; ssiu06: ssiu-6 { dmas = <&dmac1 0x62>, <&dmac1 0x63>; dma-names = "tx", "rx"; }; ssiu07: ssiu-7 { dmas = <&dmac1 0x60>, <&dmac1 0x61>; dma-names = "tx", "rx"; }; }; rcar_sound,ssi { ssi0: ssi-0 { interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; }; }; }; mmc0: mmc@ee140000 { compatible = "renesas,sdhi-r8a779h0", "renesas,rcar-gen4-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779H0_CLK_SD0H>; clock-names = "core", "clkh"; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 706>; max-frequency = <200000000>; iommus = <&ipmmu_ds0 32>; status = "disabled"; }; rpc: spi@ee200000 { compatible = "renesas,r8a779h0-rpc-if", "renesas,rcar-gen4-rpc-if"; reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>, <0 0xee208000 0 0x100>; reg-names = "regs", "dirmap", "wbuf"; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 629>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 629>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; ipmmu_rt0: iommu@ee480000 { compatible = "renesas,ipmmu-r8a779h0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee480000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_rt1: iommu@ee4c0000 { compatible = "renesas,ipmmu-r8a779h0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee4c0000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_ds0: iommu@eed00000 { compatible = "renesas,ipmmu-r8a779h0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed00000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_hc: iommu@eed40000 { compatible = "renesas,ipmmu-r8a779h0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed40000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779H0_PD_C4>; #iommu-cells = <1>; }; ipmmu_ir: iommu@eed80000 { compatible = "renesas,ipmmu-r8a779h0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed80000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779H0_PD_C4>; #iommu-cells = <1>; }; ipmmu_vc: iommu@eedc0000 { compatible = "renesas,ipmmu-r8a779h0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeedc0000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779H0_PD_C4>; #iommu-cells = <1>; }; ipmmu_3dg: iommu@eee00000 { compatible = "renesas,ipmmu-r8a779h0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeee00000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779H0_PD_C4>; #iommu-cells = <1>; }; ipmmu_vi0: iommu@eee80000 { compatible = "renesas,ipmmu-r8a779h0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeee80000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779H0_PD_C4>; #iommu-cells = <1>; }; ipmmu_vi1: iommu@eeec0000 { compatible = "renesas,ipmmu-r8a779h0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeeec0000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779H0_PD_C4>; #iommu-cells = <1>; }; ipmmu_vip0: iommu@eef00000 { compatible = "renesas,ipmmu-r8a779h0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeef00000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779H0_PD_C4>; #iommu-cells = <1>; }; ipmmu_mm: iommu@eefc0000 { compatible = "renesas,ipmmu-r8a779h0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeefc0000 0 0x20000>; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; csi40: csi2@fe500000 { compatible = "renesas,r8a779h0-csi2"; reg = <0 0xfe500000 0 0x40000>; interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 331>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; }; port@1 { reg = <1>; csi40isp0: endpoint { remote-endpoint = <&isp0csi40>; }; }; }; }; csi41: csi2@fe540000 { compatible = "renesas,r8a779h0-csi2"; reg = <0 0xfe540000 0 0x40000>; interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 400>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 400>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; }; port@1 { reg = <1>; csi41isp1: endpoint { remote-endpoint = <&isp1csi41>; }; }; }; }; fcpvd0: fcp@fea10000 { compatible = "renesas,fcpv"; reg = <0 0xfea10000 0 0x200>; clocks = <&cpg CPG_MOD 508>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 508>; }; fcpvx0: fcp@fedb0000 { compatible = "renesas,fcpv"; reg = <0 0xfedb0000 0 0x200>; clocks = <&cpg CPG_MOD 1100>; power-domains = <&sysc R8A779H0_PD_A3ISP0>; resets = <&cpg 1100>; iommus = <&ipmmu_vi1 24>; }; vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x8000>; interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 830>; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 830>; renesas,fcp = <&fcpvd0>; }; vspx0: vsp@fedd0000 { compatible = "renesas,vsp2"; reg = <0 0xfedd0000 0 0x8000>; interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 1028>; power-domains = <&sysc R8A779H0_PD_A3ISP0>; resets = <&cpg 1028>; renesas,fcp = <&fcpvx0>; }; du: display@feb00000 { compatible = "renesas,du-r8a779h0"; reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 411>; clock-names = "du.0"; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 411>; reset-names = "du.0"; renesas,vsps = <&vspd0 0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; du_out_dsi0: endpoint { remote-endpoint = <&dsi0_in>; }; }; }; }; isp0: isp@fed00000 { compatible = "renesas,r8a779h0-isp", "renesas,rcar-gen4-isp"; reg = <0 0xfed00000 0 0x10000>, <0 0xfec00000 0 0x100000>; reg-names = "cs", "core"; interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cs", "core"; clocks = <&cpg CPG_MOD 612>, <&cpg CPG_MOD 16>; clock-names = "cs", "core"; power-domains = <&sysc R8A779H0_PD_A3ISP0>; resets = <&cpg 612>, <&cpg 16>; reset-names = "cs", "core"; status = "disabled"; renesas,vspx = <&vspx0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; isp0csi40: endpoint@0 { reg = <0>; remote-endpoint = <&csi40isp0>; }; }; port@1 { reg = <1>; isp0vin00: endpoint { remote-endpoint = <&vin00isp0>; }; }; port@2 { reg = <2>; isp0vin01: endpoint { remote-endpoint = <&vin01isp0>; }; }; port@3 { reg = <3>; isp0vin02: endpoint { remote-endpoint = <&vin02isp0>; }; }; port@4 { reg = <4>; isp0vin03: endpoint { remote-endpoint = <&vin03isp0>; }; }; port@5 { reg = <5>; isp0vin04: endpoint { remote-endpoint = <&vin04isp0>; }; }; port@6 { reg = <6>; isp0vin05: endpoint { remote-endpoint = <&vin05isp0>; }; }; port@7 { reg = <7>; isp0vin06: endpoint { remote-endpoint = <&vin06isp0>; }; }; port@8 { reg = <8>; isp0vin07: endpoint { remote-endpoint = <&vin07isp0>; }; }; }; }; isp1: isp@fed20000 { compatible = "renesas,r8a779h0-isp", "renesas,rcar-gen4-isp"; reg = <0 0xfed20000 0 0x10000>; reg-names = "cs"; interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cs"; clocks = <&cpg CPG_MOD 613>; clock-names = "cs"; power-domains = <&sysc R8A779H0_PD_A3ISP0>; resets = <&cpg 613>; reset-names = "cs"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; isp1csi41: endpoint@1 { reg = <1>; remote-endpoint = <&csi41isp1>; }; }; port@1 { reg = <1>; isp1vin08: endpoint { remote-endpoint = <&vin08isp1>; }; }; port@2 { reg = <2>; isp1vin09: endpoint { remote-endpoint = <&vin09isp1>; }; }; port@3 { reg = <3>; isp1vin10: endpoint { remote-endpoint = <&vin10isp1>; }; }; port@4 { reg = <4>; isp1vin11: endpoint { remote-endpoint = <&vin11isp1>; }; }; port@5 { reg = <5>; isp1vin12: endpoint { remote-endpoint = <&vin12isp1>; }; }; port@6 { reg = <6>; isp1vin13: endpoint { remote-endpoint = <&vin13isp1>; }; }; port@7 { reg = <7>; isp1vin14: endpoint { remote-endpoint = <&vin14isp1>; }; }; port@8 { reg = <8>; isp1vin15: endpoint { remote-endpoint = <&vin15isp1>; }; }; }; }; dsi0: dsi-encoder@fed80000 { compatible = "renesas,r8a779h0-dsi-csi2-tx"; reg = <0 0xfed80000 0 0x10000>; clocks = <&cpg CPG_MOD 415>, <&cpg CPG_CORE R8A779H0_CLK_DSIEXT>, <&cpg CPG_CORE R8A779H0_CLK_DSIREF>; clock-names = "fck", "dsi", "pll"; power-domains = <&sysc R8A779H0_PD_C4>; resets = <&cpg 415>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dsi0_in: endpoint { remote-endpoint = <&du_out_dsi0>; }; }; port@1 { reg = <1>; }; }; }; prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; bootph-all; }; }; thermal-zones { sensor_thermal_cr52: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; trips { sensor1_crit: sensor1-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; }; sensor_thermal_ca76: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; trips { sensor2_crit: sensor2-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; }; [ Dauer der Verarbeitung: 0.30 Sekunden (vorverarbeitet) ] |
2026-04-07