/* * Reads of RNDR set PSTATE.NZCV to 0b0000 on success, * and set PSTATE.NZCV to 0b0100 otherwise.
*/ asmvolatile(
__mrs_s("%0", SYS_RNDR_EL0) "\n" " cset %w1, ne\n"
: "=r" (*v), "=r" (ok)
:
: "cc");
/* * Reads of RNDRRS set PSTATE.NZCV to 0b0000 on success, * and set PSTATE.NZCV to 0b0100 otherwise.
*/ asmvolatile(
__mrs_s("%0", SYS_RNDRRS_EL0) "\n" " cset %w1, ne\n"
: "=r" (*v), "=r" (ok)
:
: "cc");
staticinline size_t __must_check arch_get_random_longs(unsignedlong *v, size_t max_longs)
{ /* * Only support the generic interface after we have detected * the system wide capability, avoiding complexity with the * cpufeature code and with potential scheduling between CPUs * with and without the feature.
*/ if (max_longs && __cpu_has_rng() && __arm64_rndr(v)) return 1; return 0;
}
/* * We prefer the SMCCC call, since its semantics (return actual * hardware backed entropy) is closer to the idea behind this * function here than what even the RNDRSS register provides * (the output of a pseudo RNG freshly seeded by a TRNG).
*/ if (smccc_trng_available) { struct arm_smccc_res res;
/* * RNDRRS is not backed by an entropy source but by a DRBG that is * reseeded after each invocation. This is not a 100% fit but good * enough to implement this API if no other entropy source exists.
*/ if (__cpu_has_rng() && __arm64_rndrrs(v)) return 1;
return 0;
}
staticinlinebool __init __early_cpu_has_rndr(void)
{ /* Open code as we run prior to the first call to cpufeature. */ unsignedlong ftr = read_sysreg_s(SYS_ID_AA64ISAR0_EL1); return (ftr >> ID_AA64ISAR0_EL1_RNDR_SHIFT) & 0xf;
}
#endif/* _ASM_ARCHRANDOM_H */
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