/* Subsystem config/status Video processor */ #define VED_SS_PM0 0x32 /* Subsystem config/status ISP (Image Signal Processor) */ #define ISP_SS_PM0 0x39 /* Subsystem config/status Input/output controller */ #define MIO_SS_PM 0x3B /* Shift bits for getting status for video, isp and i/o */ #define SSS_SHIFT 24
/* Power gate status reg */ #define PWRGT_STATUS 0x61 /* Shift bits for getting status for graphics rendering */ #define RENDER_POS 0 /* Shift bits for getting status for media control */ #define MEDIA_POS 2 /* Shift bits for getting status for Valley View/Baytrail display */ #define VLV_DISPLAY_POS 6
/* Subsystem config/status display for Cherry Trail SOC */ #define CHT_DSP_SSS 0x36 /* Shift bits for getting status for display */ #define CHT_DSP_SSS_POS 16
struct punit_device { char *name; int reg; int sss_pos;
};
for (punit_devp = punit_dev; punit_devp->name; punit_devp++) { /* Skip MIO, it is on till the very last moment */ if (punit_devp->reg == MIO_SS_PM) continue;
status = iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ,
punit_devp->reg, &punit_pwr_status); if (status) {
pr_err("%s read failed\n", punit_devp->name);
} else {
dstate = (punit_pwr_status >> punit_devp->sss_pos) & 3; if (!dstate)
pr_err("%s is in D0 prior to s2idle\n", punit_devp->name);
}
}
}
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