/** * struct drm_dp_link_train - link training state information * @request: currently requested settings * @adjust: adjustments requested by sink * @pattern: currently requested training pattern * @clock_recovered: flag to track if clock recovery has completed * @channel_equalized: flag to track if channel equalization has completed
*/ struct drm_dp_link_train { struct drm_dp_link_train_set request; struct drm_dp_link_train_set adjust;
unsignedint pattern;
bool clock_recovered; bool channel_equalized;
};
/** * struct drm_dp_link - DP link capabilities and configuration * @revision: DP specification revision supported on the link * @max_rate: maximum clock rate supported on the link * @max_lanes: maximum number of lanes supported on the link * @caps: capabilities supported on the link (see &drm_dp_link_caps) * @aux_rd_interval: AUX read interval to use for training (in microseconds) * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...) * @rate: currently configured link rate * @lanes: currently configured number of lanes * @rates: additional supported link rates in kHz (eDP 1.4) * @num_rates: number of additional supported link rates (eDP 1.4)
*/ struct drm_dp_link { unsignedchar revision; unsignedint max_rate; unsignedint max_lanes;
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