Quelle  roce_hsi.h   Sprache: C

/*
 * Broadcom NetXtreme-E RoCE driver.
 *
 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * BSD license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Description: RoCE HSI File - Autogenerated
 */

#ifndef __BNXT_RE_HSI_H__
#define __BNXT_RE_HSI_H__

/* include linux/bnxt/hsi.h */
#include <linux/bnxt/hsi.h>

/* tx_doorbell (size:32b/4B) */
struct tx_doorbell {
 __le32 key_idx;
 #define TX_DOORBELL_IDX_MASK 0xffffffUL
 #define TX_DOORBELL_IDX_SFT 0
 #define TX_DOORBELL_KEY_MASK 0xf0000000UL
 #define TX_DOORBELL_KEY_SFT 28
 #define TX_DOORBELL_KEY_TX    (0x0UL << 28)
 #define TX_DOORBELL_KEY_LAST TX_DOORBELL_KEY_TX
};

/* rx_doorbell (size:32b/4B) */
struct rx_doorbell {
 __le32 key_idx;
 #define RX_DOORBELL_IDX_MASK 0xffffffUL
 #define RX_DOORBELL_IDX_SFT 0
 #define RX_DOORBELL_KEY_MASK 0xf0000000UL
 #define RX_DOORBELL_KEY_SFT 28
 #define RX_DOORBELL_KEY_RX    (0x1UL << 28)
 #define RX_DOORBELL_KEY_LAST RX_DOORBELL_KEY_RX
};

/* cmpl_doorbell (size:32b/4B) */
struct cmpl_doorbell {
 __le32 key_mask_valid_idx;
 #define CMPL_DOORBELL_IDX_MASK      0xffffffUL
 #define CMPL_DOORBELL_IDX_SFT       0
 #define CMPL_DOORBELL_IDX_VALID     0x4000000UL
 #define CMPL_DOORBELL_MASK          0x8000000UL
 #define CMPL_DOORBELL_KEY_MASK      0xf0000000UL
 #define CMPL_DOORBELL_KEY_SFT       28
 #define CMPL_DOORBELL_KEY_CMPL        (0x2UL << 28)
 #define CMPL_DOORBELL_KEY_LAST       CMPL_DOORBELL_KEY_CMPL
};

/* status_doorbell (size:32b/4B) */
struct status_doorbell {
 __le32 key_idx;
 #define STATUS_DOORBELL_IDX_MASK 0xffffffUL
 #define STATUS_DOORBELL_IDX_SFT 0
 #define STATUS_DOORBELL_KEY_MASK 0xf0000000UL
 #define STATUS_DOORBELL_KEY_SFT 28
 #define STATUS_DOORBELL_KEY_STAT  (0x3UL << 28)
 #define STATUS_DOORBELL_KEY_LAST STATUS_DOORBELL_KEY_STAT
};

/* cmdq_init (size:128b/16B) */
struct cmdq_init {
 __le64 cmdq_pbl;
 __le16 cmdq_size_cmdq_lvl;
 #define CMDQ_INIT_CMDQ_LVL_MASK 0x3UL
 #define CMDQ_INIT_CMDQ_LVL_SFT  0
 #define CMDQ_INIT_CMDQ_SIZE_MASK 0xfffcUL
 #define CMDQ_INIT_CMDQ_SIZE_SFT 2
 __le16 creq_ring_id;
 __le32 prod_idx;
};

/* cmdq_base (size:128b/16B) */
struct cmdq_base {
 u8 opcode;
 #define CMDQ_BASE_OPCODE_CREATE_QP              0x1UL
 #define CMDQ_BASE_OPCODE_DESTROY_QP             0x2UL
 #define CMDQ_BASE_OPCODE_MODIFY_QP              0x3UL
 #define CMDQ_BASE_OPCODE_QUERY_QP               0x4UL
 #define CMDQ_BASE_OPCODE_CREATE_SRQ             0x5UL
 #define CMDQ_BASE_OPCODE_DESTROY_SRQ            0x6UL
 #define CMDQ_BASE_OPCODE_QUERY_SRQ              0x8UL
 #define CMDQ_BASE_OPCODE_CREATE_CQ              0x9UL
 #define CMDQ_BASE_OPCODE_DESTROY_CQ             0xaUL
 #define CMDQ_BASE_OPCODE_RESIZE_CQ              0xcUL
 #define CMDQ_BASE_OPCODE_ALLOCATE_MRW           0xdUL
 #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY         0xeUL
 #define CMDQ_BASE_OPCODE_REGISTER_MR            0xfUL
 #define CMDQ_BASE_OPCODE_DEREGISTER_MR          0x10UL
 #define CMDQ_BASE_OPCODE_ADD_GID                0x11UL
 #define CMDQ_BASE_OPCODE_DELETE_GID             0x12UL
 #define CMDQ_BASE_OPCODE_MODIFY_GID             0x17UL
 #define CMDQ_BASE_OPCODE_QUERY_GID              0x18UL
 #define CMDQ_BASE_OPCODE_CREATE_QP1             0x13UL
 #define CMDQ_BASE_OPCODE_DESTROY_QP1            0x14UL
 #define CMDQ_BASE_OPCODE_CREATE_AH              0x15UL
 #define CMDQ_BASE_OPCODE_DESTROY_AH             0x16UL
 #define CMDQ_BASE_OPCODE_INITIALIZE_FW          0x80UL
 #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW        0x81UL
 #define CMDQ_BASE_OPCODE_STOP_FUNC              0x82UL
 #define CMDQ_BASE_OPCODE_QUERY_FUNC             0x83UL
 #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES     0x84UL
 #define CMDQ_BASE_OPCODE_READ_CONTEXT           0x85UL
 #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST 0x86UL
 #define CMDQ_BASE_OPCODE_READ_VF_MEMORY         0x87UL
 #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST    0x88UL
 #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY  0x89UL
 #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS          0x8aUL
 #define CMDQ_BASE_OPCODE_QUERY_VERSION          0x8bUL
 #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC         0x8cUL
 #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC          0x8dUL
 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS       0x8eUL
 #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE     0x8fUL
 #define CMDQ_BASE_OPCODE_MODIFY_CQ              0x90UL
 #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND        0x91UL
 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT   0x92UL
 #define CMDQ_BASE_OPCODE_LAST                  CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
};

/* creq_base (size:128b/16B) */
struct creq_base {
 u8 type;
 #define CREQ_BASE_TYPE_MASK      0x3fUL
 #define CREQ_BASE_TYPE_SFT       0
 #define CREQ_BASE_TYPE_QP_EVENT    0x38UL
 #define CREQ_BASE_TYPE_FUNC_EVENT  0x3aUL
 #define CREQ_BASE_TYPE_LAST       CREQ_BASE_TYPE_FUNC_EVENT
 u8 reserved56[7];
 u8 v;
 #define CREQ_BASE_V     0x1UL
 u8 event;
 u8 reserved48[6];
};

/* cmdq_query_version (size:128b/16B) */
struct cmdq_query_version {
 u8 opcode;
 #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 0x8bUL
 #define CMDQ_QUERY_VERSION_OPCODE_LAST         CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
};

/* creq_query_version_resp (size:128b/16B) */
struct creq_query_version_resp {
 u8 type;
 #define CREQ_QUERY_VERSION_RESP_TYPE_MASK    0x3fUL
 #define CREQ_QUERY_VERSION_RESP_TYPE_SFT     0
 #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_QUERY_VERSION_RESP_TYPE_LAST     CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 u8 fw_maj;
 u8 fw_minor;
 u8 fw_bld;
 u8 fw_rsvd;
 u8 v;
 #define CREQ_QUERY_VERSION_RESP_V     0x1UL
 u8 event;
 #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 0x8bUL
 #define CREQ_QUERY_VERSION_RESP_EVENT_LAST         \
  CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION
 __le16 reserved16;
 u8 intf_maj;
 u8 intf_minor;
 u8 intf_bld;
 u8 intf_rsvd;
};

/* cmdq_initialize_fw (size:896b/112B) */
struct cmdq_initialize_fw {
 u8 opcode;
 #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 0x80UL
 #define CMDQ_INITIALIZE_FW_OPCODE_LAST         CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW
 u8 cmd_size;
 __le16 flags;
 #define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT          0x1UL
 #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED     0x2UL
 #define CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED    0x8UL
 #define CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT   0x10UL
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 u8 qpc_pg_size_qpc_lvl;
 #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK      0xfUL
 #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT       0
 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0       0x0UL
 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1       0x1UL
 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2       0x2UL
 #define CMDQ_INITIALIZE_FW_QPC_LVL_LAST       CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2
 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK  0xf0UL
 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT   4
 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K   (0x0UL << 4)
 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K   (0x1UL << 4)
 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K  (0x2UL << 4)
 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M   (0x3UL << 4)
 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M   (0x4UL << 4)
 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G   (0x5UL << 4)
 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_LAST   CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G
 u8 mrw_pg_size_mrw_lvl;
 #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK      0xfUL
 #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT       0
 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0       0x0UL
 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1       0x1UL
 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2       0x2UL
 #define CMDQ_INITIALIZE_FW_MRW_LVL_LAST       CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2
 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK  0xf0UL
 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT   4
 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K   (0x0UL << 4)
 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K   (0x1UL << 4)
 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K  (0x2UL << 4)
 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M   (0x3UL << 4)
 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M   (0x4UL << 4)
 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G   (0x5UL << 4)
 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_LAST   CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G
 u8 srq_pg_size_srq_lvl;
 #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK      0xfUL
 #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT       0
 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0       0x0UL
 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1       0x1UL
 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2       0x2UL
 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST       CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2
 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK  0xf0UL
 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT   4
 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K   (0x0UL << 4)
 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K   (0x1UL << 4)
 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K  (0x2UL << 4)
 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M   (0x3UL << 4)
 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M   (0x4UL << 4)
 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G   (0x5UL << 4)
 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_LAST   CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G
 u8 cq_pg_size_cq_lvl;
 #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK      0xfUL
 #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT       0
 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0       0x0UL
 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1       0x1UL
 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2       0x2UL
 #define CMDQ_INITIALIZE_FW_CQ_LVL_LAST       CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2
 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK  0xf0UL
 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT   4
 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K   (0x0UL << 4)
 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K   (0x1UL << 4)
 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K  (0x2UL << 4)
 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M   (0x3UL << 4)
 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M   (0x4UL << 4)
 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G   (0x5UL << 4)
 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_LAST   CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G
 u8 tqm_pg_size_tqm_lvl;
 #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK      0xfUL
 #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT       0
 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0       0x0UL
 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1       0x1UL
 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2       0x2UL
 #define CMDQ_INITIALIZE_FW_TQM_LVL_LAST       CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2
 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK  0xf0UL
 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT   4
 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K   (0x0UL << 4)
 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K   (0x1UL << 4)
 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K  (0x2UL << 4)
 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M   (0x3UL << 4)
 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M   (0x4UL << 4)
 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G   (0x5UL << 4)
 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_LAST   CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G
 u8 tim_pg_size_tim_lvl;
 #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK      0xfUL
 #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT       0
 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0       0x0UL
 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1       0x1UL
 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2       0x2UL
 #define CMDQ_INITIALIZE_FW_TIM_LVL_LAST       CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2
 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK  0xf0UL
 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT   4
 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K   (0x0UL << 4)
 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K   (0x1UL << 4)
 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K  (0x2UL << 4)
 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M   (0x3UL << 4)
 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M   (0x4UL << 4)
 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G   (0x5UL << 4)
 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST   CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G
 __le16 log2_dbr_pg_size;
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK   0xfUL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT    0
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K    0x0UL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K    0x1UL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K   0x2UL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K   0x3UL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K   0x4UL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K  0x5UL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K  0x6UL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K  0x7UL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M    0x8UL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M    0x9UL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M    0xaUL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M    0xbUL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M   0xcUL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M   0xdUL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M   0xeUL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M  0xfUL
 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST    \
  CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M
 #define CMDQ_INITIALIZE_FW_RSVD_MASK               0xfff0UL
 #define CMDQ_INITIALIZE_FW_RSVD_SFT                4
 __le64 qpc_page_dir;
 __le64 mrw_page_dir;
 __le64 srq_page_dir;
 __le64 cq_page_dir;
 __le64 tqm_page_dir;
 __le64 tim_page_dir;
 __le32 number_of_qp;
 __le32 number_of_mrw;
 __le32 number_of_srq;
 __le32 number_of_cq;
 __le32 max_qp_per_vf;
 __le32 max_mrw_per_vf;
 __le32 max_srq_per_vf;
 __le32 max_cq_per_vf;
 __le32 max_gid_per_vf;
 __le32 stat_ctx_id;
};

/* creq_initialize_fw_resp (size:128b/16B) */
struct creq_initialize_fw_resp {
 u8 type;
 #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK    0x3fUL
 #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT     0
 #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_INITIALIZE_FW_RESP_TYPE_LAST     CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 reserved32;
 u8 v;
 #define CREQ_INITIALIZE_FW_RESP_V     0x1UL
 u8 event;
 #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 0x80UL
 #define CREQ_INITIALIZE_FW_RESP_EVENT_LAST         \
  CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW
 u8 reserved48[6];
};

/* cmdq_deinitialize_fw (size:128b/16B) */
struct cmdq_deinitialize_fw {
 u8 opcode;
 #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 0x81UL
 #define CMDQ_DEINITIALIZE_FW_OPCODE_LAST           \
  CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
};

/* creq_deinitialize_fw_resp (size:128b/16B) */
struct creq_deinitialize_fw_resp {
 u8 type;
 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK    0x3fUL
 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT     0
 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_LAST     CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 reserved32;
 u8 v;
 #define CREQ_DEINITIALIZE_FW_RESP_V     0x1UL
 u8 event;
 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 0x81UL
 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_LAST           \
  CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW
 u8 reserved48[6];
};

/* cmdq_create_qp (size:832b/104B) */
struct cmdq_create_qp {
 u8 opcode;
 #define CMDQ_CREATE_QP_OPCODE_CREATE_QP 0x1UL
 #define CMDQ_CREATE_QP_OPCODE_LAST     CMDQ_CREATE_QP_OPCODE_CREATE_QP
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le64 qp_handle;
 __le32 qp_flags;
 #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED                   0x1UL
 #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION           0x2UL
 #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE       0x4UL
 #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED             0x8UL
 #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED 0x10UL
 #define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED 0x20UL
 #define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA  0x40UL
 #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED          0x80UL
 #define CMDQ_CREATE_QP_QP_FLAGS_EXPRESS_MODE_ENABLED       0x100UL
 #define CMDQ_CREATE_QP_QP_FLAGS_STEERING_TAG_VALID         0x200UL
 #define CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED  0x400UL
 #define CMDQ_CREATE_QP_QP_FLAGS_LAST                      \
  CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED
 u8 type;
 #define CMDQ_CREATE_QP_TYPE_RC            0x2UL
 #define CMDQ_CREATE_QP_TYPE_UD            0x4UL
 #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL
 #define CMDQ_CREATE_QP_TYPE_GSI           0x7UL
 #define CMDQ_CREATE_QP_TYPE_LAST         CMDQ_CREATE_QP_TYPE_GSI
 u8 sq_pg_size_sq_lvl;
 #define CMDQ_CREATE_QP_SQ_LVL_MASK      0xfUL
 #define CMDQ_CREATE_QP_SQ_LVL_SFT       0
 #define CMDQ_CREATE_QP_SQ_LVL_LVL_0       0x0UL
 #define CMDQ_CREATE_QP_SQ_LVL_LVL_1       0x1UL
 #define CMDQ_CREATE_QP_SQ_LVL_LVL_2       0x2UL
 #define CMDQ_CREATE_QP_SQ_LVL_LAST       CMDQ_CREATE_QP_SQ_LVL_LVL_2
 #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK  0xf0UL
 #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT   4
 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K   (0x0UL << 4)
 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K   (0x1UL << 4)
 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K  (0x2UL << 4)
 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M   (0x3UL << 4)
 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M   (0x4UL << 4)
 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G   (0x5UL << 4)
 #define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST   CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G
 u8 rq_pg_size_rq_lvl;
 #define CMDQ_CREATE_QP_RQ_LVL_MASK      0xfUL
 #define CMDQ_CREATE_QP_RQ_LVL_SFT       0
 #define CMDQ_CREATE_QP_RQ_LVL_LVL_0       0x0UL
 #define CMDQ_CREATE_QP_RQ_LVL_LVL_1       0x1UL
 #define CMDQ_CREATE_QP_RQ_LVL_LVL_2       0x2UL
 #define CMDQ_CREATE_QP_RQ_LVL_LAST       CMDQ_CREATE_QP_RQ_LVL_LVL_2
 #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK  0xf0UL
 #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT   4
 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K   (0x0UL << 4)
 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K   (0x1UL << 4)
 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K  (0x2UL << 4)
 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M   (0x3UL << 4)
 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M   (0x4UL << 4)
 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G   (0x5UL << 4)
 #define CMDQ_CREATE_QP_RQ_PG_SIZE_LAST   CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G
 u8 unused_0;
 __le32 dpi;
 __le32 sq_size;
 __le32 rq_size;
 __le16 sq_fwo_sq_sge;
 #define CMDQ_CREATE_QP_SQ_SGE_MASK 0xfUL
 #define CMDQ_CREATE_QP_SQ_SGE_SFT 0
 #define CMDQ_CREATE_QP_SQ_FWO_MASK 0xfff0UL
 #define CMDQ_CREATE_QP_SQ_FWO_SFT 4
 __le16 rq_fwo_rq_sge;
 #define CMDQ_CREATE_QP_RQ_SGE_MASK 0xfUL
 #define CMDQ_CREATE_QP_RQ_SGE_SFT 0
 #define CMDQ_CREATE_QP_RQ_FWO_MASK 0xfff0UL
 #define CMDQ_CREATE_QP_RQ_FWO_SFT 4
 __le32 scq_cid;
 __le32 rcq_cid;
 __le32 srq_cid;
 __le32 pd_id;
 __le64 sq_pbl;
 __le64 rq_pbl;
 __le64 irrq_addr;
 __le64 orrq_addr;
 __le32 request_xid;
 __le16 steering_tag;
 __le16 reserved16;
};

/* creq_create_qp_resp (size:128b/16B) */
struct creq_create_qp_resp {
 u8 type;
 #define CREQ_CREATE_QP_RESP_TYPE_MASK    0x3fUL
 #define CREQ_CREATE_QP_RESP_TYPE_SFT     0
 #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_CREATE_QP_RESP_TYPE_LAST     CREQ_CREATE_QP_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_CREATE_QP_RESP_V     0x1UL
 u8 event;
 #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 0x1UL
 #define CREQ_CREATE_QP_RESP_EVENT_LAST     CREQ_CREATE_QP_RESP_EVENT_CREATE_QP
 u8 optimized_transmit_enabled;
 u8 reserved48[5];
};

/* cmdq_destroy_qp (size:192b/24B) */
struct cmdq_destroy_qp {
 u8 opcode;
 #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 0x2UL
 #define CMDQ_DESTROY_QP_OPCODE_LAST      CMDQ_DESTROY_QP_OPCODE_DESTROY_QP
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le32 qp_cid;
 __le32 unused_0;
};

/* creq_destroy_qp_resp (size:128b/16B) */
struct creq_destroy_qp_resp {
 u8 type;
 #define CREQ_DESTROY_QP_RESP_TYPE_MASK    0x3fUL
 #define CREQ_DESTROY_QP_RESP_TYPE_SFT     0
 #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_DESTROY_QP_RESP_TYPE_LAST     CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_DESTROY_QP_RESP_V     0x1UL
 u8 event;
 #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 0x2UL
 #define CREQ_DESTROY_QP_RESP_EVENT_LAST      CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP
 u8 reserved48[6];
};

/* cmdq_modify_qp (size:1024b/128B) */
struct cmdq_modify_qp {
 u8 opcode;
 #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 0x3UL
 #define CMDQ_MODIFY_QP_OPCODE_LAST     CMDQ_MODIFY_QP_OPCODE_MODIFY_QP
 u8 cmd_size;
 __le16 flags;
  #define CMDQ_MODIFY_QP_FLAGS_SRQ_USED       0x1UL
 __le16 cookie;
 u8 resp_size;
 u8 qp_type;
 #define CMDQ_MODIFY_QP_QP_TYPE_RC            0x2UL
 #define CMDQ_MODIFY_QP_QP_TYPE_UD            0x4UL
 #define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE 0x6UL
 #define CMDQ_MODIFY_QP_QP_TYPE_GSI           0x7UL
 #define CMDQ_MODIFY_QP_QP_TYPE_LAST         CMDQ_MODIFY_QP_QP_TYPE_GSI
 __le64 resp_addr;
 __le32 modify_mask;
 #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE                   0x1UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY     0x2UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS                  0x4UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY                    0x8UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY                    0x10UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID                    0x20UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL              0x40UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX              0x80UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT               0x100UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS           0x200UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC                0x400UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE      0x800UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU                0x1000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT                 0x2000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT               0x4000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY               0x8000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN                  0x10000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC           0x20000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER           0x40000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN                  0x80000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC      0x100000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE                 0x200000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE                 0x400000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE                  0x800000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE                  0x1000000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA         0x2000000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID              0x4000000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC                 0x8000000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID                 0x10000000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC               0x20000000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN                 0x40000000UL
 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP                0x80000000UL
 __le32 qp_cid;
 u8 network_type_en_sqd_async_notify_new_state;
 #define CMDQ_MODIFY_QP_NEW_STATE_MASK          0xfUL
 #define CMDQ_MODIFY_QP_NEW_STATE_SFT           0
 #define CMDQ_MODIFY_QP_NEW_STATE_RESET           0x0UL
 #define CMDQ_MODIFY_QP_NEW_STATE_INIT            0x1UL
 #define CMDQ_MODIFY_QP_NEW_STATE_RTR             0x2UL
 #define CMDQ_MODIFY_QP_NEW_STATE_RTS             0x3UL
 #define CMDQ_MODIFY_QP_NEW_STATE_SQD             0x4UL
 #define CMDQ_MODIFY_QP_NEW_STATE_SQE             0x5UL
 #define CMDQ_MODIFY_QP_NEW_STATE_ERR             0x6UL
 #define CMDQ_MODIFY_QP_NEW_STATE_LAST           CMDQ_MODIFY_QP_NEW_STATE_ERR
 #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY     0x10UL
 #define CMDQ_MODIFY_QP_UNUSED1                 0x20UL
 #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK       0xc0UL
 #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT        6
 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1       (0x0UL << 6)
 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4  (0x2UL << 6)
 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6  (0x3UL << 6)
 #define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST        CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6
 u8 access;
 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK 0xffUL
 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0
 #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE   0x1UL
 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE  0x2UL
 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ   0x4UL
 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL
 __le16 pkey;
 __le32 qkey;
 __le32 dgid[4];
 __le32 flow_label;
 __le16 sgid_index;
 u8 hop_limit;
 u8 traffic_class;
 __le16 dest_mac[3];
 u8 tos_dscp_tos_ecn;
 #define CMDQ_MODIFY_QP_TOS_ECN_MASK 0x3UL
 #define CMDQ_MODIFY_QP_TOS_ECN_SFT  0
 #define CMDQ_MODIFY_QP_TOS_DSCP_MASK 0xfcUL
 #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2
 u8 path_mtu_pingpong_push_enable;
 #define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE     0x1UL
 #define CMDQ_MODIFY_QP_UNUSED3_MASK             0xeUL
 #define CMDQ_MODIFY_QP_UNUSED3_SFT              1
 #define CMDQ_MODIFY_QP_PATH_MTU_MASK            0xf0UL
 #define CMDQ_MODIFY_QP_PATH_MTU_SFT             4
 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256           (0x0UL << 4)
 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512           (0x1UL << 4)
 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024          (0x2UL << 4)
 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048          (0x3UL << 4)
 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096          (0x4UL << 4)
 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192          (0x5UL << 4)
 #define CMDQ_MODIFY_QP_PATH_MTU_LAST             CMDQ_MODIFY_QP_PATH_MTU_MTU_8192
 u8 timeout;
 u8 retry_cnt;
 u8 rnr_retry;
 u8 min_rnr_timer;
 __le32 rq_psn;
 __le32 sq_psn;
 u8 max_rd_atomic;
 u8 max_dest_rd_atomic;
 __le16 enable_cc;
 #define CMDQ_MODIFY_QP_ENABLE_CC     0x1UL
 #define CMDQ_MODIFY_QP_UNUSED15_MASK 0xfffeUL
 #define CMDQ_MODIFY_QP_UNUSED15_SFT  1
 __le32 sq_size;
 __le32 rq_size;
 __le16 sq_sge;
 __le16 rq_sge;
 __le32 max_inline_data;
 __le32 dest_qp_id;
 __le32 pingpong_push_dpi;
 __le16 src_mac[3];
 __le16 vlan_pcp_vlan_dei_vlan_id;
 #define CMDQ_MODIFY_QP_VLAN_ID_MASK 0xfffUL
 #define CMDQ_MODIFY_QP_VLAN_ID_SFT  0
 #define CMDQ_MODIFY_QP_VLAN_DEI     0x1000UL
 #define CMDQ_MODIFY_QP_VLAN_PCP_MASK 0xe000UL
 #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13
 __le64 irrq_addr;
 __le64 orrq_addr;
 __le32 ext_modify_mask;
 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX     0x1UL
 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID     0x2UL
 __le32 ext_stats_ctx_id;
 __le16 schq_id;
 __le16 unused_0;
 __le32 reserved32;
};

/* creq_modify_qp_resp (size:128b/16B) */
struct creq_modify_qp_resp {
 u8 type;
 #define CREQ_MODIFY_QP_RESP_TYPE_MASK    0x3fUL
 #define CREQ_MODIFY_QP_RESP_TYPE_SFT     0
 #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_MODIFY_QP_RESP_TYPE_LAST     CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_MODIFY_QP_RESP_V     0x1UL
 u8 event;
 #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 0x3UL
 #define CREQ_MODIFY_QP_RESP_EVENT_LAST     CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP
 u8 pingpong_push_state_index_enabled;
 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED     0x1UL
 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK  0xeUL
 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT   1
 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE       0x10UL
 u8 reserved8;
 __le32 lag_src_mac;
};

/* cmdq_query_qp (size:192b/24B) */
struct cmdq_query_qp {
 u8 opcode;
 #define CMDQ_QUERY_QP_OPCODE_QUERY_QP 0x4UL
 #define CMDQ_QUERY_QP_OPCODE_LAST    CMDQ_QUERY_QP_OPCODE_QUERY_QP
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le32 qp_cid;
 __le32 unused_0;
};

/* creq_query_qp_resp (size:128b/16B) */
struct creq_query_qp_resp {
 u8 type;
 #define CREQ_QUERY_QP_RESP_TYPE_MASK    0x3fUL
 #define CREQ_QUERY_QP_RESP_TYPE_SFT     0
 #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_QUERY_QP_RESP_TYPE_LAST     CREQ_QUERY_QP_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 size;
 u8 v;
 #define CREQ_QUERY_QP_RESP_V     0x1UL
 u8 event;
 #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 0x4UL
 #define CREQ_QUERY_QP_RESP_EVENT_LAST    CREQ_QUERY_QP_RESP_EVENT_QUERY_QP
 u8 reserved48[6];
};

/* creq_query_qp_resp_sb (size:832b/104B) */
struct creq_query_qp_resp_sb {
 u8 opcode;
 #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 0x4UL
 #define CREQ_QUERY_QP_RESP_SB_OPCODE_LAST    CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP
 u8 status;
 __le16 cookie;
 __le16 flags;
 u8 resp_size;
 u8 reserved8;
 __le32 xid;
 u8 en_sqd_async_notify_state;
 #define CREQ_QUERY_QP_RESP_SB_STATE_MASK              0xfUL
 #define CREQ_QUERY_QP_RESP_SB_STATE_SFT               0
 #define CREQ_QUERY_QP_RESP_SB_STATE_RESET               0x0UL
 #define CREQ_QUERY_QP_RESP_SB_STATE_INIT                0x1UL
 #define CREQ_QUERY_QP_RESP_SB_STATE_RTR                 0x2UL
 #define CREQ_QUERY_QP_RESP_SB_STATE_RTS                 0x3UL
 #define CREQ_QUERY_QP_RESP_SB_STATE_SQD                 0x4UL
 #define CREQ_QUERY_QP_RESP_SB_STATE_SQE                 0x5UL
 #define CREQ_QUERY_QP_RESP_SB_STATE_ERR                 0x6UL
 #define CREQ_QUERY_QP_RESP_SB_STATE_LAST               CREQ_QUERY_QP_RESP_SB_STATE_ERR
 #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY     0x10UL
 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK            0xe0UL
 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_SFT             5
 u8 access;
 #define \
 CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK\
  0xffUL
 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT\
  0
 #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE 0x1UL
 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE 0x2UL
 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ 0x4UL
 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC 0x8UL
 __le16 pkey;
 __le32 qkey;
 __le32 reserved32;
 __le32 dgid[4];
 __le32 flow_label;
 __le16 sgid_index;
 u8 hop_limit;
 u8 traffic_class;
 __le16 dest_mac[3];
 __le16 path_mtu_dest_vlan_id;
 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK 0xfffUL
 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0
 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK    0xf000UL
 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT     12
 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256   (0x0UL << 12)
 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512   (0x1UL << 12)
 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024  (0x2UL << 12)
 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048  (0x3UL << 12)
 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096  (0x4UL << 12)
 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192  (0x5UL << 12)
 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_LAST     CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192
 u8 timeout;
 u8 retry_cnt;
 u8 rnr_retry;
 u8 min_rnr_timer;
 __le32 rq_psn;
 __le32 sq_psn;
 u8 max_rd_atomic;
 u8 max_dest_rd_atomic;
 u8 tos_dscp_tos_ecn;
 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK 0x3UL
 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT  0
 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK 0xfcUL
 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2
 u8 enable_cc;
 #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC     0x1UL
 __le32 sq_size;
 __le32 rq_size;
 __le16 sq_sge;
 __le16 rq_sge;
 __le32 max_inline_data;
 __le32 dest_qp_id;
 __le16 port_id;
 u8 unused_0;
 u8 stat_collection_id;
 __le16 src_mac[3];
 __le16 vlan_pcp_vlan_dei_vlan_id;
 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK 0xfffUL
 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT  0
 #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI     0x1000UL
 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK 0xe000UL
 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13
};

/* cmdq_query_qp_extend (size:192b/24B) */
struct cmdq_query_qp_extend {
 u8 opcode;
 #define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 0x91UL
 #define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 num_qps;
 __le64 resp_addr;
 __le32 function_id;
 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK  0xffUL
 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT   0
 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK  0xffff00UL
 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_SFT   8
 #define CMDQ_QUERY_QP_EXTEND_VF_VALID     0x1000000UL
 __le32 current_index;
};

/* creq_query_qp_extend_resp (size:128b/16B) */
struct creq_query_qp_extend_resp {
 u8 type;
 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK    0x3fUL
 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT     0
 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_LAST     CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 size;
 u8 v;
 #define CREQ_QUERY_QP_EXTEND_RESP_V     0x1UL
 u8 event;
 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 0x91UL
 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND
 __le16 reserved16;
 __le32 current_index;
};

/* creq_query_qp_extend_resp_sb (size:384b/48B) */
struct creq_query_qp_extend_resp_sb {
 u8 opcode;
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 0x91UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_LAST \
  CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND
 u8 status;
 __le16 cookie;
 __le16 flags;
 u8 resp_size;
 u8 reserved8;
 __le32 xid;
 u8 state;
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK  0xfUL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT   0
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET   0x0UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT    0x1UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR     0x2UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS     0x3UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD     0x4UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE     0x5UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR     0x6UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_LAST   CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK 0xf0UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_SFT 4
 u8 reserved_8;
 __le16 port_id;
 __le32 qkey;
 __le16 sgid_index;
 u8 network_type;
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1      0x0UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 0x2UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 0x3UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_LAST \
  CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6
 u8 unused_0;
 __le32 dgid[4];
 __le32 dest_qp_id;
 u8 stat_collection_id;
 u8 reservred_8;
 __le16 reserved_16;
};

/* creq_query_qp_extend_resp_sb_tlv (size:512b/64B) */
struct creq_query_qp_extend_resp_sb_tlv {
 __le16 cmd_discr;
 u8 reserved_8b;
 u8 tlv_flags;
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE         0x1UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST      0x0UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST  0x1UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED     0x2UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO    (0x0UL << 1)
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES   (0x1UL << 1)
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \
  CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
 __le16 tlv_type;
 __le16 length;
 u8 total_size;
 u8 reserved56[7];
 u8 opcode;
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 0x91UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_LAST \
  CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND
 u8 status;
 __le16 cookie;
 __le16 flags;
 u8 resp_size;
 u8 reserved8;
 __le32 xid;
 u8 state;
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK  0xfUL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT   0
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET   0x0UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT    0x1UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR     0x2UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS     0x3UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD     0x4UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE     0x5UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR     0x6UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_LAST \
  CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK 0xf0UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_SFT 4
 u8 reserved_8;
 __le16 port_id;
 __le32 qkey;
 __le16 sgid_index;
 u8 network_type;
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1      0x0UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 0x2UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 0x3UL
 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_LAST \
  CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6
 u8 unused_0;
 __le32 dgid[4];
 __le32 dest_qp_id;
 u8 stat_collection_id;
 u8 reservred_8;
 __le16 reserved_16;
};

/* cmdq_create_srq (size:448b/56B) */
struct cmdq_create_srq {
 u8 opcode;
 #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 0x5UL
 #define CMDQ_CREATE_SRQ_OPCODE_LAST      CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ
 u8 cmd_size;
 __le16 flags;
 #define CMDQ_CREATE_SRQ_FLAGS_STEERING_TAG_VALID 0x1UL
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le64 srq_handle;
 __le16 pg_size_lvl;
 #define CMDQ_CREATE_SRQ_LVL_MASK      0x3UL
 #define CMDQ_CREATE_SRQ_LVL_SFT       0
 #define CMDQ_CREATE_SRQ_LVL_LVL_0       0x0UL
 #define CMDQ_CREATE_SRQ_LVL_LVL_1       0x1UL
 #define CMDQ_CREATE_SRQ_LVL_LVL_2       0x2UL
 #define CMDQ_CREATE_SRQ_LVL_LAST       CMDQ_CREATE_SRQ_LVL_LVL_2
 #define CMDQ_CREATE_SRQ_PG_SIZE_MASK  0x1cUL
 #define CMDQ_CREATE_SRQ_PG_SIZE_SFT   2
 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K   (0x0UL << 2)
 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K   (0x1UL << 2)
 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K  (0x2UL << 2)
 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M   (0x3UL << 2)
 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M   (0x4UL << 2)
 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G   (0x5UL << 2)
 #define CMDQ_CREATE_SRQ_PG_SIZE_LAST   CMDQ_CREATE_SRQ_PG_SIZE_PG_1G
 #define CMDQ_CREATE_SRQ_UNUSED11_MASK 0xffe0UL
 #define CMDQ_CREATE_SRQ_UNUSED11_SFT  5
 __le16 eventq_id;
 #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK 0xfffUL
 #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0
 #define CMDQ_CREATE_SRQ_UNUSED4_MASK  0xf000UL
 #define CMDQ_CREATE_SRQ_UNUSED4_SFT   12
 __le16 srq_size;
 __le16 srq_fwo;
 __le32 dpi;
 __le32 pd_id;
 __le64 pbl;
 __le16 steering_tag;
 u8 reserved48[6];
};

/* creq_create_srq_resp (size:128b/16B) */
struct creq_create_srq_resp {
 u8 type;
 #define CREQ_CREATE_SRQ_RESP_TYPE_MASK    0x3fUL
 #define CREQ_CREATE_SRQ_RESP_TYPE_SFT     0
 #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_CREATE_SRQ_RESP_TYPE_LAST     CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_CREATE_SRQ_RESP_V     0x1UL
 u8 event;
 #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 0x5UL
 #define CREQ_CREATE_SRQ_RESP_EVENT_LAST      CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ
 u8 reserved48[6];
};

/* cmdq_destroy_srq (size:192b/24B) */
struct cmdq_destroy_srq {
 u8 opcode;
 #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 0x6UL
 #define CMDQ_DESTROY_SRQ_OPCODE_LAST       CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le32 srq_cid;
 __le32 unused_0;
};

/* creq_destroy_srq_resp (size:128b/16B) */
struct creq_destroy_srq_resp {
 u8 type;
 #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK    0x3fUL
 #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT     0
 #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_DESTROY_SRQ_RESP_TYPE_LAST     CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_DESTROY_SRQ_RESP_V     0x1UL
 u8 event;
 #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 0x6UL
 #define CREQ_DESTROY_SRQ_RESP_EVENT_LAST       CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ
 __le16 enable_for_arm[3];
 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK       0xffffUL
 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT        0
 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK 0x30000UL
 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16
};

/* cmdq_query_srq (size:192b/24B) */
struct cmdq_query_srq {
 u8 opcode;
 #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 0x8UL
 #define CMDQ_QUERY_SRQ_OPCODE_LAST     CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le32 srq_cid;
 __le32 unused_0;
};

/* creq_query_srq_resp (size:128b/16B) */
struct creq_query_srq_resp {
 u8 type;
 #define CREQ_QUERY_SRQ_RESP_TYPE_MASK    0x3fUL
 #define CREQ_QUERY_SRQ_RESP_TYPE_SFT     0
 #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_QUERY_SRQ_RESP_TYPE_LAST     CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 size;
 u8 v;
 #define CREQ_QUERY_SRQ_RESP_V     0x1UL
 u8 event;
 #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 0x8UL
 #define CREQ_QUERY_SRQ_RESP_EVENT_LAST     CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ
 u8 reserved48[6];
};

/* creq_query_srq_resp_sb (size:256b/32B) */
struct creq_query_srq_resp_sb {
 u8 opcode;
 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 0x8UL
 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_LAST     CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ
 u8 status;
 __le16 cookie;
 __le16 flags;
 u8 resp_size;
 u8 reserved8;
 __le32 xid;
 __le16 srq_limit;
 __le16 reserved16;
 __le32 data[4];
};

/* cmdq_create_cq (size:448b/56B) */
struct cmdq_create_cq {
 u8 opcode;
 #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 0x9UL
 #define CMDQ_CREATE_CQ_OPCODE_LAST     CMDQ_CREATE_CQ_OPCODE_CREATE_CQ
 u8 cmd_size;
 __le16 flags;
 #define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION     0x1UL
 #define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID                0x2UL
 #define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE                  0x4UL
 #define CMDQ_CREATE_CQ_FLAGS_COALESCING_VALID                  0x8UL
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le64 cq_handle;
 __le32 pg_size_lvl;
 #define CMDQ_CREATE_CQ_LVL_MASK      0x3UL
 #define CMDQ_CREATE_CQ_LVL_SFT       0
 #define CMDQ_CREATE_CQ_LVL_LVL_0       0x0UL
 #define CMDQ_CREATE_CQ_LVL_LVL_1       0x1UL
 #define CMDQ_CREATE_CQ_LVL_LVL_2       0x2UL
 #define CMDQ_CREATE_CQ_LVL_LAST       CMDQ_CREATE_CQ_LVL_LVL_2
 #define CMDQ_CREATE_CQ_PG_SIZE_MASK  0x1cUL
 #define CMDQ_CREATE_CQ_PG_SIZE_SFT   2
 #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K   (0x0UL << 2)
 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K   (0x1UL << 2)
 #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K  (0x2UL << 2)
 #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M   (0x3UL << 2)
 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M   (0x4UL << 2)
 #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G   (0x5UL << 2)
 #define CMDQ_CREATE_CQ_PG_SIZE_LAST   CMDQ_CREATE_CQ_PG_SIZE_PG_1G
 #define CMDQ_CREATE_CQ_UNUSED27_MASK 0xffffffe0UL
 #define CMDQ_CREATE_CQ_UNUSED27_SFT  5
 __le32 cq_fco_cnq_id;
 #define CMDQ_CREATE_CQ_CNQ_ID_MASK 0xfffUL
 #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0
 #define CMDQ_CREATE_CQ_CQ_FCO_MASK 0xfffff000UL
 #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12
 __le32 dpi;
 __le32 cq_size;
 __le64 pbl;
 __le16 steering_tag;
 u8 reserved48[2];
 __le32  coalescing;
 #define CMDQ_CREATE_CQ_BUF_MAXTIME_MASK          0x1ffUL
 #define CMDQ_CREATE_CQ_BUF_MAXTIME_SFT           0
 #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_MASK        0x3e00UL
 #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_SFT         9
 #define CMDQ_CREATE_CQ_DURING_MAXBUF_MASK        0x7c000UL
 #define CMDQ_CREATE_CQ_DURING_MAXBUF_SFT         14
 #define CMDQ_CREATE_CQ_ENABLE_RING_IDLE_MODE     0x80000UL
 #define CMDQ_CREATE_CQ_UNUSED12_MASK             0xfff00000UL
 #define CMDQ_CREATE_CQ_UNUSED12_SFT              20
 __le64  reserved64;
};

/* creq_create_cq_resp (size:128b/16B) */
struct creq_create_cq_resp {
 u8 type;
 #define CREQ_CREATE_CQ_RESP_TYPE_MASK    0x3fUL
 #define CREQ_CREATE_CQ_RESP_TYPE_SFT     0
 #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_CREATE_CQ_RESP_TYPE_LAST     CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_CREATE_CQ_RESP_V     0x1UL
 u8 event;
 #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 0x9UL
 #define CREQ_CREATE_CQ_RESP_EVENT_LAST     CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ
 u8 reserved48[6];
};

/* cmdq_destroy_cq (size:192b/24B) */
struct cmdq_destroy_cq {
 u8 opcode;
 #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 0xaUL
 #define CMDQ_DESTROY_CQ_OPCODE_LAST      CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le32 cq_cid;
 __le32 unused_0;
};

/* creq_destroy_cq_resp (size:128b/16B) */
struct creq_destroy_cq_resp {
 u8 type;
 #define CREQ_DESTROY_CQ_RESP_TYPE_MASK    0x3fUL
 #define CREQ_DESTROY_CQ_RESP_TYPE_SFT     0
 #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_DESTROY_CQ_RESP_TYPE_LAST     CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_DESTROY_CQ_RESP_V     0x1UL
 u8 event;
 #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 0xaUL
 #define CREQ_DESTROY_CQ_RESP_EVENT_LAST      CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ
 __le16 cq_arm_lvl;
 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK 0x3UL
 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0
 __le16 total_cnq_events;
 __le16 reserved16;
};

/* cmdq_resize_cq (size:320b/40B) */
struct cmdq_resize_cq {
 u8 opcode;
 #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 0xcUL
 #define CMDQ_RESIZE_CQ_OPCODE_LAST     CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le32 cq_cid;
 __le32 new_cq_size_pg_size_lvl;
 #define CMDQ_RESIZE_CQ_LVL_MASK        0x3UL
 #define CMDQ_RESIZE_CQ_LVL_SFT         0
 #define CMDQ_RESIZE_CQ_LVL_LVL_0         0x0UL
 #define CMDQ_RESIZE_CQ_LVL_LVL_1         0x1UL
 #define CMDQ_RESIZE_CQ_LVL_LVL_2         0x2UL
 #define CMDQ_RESIZE_CQ_LVL_LAST         CMDQ_RESIZE_CQ_LVL_LVL_2
 #define CMDQ_RESIZE_CQ_PG_SIZE_MASK    0x1cUL
 #define CMDQ_RESIZE_CQ_PG_SIZE_SFT     2
 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K     (0x0UL << 2)
 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K     (0x1UL << 2)
 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K    (0x2UL << 2)
 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M     (0x3UL << 2)
 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M     (0x4UL << 2)
 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G     (0x5UL << 2)
 #define CMDQ_RESIZE_CQ_PG_SIZE_LAST     CMDQ_RESIZE_CQ_PG_SIZE_PG_1G
 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK 0x1fffffe0UL
 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5
 __le64 new_pbl;
 __le32 new_cq_fco;
 __le32 unused_0;
};

/* creq_resize_cq_resp (size:128b/16B) */
struct creq_resize_cq_resp {
 u8 type;
 #define CREQ_RESIZE_CQ_RESP_TYPE_MASK    0x3fUL
 #define CREQ_RESIZE_CQ_RESP_TYPE_SFT     0
 #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_RESIZE_CQ_RESP_TYPE_LAST     CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_RESIZE_CQ_RESP_V     0x1UL
 u8 event;
 #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 0xcUL
 #define CREQ_RESIZE_CQ_RESP_EVENT_LAST     CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ
 u8 reserved48[6];
};

/* cmdq_allocate_mrw (size:256b/32B) */
struct cmdq_allocate_mrw {
 u8 opcode;
 #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 0xdUL
 #define CMDQ_ALLOCATE_MRW_OPCODE_LAST        CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le64 mrw_handle;
 u8 mrw_flags;
 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK     0xfUL
 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT      0
 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR         0x0UL
 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR        0x1UL
 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1   0x2UL
 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A  0x3UL
 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B  0x4UL
 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST      CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B
 #define CMDQ_ALLOCATE_MRW_STEERING_TAG_VALID     0x10UL
 #define CMDQ_ALLOCATE_MRW_UNUSED4_MASK       0xe0UL
 #define CMDQ_ALLOCATE_MRW_UNUSED4_SFT        5
 u8 access;
 #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY     0x20UL
 __le16 steering_tag;
 __le32 pd_id;
};

/* creq_allocate_mrw_resp (size:128b/16B) */
struct creq_allocate_mrw_resp {
 u8 type;
 #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK    0x3fUL
 #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT     0
 #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_ALLOCATE_MRW_RESP_TYPE_LAST     CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_ALLOCATE_MRW_RESP_V     0x1UL
 u8 event;
 #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 0xdUL
 #define CREQ_ALLOCATE_MRW_RESP_EVENT_LAST        CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW
 u8 reserved48[6];
};

/* cmdq_deallocate_key (size:192b/24B) */
struct cmdq_deallocate_key {
 u8 opcode;
 #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 0xeUL
 #define CMDQ_DEALLOCATE_KEY_OPCODE_LAST          CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 u8 mrw_flags;
 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK     0xfUL
 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT      0
 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR         0x0UL
 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR        0x1UL
 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1   0x2UL
 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A  0x3UL
 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B  0x4UL
 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_LAST      CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B
 #define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK       0xf0UL
 #define CMDQ_DEALLOCATE_KEY_UNUSED4_SFT        4
 u8 unused24[3];
 __le32 key;
};

/* creq_deallocate_key_resp (size:128b/16B) */
struct creq_deallocate_key_resp {
 u8 type;
 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK    0x3fUL
 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT     0
 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_LAST     CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_DEALLOCATE_KEY_RESP_V     0x1UL
 u8 event;
 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 0xeUL
 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY
 __le16 reserved16;
 __le32 bound_window_info;
};

/* cmdq_register_mr (size:448b/56B) */
struct cmdq_register_mr {
 u8 opcode;
 #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 0xfUL
 #define CMDQ_REGISTER_MR_OPCODE_LAST       CMDQ_REGISTER_MR_OPCODE_REGISTER_MR
 u8 cmd_size;
 __le16 flags;
 #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR   0x1UL
 #define CMDQ_REGISTER_MR_FLAGS_STEERING_TAG_VALID 0x2UL
 #define CMDQ_REGISTER_MR_FLAGS_ENABLE_RO  0x4UL
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 u8 log2_pg_size_lvl;
 #define CMDQ_REGISTER_MR_LVL_MASK            0x3UL
 #define CMDQ_REGISTER_MR_LVL_SFT             0
 #define CMDQ_REGISTER_MR_LVL_LVL_0             0x0UL
 #define CMDQ_REGISTER_MR_LVL_LVL_1             0x1UL
 #define CMDQ_REGISTER_MR_LVL_LVL_2             0x2UL
 #define CMDQ_REGISTER_MR_LVL_LAST             CMDQ_REGISTER_MR_LVL_LVL_2
 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK   0x7cUL
 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT    2
 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K    (0xcUL << 2)
 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K    (0xdUL << 2)
 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K   (0x10UL << 2)
 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K  (0x12UL << 2)
 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M    (0x14UL << 2)
 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M    (0x15UL << 2)
 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M    (0x16UL << 2)
 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G    (0x1eUL << 2)
 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST    CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G
 #define CMDQ_REGISTER_MR_UNUSED1             0x80UL
 u8 access;
 #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE       0x1UL
 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ       0x2UL
 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE      0x4UL
 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC     0x8UL
 #define CMDQ_REGISTER_MR_ACCESS_MW_BIND           0x10UL
 #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED        0x20UL
 __le16 log2_pbl_pg_size;
 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK   0x1fUL
 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT    0
 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K    0xcUL
 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K    0xdUL
 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K   0x10UL
 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K  0x12UL
 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M    0x14UL
 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M    0x15UL
 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M    0x16UL
 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G    0x1eUL
 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST    CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G
 #define CMDQ_REGISTER_MR_UNUSED11_MASK           0xffe0UL
 #define CMDQ_REGISTER_MR_UNUSED11_SFT            5
 __le32 key;
 __le64 pbl;
 __le64 va;
 __le64 mr_size;
 __le16  steering_tag;
 u8      reserved48[6];
};

/* creq_register_mr_resp (size:128b/16B) */
struct creq_register_mr_resp {
 u8 type;
 #define CREQ_REGISTER_MR_RESP_TYPE_MASK    0x3fUL
 #define CREQ_REGISTER_MR_RESP_TYPE_SFT     0
 #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_REGISTER_MR_RESP_TYPE_LAST     CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_REGISTER_MR_RESP_V     0x1UL
 u8 event;
 #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 0xfUL
 #define CREQ_REGISTER_MR_RESP_EVENT_LAST       CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR
 u8 reserved48[6];
};

/* cmdq_deregister_mr (size:192b/24B) */
struct cmdq_deregister_mr {
 u8 opcode;
 #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 0x10UL
 #define CMDQ_DEREGISTER_MR_OPCODE_LAST         CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le32 lkey;
 __le32 unused_0;
};

/* creq_deregister_mr_resp (size:128b/16B) */
struct creq_deregister_mr_resp {
 u8 type;
 #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK    0x3fUL
 #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT     0
 #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_DEREGISTER_MR_RESP_TYPE_LAST     CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_DEREGISTER_MR_RESP_V     0x1UL
 u8 event;
 #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 0x10UL
 #define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR
 __le16 reserved16;
 __le32 bound_windows;
};

/* cmdq_add_gid (size:384b/48B) */
struct cmdq_add_gid {
 u8 opcode;
 #define CMDQ_ADD_GID_OPCODE_ADD_GID 0x11UL
 #define CMDQ_ADD_GID_OPCODE_LAST   CMDQ_ADD_GID_OPCODE_ADD_GID
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __be32 gid[4];
 __be16 src_mac[3];
 __le16 vlan;
 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK          0xffffUL
 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT           0
 #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK                       0xfffUL
 #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT                        0
 #define CMDQ_ADD_GID_VLAN_TPID_MASK                          0x7000UL
 #define CMDQ_ADD_GID_VLAN_TPID_SFT                           12
 #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8                       (0x0UL << 12)
 #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100                       (0x1UL << 12)
 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100                       (0x2UL << 12)
 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200                       (0x3UL << 12)
 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300                       (0x4UL << 12)
 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1                       (0x5UL << 12)
 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2                       (0x6UL << 12)
 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3                       (0x7UL << 12)
 #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3
 #define CMDQ_ADD_GID_VLAN_VLAN_EN                            0x8000UL
 __le16 ipid;
 __le16 stats_ctx;
 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK                0xffffUL
 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT                 0
 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK                                0x7fffUL
 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT                                 0
 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID                                  0x8000UL
 __le32 unused_0;
};

/* creq_add_gid_resp (size:128b/16B) */
struct creq_add_gid_resp {
 u8 type;
 #define CREQ_ADD_GID_RESP_TYPE_MASK    0x3fUL
 #define CREQ_ADD_GID_RESP_TYPE_SFT     0
 #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_ADD_GID_RESP_TYPE_LAST     CREQ_ADD_GID_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_ADD_GID_RESP_V     0x1UL
 u8 event;
 #define CREQ_ADD_GID_RESP_EVENT_ADD_GID 0x11UL
 #define CREQ_ADD_GID_RESP_EVENT_LAST   CREQ_ADD_GID_RESP_EVENT_ADD_GID
 u8 reserved48[6];
};

/* cmdq_delete_gid (size:192b/24B) */
struct cmdq_delete_gid {
 u8 opcode;
 #define CMDQ_DELETE_GID_OPCODE_DELETE_GID 0x12UL
 #define CMDQ_DELETE_GID_OPCODE_LAST      CMDQ_DELETE_GID_OPCODE_DELETE_GID
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le16 gid_index;
 u8 unused_0[6];
};

/* creq_delete_gid_resp (size:128b/16B) */
struct creq_delete_gid_resp {
 u8 type;
 #define CREQ_DELETE_GID_RESP_TYPE_MASK    0x3fUL
 #define CREQ_DELETE_GID_RESP_TYPE_SFT     0
 #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_DELETE_GID_RESP_TYPE_LAST     CREQ_DELETE_GID_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_DELETE_GID_RESP_V     0x1UL
 u8 event;
 #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 0x12UL
 #define CREQ_DELETE_GID_RESP_EVENT_LAST      CREQ_DELETE_GID_RESP_EVENT_DELETE_GID
 u8 reserved48[6];
};

/* cmdq_modify_gid (size:384b/48B) */
struct cmdq_modify_gid {
 u8 opcode;
 #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 0x17UL
 #define CMDQ_MODIFY_GID_OPCODE_LAST      CMDQ_MODIFY_GID_OPCODE_MODIFY_GID
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __be32 gid[4];
 __be16 src_mac[3];
 __le16 vlan;
 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK  0xfffUL
 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT   0
 #define CMDQ_MODIFY_GID_VLAN_TPID_MASK     0x7000UL
 #define CMDQ_MODIFY_GID_VLAN_TPID_SFT      12
 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8  (0x0UL << 12)
 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100  (0x1UL << 12)
 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100  (0x2UL << 12)
 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200  (0x3UL << 12)
 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300  (0x4UL << 12)
 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1  (0x5UL << 12)
 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2  (0x6UL << 12)
 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3  (0x7UL << 12)
 #define CMDQ_MODIFY_GID_VLAN_TPID_LAST      CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3
 #define CMDQ_MODIFY_GID_VLAN_VLAN_EN       0x8000UL
 __le16 ipid;
 __le16 gid_index;
 __le16 stats_ctx;
 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK   0x7fffUL
 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT    0
 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID     0x8000UL
 __le16 unused_0;
};

/* creq_modify_gid_resp (size:128b/16B) */
struct creq_modify_gid_resp {
 u8 type;
 #define CREQ_MODIFY_GID_RESP_TYPE_MASK    0x3fUL
 #define CREQ_MODIFY_GID_RESP_TYPE_SFT     0
 #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_MODIFY_GID_RESP_TYPE_LAST     CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 xid;
 u8 v;
 #define CREQ_MODIFY_GID_RESP_V     0x1UL
 u8 event;
 #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 0x11UL
 #define CREQ_MODIFY_GID_RESP_EVENT_LAST   CREQ_MODIFY_GID_RESP_EVENT_ADD_GID
 u8 reserved48[6];
};

/* cmdq_query_gid (size:192b/24B) */
struct cmdq_query_gid {
 u8 opcode;
 #define CMDQ_QUERY_GID_OPCODE_QUERY_GID 0x18UL
 #define CMDQ_QUERY_GID_OPCODE_LAST     CMDQ_QUERY_GID_OPCODE_QUERY_GID
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le16 gid_index;
 u8 unused16[6];
};

/* creq_query_gid_resp (size:128b/16B) */
struct creq_query_gid_resp {
 u8 type;
 #define CREQ_QUERY_GID_RESP_TYPE_MASK    0x3fUL
 #define CREQ_QUERY_GID_RESP_TYPE_SFT     0
 #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT  0x38UL
 #define CREQ_QUERY_GID_RESP_TYPE_LAST     CREQ_QUERY_GID_RESP_TYPE_QP_EVENT
 u8 status;
 __le16 cookie;
 __le32 size;
 u8 v;
 #define CREQ_QUERY_GID_RESP_V     0x1UL
 u8 event;
 #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 0x18UL
 #define CREQ_QUERY_GID_RESP_EVENT_LAST     CREQ_QUERY_GID_RESP_EVENT_QUERY_GID
 u8 reserved48[6];
};

/* creq_query_gid_resp_sb (size:320b/40B) */
struct creq_query_gid_resp_sb {
 u8 opcode;
 #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 0x18UL
 #define CREQ_QUERY_GID_RESP_SB_OPCODE_LAST     CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID
 u8 status;
 __le16 cookie;
 __le16 flags;
 u8 resp_size;
 u8 reserved8;
 __le32 gid[4];
 __le16 src_mac[3];
 __le16 vlan;
 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK          0xffffUL
 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT           0
 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK                       0xfffUL
 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT                        0
 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK                          0x7000UL
 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT                           12
 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8                       (0x0UL << 12)
 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100                       (0x1UL << 12)
 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100                       (0x2UL << 12)
 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200                       (0x3UL << 12)
 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300                       (0x4UL << 12)
 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1                       (0x5UL << 12)
 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2                       (0x6UL << 12)
 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3                       (0x7UL << 12)
 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3
 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN                            0x8000UL
 __le16 ipid;
 __le16 gid_index;
 __le32 unused_0;
};

/* cmdq_create_qp1 (size:640b/80B) */
struct cmdq_create_qp1 {
 u8 opcode;
 #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 0x13UL
 #define CMDQ_CREATE_QP1_OPCODE_LAST      CMDQ_CREATE_QP1_OPCODE_CREATE_QP1
 u8 cmd_size;
 __le16 flags;
 __le16 cookie;
 u8 resp_size;
 u8 reserved8;
 __le64 resp_addr;
 __le64 qp_handle;
 __le32 qp_flags;
 #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED             0x1UL
 #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION     0x2UL
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