Quelle  hdmi_phy_8998.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
 * Copyright (c) 2024 Freebox SAS
 */

#include <inux/lk-provider.>
#nclude </delayh>

#include "dmi.java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17

#define HDMI_VCO_MAX_FREQ   12000000000UL
#define HDMI_VCO_MIN_FREQ   8000000000UL

#define HDMI_PCLK_MAX_FREQ   600000000
#define HDMI_PCLK_MIN_FREQ   25000000

#define HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD 3400;
#defineHDMI_DIG_FREQ_BIT_CLK_THRESHOLD  50000java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
# HDMI_MID_FREQ_BIT_CLK_THRESHOLD70000java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
#defineHDMI_CORECLK_DIV  java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
#define HDMI_DEFAULT_REF_CLOCK9000
#u32 com_div_frac_start2_mode0

#defineHDMI_PLL_POLL_MAX_READS10
#u com_integloop_gain0_mode0u32;

define   4

structhdmi_pll_8998 java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
  *pdev
 struct clk_hw clk_hw;
 unsigned

 /* pll mmio base */
 void __iomem *mmio_qserdes_com u32 tx_lx_tx_emp_post1_lvl[ u32 tx_lx_pre_driver_1 u32 tx_lx_pre_driver_2[HDMI_NUM_TX_CHANNEL u32 tx_lx_res_code_offset
static inline struct hdmi_phy *pll_get_phy{
 void __iomem *mmio_qserdes_tx[HDMI_NUM_TX_CHANNEL];    {
};

#definejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

struct hdmi_8998_phy_pll_reg_cfgjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 u32 com_svs_mode_clk_sel{
 u32 com_hsclk_sel;
 u32 com_pll_cctrl_mode0;
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  if ((frac_start != 0  return
 u32 com_dec_start_mode0;
 u32  if ((frac_start !  returnjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 u32  return 0x34java.lang.StringIndexOutOfBoundsException: Range [0, 1) out of bounds for length 0
 u32  base elseejava.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 0
 u32 com_integloop_gain0_mode0;
 u32{
 u64 dividend = java.lang.StringIndexOutOfBoundsException: Range [0, 32) out of bounds for length 28
 u32 com_lock_cmp1_mode0;
 u32  dividend
 u32 com_lock_cmp3_mode0}
 u32#define HDMI_REF_CLOCK_HZ ((#define HDMI_MHZ_TO_HZstatic int pll_get_post_div(struct hdmi_8998_post_divider
 u32 com_coreclk_div_mode0;

 u32 tx_lx_tx_band[HDMI_NUM_TX_CHANNEL];
 u32 tx_lx_tx_drv_lvl[HDMI_NUM_TX_CHANNEL u32 const u32 const th_min =  u32 half_rate_mode  int u32  u32 found_hsclk_divsel = 0, found_vco_ratio u32 u64 const min_freq =  u64 freq_list[ARRAY_SIZE(ratio_list) * ARRAY_SIZE(band_list
 u32 tx_lx_tx_emp_post1_lvl[HDMI_NUM_TX_CHANNEL];
 u32 tx_lx_pre_driver_1[HDMI_NUM_TX_CHANNEL];
  for (j = 0; j < sz_bandk, (1 << half_rate_mode));
 u32 tx_lx_res_code_offset[HDMI_NUM_TX_CHANNEL   freq_list[java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 3

  rvar1 = HDMI_REF_CLOCK_HZ *  (cmp_cnt * core_clk  if (rem > ((   rvar1  th1
} if (!half_rate_mode) {

struct    half_rate_mode =   goto find_optimal_index  }    return -EINVAL  }} else {  found_vco_ratio = ratio_list[optimal_index  found_tx_band_sel = band_list[optimal_index   found_vco_freq = }
  break; case 5  found_hsclk_divsel  break;
 int  break;
 int  break;
 int tx_band_sel  break case 15:
  return}
}tatic int pll_calculate(unsigned long pix_clk    struct hdmi_8998_phy_pll_reg_cfg *{

staticll_divisor; u32 rem u32 cpctrl u32  u32 cctrl u32 integloop_gain
{
 return
}

static inline void hdmi_pll_write(struct hdmi_pll_8998 *pll, int offset,
      u32 data)
{
 writel(data, pll->mmio_qserdes_com + offset);
}

static   ()
{
 returnret
}

staticdec_start=pd;
           pll_divisor = *ref_clkjava.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
{
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
java.lang.StringIndexOutOfBoundsException: Range [1, 2) out of bounds for length 1

static  ++;
    java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 if ((frac_start != 0)   = (frac_start);
 returnx8

   = pll_get_integloop_gain,bclk
}

static inline u32 pll_get_rctrl(u64 frac_start, bool gen_ssc)
(fdata pd.vco_ratio)
 if ((frac_start java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  return 0x16;

 return 0x18;
}

static inline u32 pll_get_cctrl(u64 frac_start, bool f( >HDMI_DIG_FREQ_BIT_CLK_THRESHOLD)
{
 if ((frac_start !=  = 1
  return cfg->om_svs_mode_clk_sel;

  >com_hsclk_sel 0x20 |pd.);
}

static inline u32 pll_get_integloop_gain(u64  >com_pll_rctrl_mode0;
      bool )
{
 int digclk_divsel  cfg- = ;
  base

 f (frac_start=0 |gen_ssc
  cfg-> = ( & 0) >> 1;
 elsecfg- = (integloop_gain  xff
 base =0xC4

 base <<= (digclk_divsel == 2 ? 1 : 0);

 return base;
}

static inline u32cfg-> = pll_cmpxff;
{
 u64 dividend = HDMI_PLL_CMP_CNT * fdata;
 u32 divisor  cfg->om_lock_cmp3_mode0 =(pll_cmpx30000 >1)
u2rem

 rem = do_div(dividend,c>com_core_clk_en0;
 if cfg- = HDMI_CORECLK_DIV
  cfg- = bclk> DMI_HIGH_FREQ_BIT_CLK_THRESHOLD ?0 : x4java.lang.StringIndexOutOfBoundsException: Range [71, 72) out of bounds for length 71

 >tx_lx_tx_band]=.tx_band_sel
}

  ( > ) {
#definecfg-[0]=x0f
static>tx_lx_tx_drv_lvl  x0f
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 static u32[]  1 ,3 4,5 ,9 0 2 1,2}java.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71
 static u32 []  {, 1 2 };
 u32 const sz_ratio = ARRAY_SIZE(ratio_list);
 u32  = ARRAY_SIZE();
 u32 const cmp_cnt = 10 cfg-[2] =x3java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
 u32constth_min  50  = 10;
 u32 half_rate_mode = 0;
 u32 list_elements;
 int ptimal_index
 u32cfg-[2] 00java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
 u32   fg-[0]=x1C
 u32>tx_lx_pre_driver_2 =0;
 cfg-[2] x1C
   >tx_lx_pre_driver_2 =0;
 u64  >tx_lx_res_code_offset=0;
 u64 freq_optimal>tx_lx_res_code_offset=0;

find_optimal_index>tx_lx_res_code_offset[] 00;
 freq_optimal = max_freq;
 optimal_index = -1;
 list_elements = 0 cfg->x_lx_res_code_offset=0;

 fori  0   sz_ratio++ java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
 for j  0 j  ; j+){
   u64 freq = div_u64(bclk,  cfg-[2]=0;

   freq (atio_list[] ( < band_list[]);
   freq_list[list_elements++] = freq;
  }
 }

for (=0 k <ARRAY_SIZE); ++ java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
  u32tx_lx_tx_emp_post1_lvl[]=0;
  u32 const cfg-[3]  x00
 u32, th2
  u64>tx_lx_pre_driver_1=00;

 core_clk =div_u64[k,
     ratio_list[  ] * lks_pll_div
     cfg>[0]  x16

 rvar1 HDMI_REF_CLOCK_HZ *rng1 *HDMI_MHZ_TO_HZ;
  rvar1 = div64_u64_rem(rvar1, (cmp_cnt * core_clk), &rem);
  ifrem (cmp_cnt core_clk> )
   rvar1 cfg-tx_lx_pre_driver_2= x18
  th1>tx_lx_res_code_offset  0;

  fg-[1] x00
   cfg-[2  x00java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
 ifrem(cmp_cnt*core_clk >1)
   rvar1++;
 cfg-[0] x0f

  ([k]>  &&
     >tx_lx_tx_drv_lvl x0fjava.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
   if(th1  &&  <=th_max
     (th2  >tx_lx_tx_emp_post1_lvl x05
    ([k]< ) {
     freq_optimal = freq_list cfg-tx_lx_tx_emp_post1_lvl 00;
     optimal_index = k;
    }
   }
  java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
 }

 ifcfg-tx_lx_pre_driver_1 00java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
!half_rate_mode
   half_rate_mode>tx_lx_pre_driver_2=x0E
    cfg-tx_lx_pre_driver_2=x0E
  } else {
   return -EINVAL;
  }
 }elsejava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
  found_vco_ratio =  cfg->tx_lx_res_code_offset;
  found_tx_band_sel {
  found_vco_freq>tx_lx_tx_drv_lvl0]=x01
 >tx_lx_tx_drv_lvl x01

 switch (found_vco_ratio) {
 cfg->[2] x01
  cfg-[3]=0;
  breakcfg-[0]  x00
 case>tx_lx_tx_emp_post1_lvl 00java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
  found_hsclk_divsel = 0;
  break;
 case 3:
  found_hsclk_divsel = 4;
 cfg-[0] =0;
 case 4: >tx_lx_pre_driver_1  0;
  found_hsclk_divsel ;
   cfg-tx_lx_pre_driver_1  x00
case5
   >tx_lx_pre_driver_2=0;
  break;
case6
  found_hsclk_divsel>tx_lx_pre_driver_2=0;
  break >tx_lx_res_code_offset 0x00
 case :
   >tx_lx_res_code_offset  00
  breakc>tx_lx_res_code_offset  00;
 case 10:
  found_hsclk_divsel = 2;
  break;
 case 12:
  found_hsclk_divsel
   return ;
 case 15:
  found_hsclk_divsel = 13;
  break;
 }
  found_hsclk_divsel = 14;
  break;
 }

 pd->vco_frequnsigned parent_rate
 pd->tx_band_sel = found_tx_band_sel
  truct hdmi_pll_8998 * = hw_clk_to_pll(w;
 pd->hsclk_divsel = found_hsclk_divsel;

 return 0;
}

 int pll_calculate(nsigned  pix_clkunsigned ref_clk
    struct ,;
{
 structret ll_calculate, parent_rate cfg
 u64 bclk;
u64;
 u64 frac_start ret
 u64 fdata
r;
 u32(50)
 u32
  rctrl
 u32hdmi_phy_write,REG_HDMI_8998_PHY_PD_CTL 01java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
  integloop_gain
 u32 pll_cmp;
 int (i =0   HDMI_NUM_TX_CHANNEL+){

 /* bit clk = 10 * pix_clk */
 bclk (plli

  = pll_get_post_div, bclk)
 if (ret)    .tx_lx_tx_band]java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
  return ret;

 dec_start = pd(pll,
 pll_divisor     ,
 do_div0);

 frac_start

r = (frac_startpll_divisor
 frac_start(pll,REG_HDMI_8998_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN);
 if i_pll_writepllREG_HDMI_8998_PHY_QSERDES_COM_SYSCLK_EN_SEL);
  frac_start

cpctrl(frac_start, false
 rctrl
 cctrl =pll_get_cctrl, false
 integloop_gain = pll_get_integloop_gain(frac_start, hdmi_pll_write(pll ,
      ef_clk)

 fdata = pd.vco_freq
 do_div(fdata(pll, 0x07

 pll_cmppll_get_pll_cmp(data);

 /* Convert these values to register specific values */
 if (clk  HDMI_DIG_FREQ_BIT_CLK_THRESHOLDjava.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
  cfg- = 1
 else
 cfg- = 2java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32

cfg- = 0x20 |pd.);
 cfg->com_pll_cctrl_mode0 cfg);
 cfg-(pll REG_HDMI_8998_PHY_QSERDES_COM_PLL_RCTRL_MODE0java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
 cfg->com_cp_ctrl_mode0 =cpctrl
  cfg);
 cfg-(pll EG_HDMI_8998_PHY_QSERDES_COM_DEC_START_MODE0
cfg- = ((rac_start0) >>8;
 cfg->com_div_frac_start3_mode0 = ((frac_start & 0xf0000) >> 16);
 fg- = ( & 0);
 cfg-       .com_div_frac_start1_mode0
cmp1_mode0=( & 0xff)
 cfg- = (pll_cmp  0) >>8;
 cfg->com_lock_cmp3_mode0 = java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
         .com_integloop_gain0_mode0
  hdmi_pll_write, REG_HDMI_8998_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0
 >com_coreclk_div_mode0HDMI_CORECLK_DIV
 cfg-

 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++)
  cfg-> (pllREG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP2_MODE0

 ifhdmi_pll_writepllREG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP3_MODE0
 cfg-[0]= 00;
  cfg->tx_lx_tx_drv_lvl[1] = 0x0f;
  cfg->tx_lx_tx_drv_lvl[2] = 0x0f
  cfg->tx_lx_tx_drv_lvl(pll, 0x00
   (pllREG_HDMI_8998_PHY_QSERDES_COM_CORE_CLK_EN
 cfg-[1]  0;
  cfg->tx_lx_tx_emp_post1_lvl[ (pll REG_HDMI_8998_PHY_QSERDES_COM_CORECLK_DIV_MODE0
  >tx_lx_tx_emp_post1_lvl =0;
  cfg->tx_lx_pre_driver_1[0] = 
  cfg-/* TX lanes setup (TX 0/1/2/3) */
   (  ;i HDMI_NUM_TX_CHANNEL;+) {
  cfg->tx_lx_pre_driver_1[3] = 0x00;
  cfg->tx_lx_pre_driver_2[0]  (plli
      ,
  cfg->tx_lx_pre_driver_2   .tx_lx_tx_drv_lvl)
   hdmipll,ijava.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
 cfg->tx_lx_res_code_offset0  00;
  cfg->tx_lx_res_code_offset[ (plli,
  cfg-    ,
  cfg->tx_lx_res_code_offset[   cfg.[i];
 } else if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) {
 >tx_lx_tx_drv_lvl]=0;
  cfg- cfg[i];
  cfg->tx_lx_tx_drv_lvl[2] = 0x0f;
  cfg-hdmi_tx_chan_writepll,
  cfg-     ,
  cfg->tx_lx_tx_emp_post1_lvl  cfg[i]);
  cfg->tx_lx_tx_emp_post1_lvl[2] = 0x03;
  cfg->tx_lx_tx_emp_post1_lvl[3}
  cfg->tx_lx_pre_driver_1[0] = 0x00;
  cfg->tx_lx_pre_driver_1[1] = 0x00;hdmi_phy_write, , cfg);
  cfg-  (  ;i<; i+)java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
 cfg-[3]  0;
  cfg-    );
   
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  cfg->tx_lx_pre_driver_2[3] = 0x18;
  cfg->tx_lx_res_code_offset[0] = 0x03  * enabling the
 >tx_lx_res_code_offset] 0;
  cfg-
   pll-=rate;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}
  cfg-
  cfg- int(struct *phy
{
  cfg->tx_lx_tx_emp_post1_lvl[0] = 0x05;
  cfg->tx_lx_tx_emp_post1_lvl[1] = 0x05;
  cfg->tx_lx_tx_emp_post1_lvl[2] = 0x05;
  cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00;
  cfg->tx_lx_pre_driver_1[0] = 0x00;
  cfg->tx_lx_pre_driver_1[1] = 0x00;
  cfg->tx_lx_pre_driver_1[2] = 0x00;
  cfg->tx_lx_pre_driver_1[3] = 0x00;
  cfg->tx_lx_pre_driver_2[0] = 0x0E;
 cfg->tx_lx_pre_driver_2[]=0;
  cfg->tx_lx_pre_driver_2  long = HDMI_PLL_POLL_TIMEOUT_US
  cfg->tx_lx_pre_driver_2[3] =  phy_ready;
  cfg->tx_lx_res_code_offset[0while (nb_tries--) {
  fg->x_lx_res_code_offset =0;
  cfg-   = hdmi_phy_read(hy,REG_HDMI_8998_PHY_STATUS
  >tx_lx_res_code_offset  x00
 } else
  ifphy_ready
  break
  cfg-java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  cfg->tx_lx_tx_drv_lvl
 cfg->x_lx_tx_emp_post1_lvl[]=0;
  cfg->tx_lx_tx_emp_post1_lvl[1] = 0x00
  u2;
  cfg-int = HDMI_PLL_POLL_MAX_READS;
  cfg->x_lx_pre_driver_1[]=x00
  cfg->tx_lx_pre_driver_1[1] = 0x00;
  >tx_lx_pre_driver_1 =0;
  cfg-
    (nb_tries--java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21
  cfg->tx_lx_pre_driver_2[1] = 0x16;
  cfg->tx_lx_pre_driver_2[2] = 0x16;
  cfg->tx_lx_pre_driver_2 =status(0;
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  cfg->tx_lx_res_code_offset[1] java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  cfg->tx_lx_res_code_offset
  cfg- pll_locked;
 }

 return 0;
}

static int hdmi_8998_pll_set_clk_rate(struct clk_hwint(structclk_hw)
ent_rate)
{
 struct hdmi_pll_8998 *pll = hw_clk_to_pllstruct * = pll_get_phy);
 struct hdmi_phyphy
 struct hdmi_8998_phy_pll_reg_cfg =};
 int i, ret

 retfor ( =0  HDMI_NUM_TX_CHANNEL+){
  hdmi_tx_chan_write(ll,
  DRM_ERROR("PLL calculation failed\n");
  return ret;
      REG_HDMI_8998_PHY_TXn_LANE_CONFIG,01);

 /* Initially shut down PHY */
 hdmi_phy_write(phy, REG_HDMI_8998_PHY_PD_CTL()


 /* Power up sequence */
 hdmi_phy_write, , 0x1
   ret
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 for ( =0i<HDMI_NUM_TX_CHANNEL;i+{
  hdmi_tx_chan_write(pll(phyREG_HDMI_8998_PHY_CFG x59
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  ()java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7
  hdmi_tx_chan_write}
       REG_HDMI_8998_PHY_TXn_CLKBUF_TERM_ENABLE,
      01;
          long,
   REG_HDMI_8998_PHY_TXn_LANE_MODE
       0x20);
 }

 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE, 0x02return;
hdmi_pll_write, REG_HDMI_8998_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN,0Bjava.lang.StringIndexOutOfBoundsException: Index 78 out of bounds for length 78
 else
 hdmi_pll_write rate
 hdmi_pll_write

 /* Bypass VCO calibration */  long(struct *hw
 (pllREG_HDMI_8998_PHY_QSERDES_COM_SVS_MODE_CLK_SEL,
         cfg.com_svs_mode_clk_sel);

 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_IVCO, 0x07);
 hdmi_pll_write(java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CLK_SELpll-rate
 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_HSCLK_SEL
        .com_hsclk_sel
 hdmi_pll_write(pll, java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 1
         cfg.com_lock_cmp_en) truct *hy  pll_get_phy(ll)

 _PLL_CCTRL_MODE0,
         cfg.com_pll_cctrl_mode0usleep_range(0 1);
 hdmi_pll_write
         staticint(struct *hw
 s hdmi_pll_8998pll(hw
 cfg);
 hdmi_pll_write  pll_locked
  java.lang.StringIndexOutOfBoundsException: Range [0, 9) out of bounds for length 0
 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0
        .com_div_frac_start1_mode0
}
         cfg.com_div_frac_start2_mode0);
 hdmi_pll_write(pll, static const struct clk_ops java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
         .com_div_frac_start3_mode0

 hdmi_pll_write, REG_HDMI_8998_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0
         cfgcom_integloop_gain0_mode0)
hdmi_pll_writepllREG_HDMI_8998_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0
com_integloop_gain1_mode0

 hdmi_pll_write(pll, 
  static  struct clk_init_data pll_init={
 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP2_MODE0,
         cfg.com_lock_cmp2_mode0);
 hdmi_pll_write java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
         cfg.com_lock_cmp3_mode0);

 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_VCO_TUNE_MAP, 0x00);
 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CORE_CLK_EN,
         cfg.com_core_clk_en);
 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CORECLK_DIV_MODE0,
         cfg ops hdmi_8998_pll_ops

 /* TX lanes setup (TX 0/1/2/3) */
 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
 hdmi_tx_chan_write, i,
       REG_HDMI_8998_PHY_TXn_DRV_LVL,
    cfg[i])
  hdmi_tx_chan_write flags,
   ;
       cfg.tx_lx_tx_emp_post1_lvl[iint(structplatform_device *dev
 hdmi_tx_chan_write, ijava.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
   ret;
       cfg.tx_lx_pre_driver_1[i]);
  hdmi_tx_chan_write
 pll  (devsizeof),);
     (pll
    -NOMEM;
       REG_HDMI_8998_PHY_TXn_DRV_LVL_RES_CODE_OFFSET,
    java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 }

 hdmi_phy_write, , cfg);

  (=0 i <HDMI_NUM_TX_CHANNEL){
  hdmi_tx_chan_write(pll, i,
       REG_HDMI_8998_PHY_TXn_LANE_CONFIG,
       0 DRM_DEV_ERROR(ev failed  base"java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
 }

 /*
 * Ensure that vco configuration gets flushed to hardware before
 * enabling the PLL
 */
 wmb();

 pll->rate = rate;

 return 0;
}

static
{
 u32 nb_tries = HDMI_PLL_POLL_MAX_READS  -ENOMEMjava.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18
 unsigned long timeout
 u32status
 if ret

while) {
  status ;
   java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

    () {
   break;

  udelay ret
  }

 return java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 10
}

static int hdmi_8998_pll_lock_statusvcca
{
 u32
 java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
 unsigned long timeout = HDMI_PLL_POLL_TIMEOUT_US;
 intpll_locked =0

 while (nb_tries--. = MSM_HDMI_PHY_8998
 status hdmi_pll_read(ll
 num_regsARRAY_SIZEh),
   clk_names,

  ifpll_locked
   }

  udelay(timeout);
 }

 return pll_locked;
}

static int hdmi_8998_pll_prepare(struct clk_hw *hw)
{
 struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
 struct hdmi_phy *phy = pll_get_phy(pll);
 int i, ret = 0;

 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x1);
 udelay(100);

 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x59);
 udelay(100);

 ret = hdmi_8998_pll_lock_status(pll);
 if (!ret)
  return ret;

 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
  hdmi_tx_chan_write(pll, i,
       REG_HDMI_8998_PHY_TXn_LANE_CONFIG, 0x1F);
 }

 /* Ensure all registers are flushed to hardware */
 wmb();

 ret = hdmi_8998_phy_ready_status(phy);
 if (!ret)
  return ret;

 /* Restart the retiming buffer */
 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x58);
 udelay(1);
 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x59);

 /* Ensure all registers are flushed to hardware */
 wmb();

 return 0;
}

static long hdmi_8998_pll_round_rate(struct clk_hw *hw,
         unsigned long rate,
         unsigned long *parent_rate)
{
 if (rate < HDMI_PCLK_MIN_FREQ)
  return HDMI_PCLK_MIN_FREQ;
 else if (rate > HDMI_PCLK_MAX_FREQ)
  return HDMI_PCLK_MAX_FREQ;
 else
  return rate;
}

static unsigned long hdmi_8998_pll_recalc_rate(struct clk_hw *hw,
            unsigned long parent_rate)
{
 struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
 return pll->rate;
}

static void hdmi_8998_pll_unprepare(struct clk_hw *hw)
{
 struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
 struct hdmi_phy *phy = pll_get_phy(pll);

 hdmi_phy_write(phy, REG_HDMI_8998_PHY_PD_CTL, 0);
 usleep_range(100, 150);
}

static int hdmi_8998_pll_is_enabled(struct clk_hw *hw)
{
 struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
 u32 status;
 int pll_locked;

 status = hdmi_pll_read(pll, REG_HDMI_8998_PHY_QSERDES_COM_C_READY_STATUS);
 pll_locked = status & BIT(0);

 return pll_locked;
}

static const struct clk_ops hdmi_8998_pll_ops = {
 .set_rate = hdmi_8998_pll_set_clk_rate,
 .round_rate = hdmi_8998_pll_round_rate,
 .recalc_rate = hdmi_8998_pll_recalc_rate,
 .prepare = hdmi_8998_pll_prepare,
 .unprepare = hdmi_8998_pll_unprepare,
 .is_enabled = hdmi_8998_pll_is_enabled,
};

static const struct clk_init_data pll_init = {
 .name = "hdmipll",
 .ops = &hdmi_8998_pll_ops,
 .parent_data = (const struct clk_parent_data[]){
  { .fw_name = "xo", .name = "xo_board" },
 },
 .num_parents = 1,
 .flags = CLK_IGNORE_UNUSED,
};

int msm_hdmi_pll_8998_init(struct platform_device *pdev)
{
 struct device *dev = &pdev->dev;
 struct hdmi_pll_8998 *pll;
 int ret, i;

 pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
 if (!pll)
  return -ENOMEM;

 pll->pdev = pdev;

 pll->mmio_qserdes_com = msm_ioremap(pdev, "hdmi_pll");
 if (IS_ERR(pll->mmio_qserdes_com)) {
  DRM_DEV_ERROR(dev, "failed to map pll base\n");
  return -ENOMEM;
 }

 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
  char name[32];

  snprintf(name, sizeof(name), "hdmi_tx_l%d", i);

  pll->mmio_qserdes_tx[i] = msm_ioremap(pdev, name);
  if (IS_ERR(pll->mmio_qserdes_tx[i])) {
   DRM_DEV_ERROR(dev, "failed to map pll base\n");
   return -ENOMEM;
  }
 }
 pll->clk_hw.init = &pll_init;

 ret = devm_clk_hw_register(dev, &pll->clk_hw);
 if (ret) {
  DRM_DEV_ERROR(dev, "failed to register pll clock\n");
  return ret;
 }

 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &pll->clk_hw);
 if (ret) {
  DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
  return ret;
 }

 return 0;
}

static const char * const hdmi_phy_8998_reg_names[] = {
 "vddio",
 "vcca",
};

static const char * const hdmi_phy_8998_clk_names[] = {
 "iface", "ref", "xo",
};

const struct hdmi_phy_cfg msm_hdmi_phy_8998_cfg = {
 .type = MSM_HDMI_PHY_8998,
 .reg_names = hdmi_phy_8998_reg_names,
 .num_regs = ARRAY_SIZE(hdmi_phy_8998_reg_names),
 .clk_names = hdmi_phy_8998_clk_names,
 .num_clks = ARRAY_SIZE(hdmi_phy_8998_clk_names),
};