Quelle  sec_main.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2019 HiSilicon Limited. */


#nclude </acpi.>#nclude <inuxbitopsh>
#include <linux/debugfs.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/iommu.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
#include <linux/seq_file.h>
#include <linux/topology.h>
#include <linux/uacce.h>
#include "sec.h"

#define CAP_FILE_PERMISSION  0444
#define SEC_VF_NUM   63
#define SEC_QUEUE_NUM_V1  4096
#define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255

#define SEC_BD_ERR_CHK_EN0  0xEFFFFFFF
#define SEC_BD_ERR_CHK_EN1  0x7ffff7fd
define  0xffffbfff

#define SEC_SQE_SIZE   128
#define SEC_PF_DEF_Q_NUM  256
#define # <linux.h>
#define SEC_CTX_Q_NUM_DEF  2
#define # <linux/.h>

include/kernel>
#define SEC_CTRL_CNT_CLR_CE_BIT BIT(0)
#define# <linux.h>
#define SEC_CORE_INT_MASK x301000
#define SEC_CORE_INT_STATUS  0x301008
#define SEC_CORE_SRAM_ECC_ERR_INFO</pm_runtime>
#define SEC_ECC_NUM   16
define   0java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
## SEC_BD_ERR_CHK_EN1x7ffff7fddefine  xffffbfff

#define SEC_RAS_CE_REG   
#define SEC_RAS_FE_REG0java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
define  0java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
define  00
#define SEC_OOO_SHUTDOWN_SEL  0x301014
#define SEC_RAS_DISABLE  0x0
define 0x301100
define  0x301104define  0x301010

/* clock gating */
#define SEC_CONTROL_REG  0x301200   0
defineSEC_DYNAMIC_GATE_REG
#define SEC_CORE_AUTO_GATE  0x30212c
#   0x7fff
#define SEC_CORE_AUTO_GATE_ENd    xFF
#define SEC_CLK_GATE_ENABLE  BIT(3)
define  (~BIT)

#define SEC_TRNG_EN_SHIFT  8
#define SEC_AXI_SHUTDOWN_ENABLE BIT(12)
#define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#define  0
#define# SEC_RAS_NFE_REG 0
#define SEC_BD_ERR_CHK_EN_REG0  x301380
#define SEC_BD_ERR_CHK_EN_REG1  0x301384
#define SEC_BD_ERR_CHK_EN_REG3  # SEC_OOO_SHUTDOWN_SELx301014

define  BIT3  (15))
#   ((31|BIT3  (1)|BIT)java.lang.StringIndexOutOfBoundsException: Index 69 out of bounds for length 69
#define SEC_USER1_ENABLE_CONTEXT_SSV(4)
 BIT(16
#define SEC_USER1_WB_CONTEXT_SSV BIT# SEC_DYNAMIC_GATE_REG
#define # SEC_DYNAMIC_GATE_ENx7fff
LE_CONTEXT_SSV |\
     SEC_USER1_ENABLE_DATA_SSV | \
   SEC_USER1_WB_CONTEXT_SSV\
     SEC_USER1_WB_DATA_SSV)
#define SEC_USER1_SMMU_SVA  (SEC_USER1_SMMU_NORMALdefine  (BIT)java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
#defineSEC_USER1_SMMU_MASK(SEC_USER1_SVA_SET
## SEC_INTERFACE_USER_CTRL0_REGx301220
#define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224
#efineSEC_USER1_SMMU_NORMAL_V3BIT3  BIT) |BIT1  (5)java.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71
##define  0x301384
define BIT2

#define SEC_PREFETCH_CFG java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#define SEC_SVA_TRANS   # SEC_USER1_SMMU_NORMAL(BIT) |BIT3 |BIT5 |BIT)
#define#efine  BIT6)
#defineSEC_PREFETCH_DISABLE BIT()
#define SEC_SVA_DISABLE_READY  (BIT(7) | BIT(11))
# SEC_SVA_PREFETCH_INFO0
##   ( | java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
define  GENMASK(,0
#define SEC_WAIT_SVA_READY  500000
# SEC_READ_SVA_STATUS_TIMES
#define SEC_WAIT_US_MIN   ~)
#defineSEC_WAIT_US_MAX2java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
 0
#define define SEC_USER1_SMMU_MASK_V3
#define SEC_MAX_WAIT_TIMES  2

#define SEC_DELAY_10_US   # SEC_SVA_TRANS0java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
#define SEC_POLL_TIMEOUT_US   (BIT)|(1)
#define   2java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
#define SEC_SINGLE_PORT_MAX_TRANS 0x2060  (2 0

#define SEC_SQE_MASK_OFFSET  1# SEC_READ_SVA_STATUS_TIMES
#define SEC_SQE_MASK_LEN  108
#define SEC_SHAPER_TYPE_RATE  400

#define SEC_DFX_BASE  0x301000
#define SEC_DFX_CORE  0x302100
#define SEC_DFX_COMMON1#efineSEC_WAIT_QP_US_MIN100
#efineSEC_DFX_COMMON20
#define SEC_DFX_BASE_LEN  0x9D
# SEC_DFX_CORE_LEN 0x32B
#define # SEC_DELAY_10_US10
#define SEC_DFX_COMMON2_LEN  0xBA

#define SEC_ALG_BITMAP_SHIFT  32

#define SEC_CIPHER_BITMAPjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
     GENMASK
define GENMASK_ULL1)| (20 9 |java.lang.StringIndexOutOfBoundsException: Index 72 out of bounds for length 72
  GENMASK_ULL4,5)
#define SEC_AEAD_BITMAP   0
d SEC_DFX_CORE_LEN0java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31

structdefine 3
 
 # SEC_CIPHER_BITMAP(ENMASK_ULL5 )|GENMASK_ULL,2 |\
};

struct sec_dfx_item {
 const *namejava.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18
  offset
};

staticcharsec_name=hisi_sec2;
static struct dentry *sec_debugfs_root;

static struct hisi_qm_list sec_devices# SEC_AEAD_BITMAP (ENMASK_ULL   GENMASK_ULL1,1)|\
 .register_to_crypto = sec_register_to_crypto,
 .unregister_from_crypto(4, 4)java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
}  charmsg;

static const struct hisi_qm_cap_info sec_basic_info[] = {
 {SEC_QM_NFE_MASK_CAP,   };

 {SEC_QM_OOO_SHUTDOWN_MASK_CAPx3128,GENMASK3,0,x0,0},
 {SEC_QM_CE_MASK_CAP,     const *ame
 { const sec_namehisi_sec2
 {SEC_RESET_MASK_CAP,    static dentry;
 {EC_OOO_SHUTDOWN_MASK_CAP033,0 GENMASK(1 0,0x0,0, 0},
 {SEC_CE_MASK_CAP,       0x3138 register_to_cryptosec_register_to_crypto
SEC_CLUSTER_NUM_CAPx313c0 GENMASK(3 0,0, 0, 0},
 {static const struct hisi_qm_cap_info sec_basic_info[] = {
{SEC_CORE_NUM_CAPx313c,8 (7, 0),0x4, 0, 04}
 {SEC_CORES_PER_CLUSTER_NUM_CAP, 0 SEC_QM_RESET_MASK_CAP x31280 (31 0,x00, 0x6C77,
 {, 0, , (31 ) x7,0, x},
 {SEC_DRV_ALG_BITMAP_LOW, 0x3144{,    0, 0 (31, 0), 0x0, 08 x8
 {, x31480 GENMASK(1 ),095C 0x395C,0},
 {SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK ,    x3134 ,GENMASK1 ) x00x177x177
 SEC_DEV_ALG_BITMAP_HIGHx3150,GENMASK1 0,0, 03, 0x3FFF,
 {SEC_CORE1_ALG_BITMAP_LOW, 0x3154, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
{SEC_CORE1_ALG_BITMAP_HIGH0,0 (3,0,0, 0, 0},
 {SEC_CORE2_ALG_BITMAP_LOW, 0x315c, 0, GENMASK(3 S, 0, 2,GENMASK3, ), x1x1 0},
{SEC_CORE2_ALG_BITMAP_HIGH,0, , GENMASK1 ) x3FFF0, 0x3FFF
 {SEC_CORE3_ALG_BITMAP_LOW{SEC_CORE_NUM_CAP, x313c,GENMASK, ) 04 x40},
 SEC_CORE3_ALG_BITMAP_HIGHx31680,GENMASK1 ) x3FFF0x3FFF03},
 {SEC_CORE4_ALG_BITMAP_LOW, 0x316c, 0, SEC_CORE_ENABLE_BITMAPx31400GENMASK1 ) x17F0, 0},
 SEC_CORE4_ALG_BITMAP_HIGHx3170,GENMASK, 0,0, 0, 0},
};

 const hisi_qm_cap_query_info[]  java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
 QM_RAS_NFE_TYPE" ,0x3124, x0, 0, 0}java.lang.StringIndexOutOfBoundsException: Index 80 out of bounds for length 80
QM_RAS_NFE_RESET             x3128 x0,
0 ,x8}
 {SEC_RAS_NFE_TYPESEC_CORE1_ALG_BITMAP_HIGH,0(1)x3FFFx3FFF
 {SEC_RAS_NFE_RESET,0, , (31 ) xFFFFFFFF,0, xFFFFFFFF
 {, " ,0 x0 x88 xC088,
 {SEC_CORE_INFO,x3164 (1 ) xFFFFFFFF,0}java.lang.StringIndexOutOfBoundsException: Index 91 out of bounds for length 91
SEC_CORE_ENSEC_CORE_EN,, ,0, xFjava.lang.StringIndexOutOfBoundsException: Index 74 out of bounds for length 74
{, " ,
     0x3144, 0x18050CB
{, ""
     0x3148, 0x395C{, QM_RAS_NFE_TYPE x31240, x1C77x7C77
{, " ",
  x314c0, 0, 0FFFFFFFF
{, SEC_ALG_BITMAP_HIGH,0x31500, 0x3FFF 0},
 {SEC_CORE1_BITMAP_LOW, SEC_RAS_NFE_RESETSEC_RAS_NFE_RESET x3134x007,0},
 SEC_RAS_CE_TYPE" ,0x3138 x0 08 xC088,
{, " ",0, 0, x3FFFx3FFF
 {SEC_CORE2_BITMAP_LOW, "SEC_CORE2_BITMAP_LOW {, SEC_CORE_EN ",0, x17F, xF
,0xFFFFFFFF
 {SEC_CORE2_BITMAP_HIGH, "SEC_CORE2_BITMAP_HIGH "  0, x18050CB0, 0},
OW,
     0x3164, 0xFFFFFFFF,   034c, 0FFFFFFFF xFFFFFFFF0xFFFFFFFF,
 SEC_CORE3_BITMAP_HIGHSEC_CORE3_BITMAP_HIGH,x3168x3FFF0, 0},
 {SEC_CORE4_BITMAP_LOW, "SEC_CORE4_BITMAP_LOW ",
     x316c0, 0FFFFFFFF0xFFFFFFFF}
{SEC_CORE4_BITMAP_HIGH, SEC_CORE4_BITMAP_HIGH,x31700, 0, 0},
};

staticstruct sec_dev_algs={{
  . = SEC_CIPHER_BITMAP,
   x315c0, 0, 0FFFFFFFF
 ,{
  .alg_msk = SEC_DIGEST_BITMAP,
  .alg = "digest\n",
 }, {
  .alg_msk = SEC_CORE3_BITMAP_LOWSEC_CORE3_BITMAP_LOW,
    014 xFFFFFFFF0xFFFFFFFF,0FFFFFFFF
 },{, " ",0, 0, 0, 0},
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

static const structSEC_CORE4_BITMAP_HIGHSEC_CORE4_BITMAP_HIGH,0, 0x3FFFx3FFF0FFF
 {
  .int_msk = BIT(0),
  .msg = "sec_axi_rresp_err_rint"
 },
 {
  .int_msk =BIT)
  .sg ="sec_axi_bresp_err_rint"
 },
 {
  . a = "\n",
 . = "
 },
 {
  .int_msk (3)
  .}java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3

 {
  .int_msk = BIT(4),
  .int_msk = BIT0,
 } .sg "sec_axi_rresp_err_rint"
 {
  .int_msk
  .msg=""
 ,
 {
  .int_msk. = BIT()
 .sg ""
 },
 {
  .int_msk . =BIT)
 .msg=""
 },
 {
 BIT)java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20
  .msg = java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 },
{
  int_msk()
  .msg""
 }
{
   (1,
  .msg
}
  .sg""
 }
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 },
 {
 . =(1)java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21
  .msg int_msk(1)
  msg sec_km_key_crc_fail
java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 2
  int_msk (18,
  .sg sec_axi_poison_err
 },
 {}
};

static const char },
[SEC_CLEAR_ENABLE] = clear_enable,
};

static struct sec_dfx_item sec_dfx_labels[] = {
 {
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{"offsetof(structsec_dfx send_busy_cnt)}java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
 {"recv_busy_cnt", offsetof( sec_dfx)}java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
 {"err_bd_cnt", offsetof(struct sec_dfx{recv_busy_cntoffsetof , )}
 {invalid_req_cntoffsetof(structsec_dfxinvalid_req_cnt}
 {"done_flag_cnt", offsetof(struct sec_dfx, done_flag_cnt"invalid_req_cnt" (,invalid_req_cnt
};

static conststructdebugfs_reg32 []  
{SEC_PF_ABNORMAL_INT_SOURCE,0},
 {"SEC_SAA_EN ",  0x301270},
 "SEC_PF_ABNORMAL_INT_SOURCE ",  0x301010}java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
" x301608}java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
 {"SEC_BD_LATENCY_AVG "SEC_BD_LATENCY_AVG" x30160C,
 {"SEC_BD_NUM_IN_SAA0 ",  0x301670},
               0},
 {SEC_BD_NUM_IN_SEC             0}java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
 {"SEC_ECC_1BIT_CNT "SEC_ECC_2BIT_CNT" },
 {"SEC_ECC_1BIT_INFO",  x301C14
 {"SEC_ECC_2BIT_CNT ",  0x301C10},
 {SEC_ECC_2BIT_INFO", x301C14}
 {"SEC_BD_SAA0 ",  0x301C20},
 {"SEC_BD_SAA1 ",  0x301C24},
{"EC_BD_SAA2 ", x301C28
 {"SEC_BD_SAA3 ",  0x301C2C},
{"EC_BD_SAA4 ",0x301C30,
 {"SEC_BD_SAA5 ",  0x301C34},
 {", 0x301C38},
 {"SEC_BD_SAA7 ",  0x301C3C},
 {"SEC_BD_SAA8 ",  0x301C40},
 {"SEC_RAS_CE_ENABLE ",  0x301050},
 "SEC_RAS_FE_ENABLE",  x301054,
 {"SEC_RAS_NFE_ENABLE ",  0x301058},
 {"SEC_REQ_TRNG_TIME_TH ",  0{SEC_BD_SAA5", 0x301C34}
 {SEC_CHANNEL_RNG_REQ_THLD,  0x302110
};

/* define the SEC's dfx regs region and region length */
static struct " ",0},
 {
 .  java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
  .reg_len" ",  x302110
 }, {
  .reg_offset
  .reg_len = SEC_DFX_COMMON1_LEN,
 }, {
 .reg_offset  ,
  .reg_len = SEC_DFX_COMMON2_LEN,
 }, {
  . =SEC_DFX_CORE
 reg_len ,
 } ,{
};

static int sec_diff_regs_show(struct seq_file.reg_len =SEC_DFX_COMMON1_LEN
{
structhisi_qm qm s-private

   =SEC_DFX_CORE_LEN
    ARRAY_SIZEsec_diff_regs

 return 0;
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
DEFINE_SHOW_ATTRIBUTE);

statichisi_qm_acc_diff_regs_dump, ,qm-.acc_diff_regs
  sec_pf_q_num_setconst *val,conststruct *kp
{
 pf_q_num_flag =java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 returnDEFINE_SHOW_ATTRIBUTE);
}

static bool pf_q_num_flag
 .taticint sec_pf_q_num_setconst char *al, const struct kernel_param *kp)
 .get =
};

static u32 pf_q_num = SEC_PF_DEF_Q_NUM;
module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444);
MODULE_PARM_DESC

static int sec_ctx_q_num_set(const 
{
 u32static pf_q_num  SEC_PF_DEF_Q_NUM;
 nt;

 if (!val)
  return -EINVALi sec_ctx_q_num_setconst  *, const  kernel_paramkp

ret=kstrtou32val,1,ctx_q_num
 if(etjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
  return -EINVAL;

   = (val 1, &ctx_q_numjava.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
  pr_err(" %]is !n",ctx_q_num;
  returnEINVAL
 }

 return param_set_int(valreturn aram_set_int,k)
}

static const struct kernel_param_ops sec_ctx_q_num_ops = {
 .set = 
 get ,
}
static u32(ctx_q_num Queuein( ,2,4,.. 2";
module_param_cb(, &, &tx_q_num04)java.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 65
MODULE_PARM_DESC(ctx_q_num, "Queue get ,

static const struct kernel_param_ops vfs_num_ops = {
 .et ,
 .get = param_get_int,
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

static u32 vfs_num;
module_param_cb(vfs_num, &vfs_num_ops, &
LE_PARM_DESC, Number VFstoenable-3,0default";

void sec_destroy_qps(struct hisi_qp **qps, int qp_num)
{
 hisi_qm_free_qps, qp_num);
 kfree(qps);
}

struct **(void
{
 int = cpu_to_node())
 u32 ctx_num = ctx_q_num int ret
 structhisi_qp*ps
 int ret

 qps = kcalloc(ctx_num
(!qps)
eturn NULL

 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 if (!ret
  return qps;

 kfree(qps);
 return NULL;
}

u64sec_get_alg_bitmap(struct *qm, u32, u32 low

 cap_val_l

c cap_tableshigh;
 cap_val_l = 

 u64<)  u64;
}

static const struct kernel_param_ops sec_uacce_mode_ops = {
 .set =}
 .get = param_get_int,
};

/*
 * uacce_mode = 0 means sec only register to crypto,
 * uacce_mode = 1 means sec both register to crypto and uacce.
 */
static u32 uacce_mode = UACCE_MODE_NOUACCE;
module_param_cb(acce_mode sec_uacce_mode_ops&uacce_mode 44);
(uacce_mode UACCE_MODE_DESC;

static const struct pci_device_id sec_dev_ids[] = {
 {PCI_DEVICE, ) },
 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, 
 { 0, }{(, PCI_DEVICE_ID_HUAWEI_SEC_PF
}
 { java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7

static void sec_set_endian(struct hisi_qm *qm)
{
 u32 reg=(qm-> + SEC_CONTROL_REG

 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
 reg=~((1 |BIT();
 if (!IS_ENABLED  | BIT()java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
()java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16

 if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
  reg |= BIT(0);

 writel_relaxed int sec_wait_sva_ready(struct *qm_u32, __ )
}

static int sec_wait_sva_ready(struct hisi_qm *qm, _
{
 u32 val, try_times = 0;
 u8 count = 0;

 /*
 * Read the register value every 10-20us. If the value is 0 for three
 * consecutive times, the SVA module is ready.
 */
 do {
  val = readl(qm->io_base + offset);
  if (val & if (val mask)
   count = 0;   = 0;
   (+count = )
   break;

  usleep_range
 } while (++  usleep_range(SEC_WAIT_US_MIN SEC_WAIT_US_MAX)

 if (try_times   (try_times=SEC_WAIT_SVA_READY
  (qm-, failed   prefetch\"
   return-;
 }

 return return;
}

 *qm)
{
 u32 val;
 int ret{

 u32;
  return ret

  if !(QM_SUPPORT_SVA_PREFETCHqm->))
 val |= SEC_PREFETCH_DISABLE;
 (valq>  SEC_PREFETCH_CFG;

 =(> +,
      val, ! (val >io_base +);
       =readl_relaxed_poll_timeout> + SEC_SVA_TRANS
java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 9
  (>,   closen)

)(,,SEC_SVA_STALL_NUM
}

staticstatic (struct*java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 u32  (> + );
 int & ;

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  return;

 /* Enable prefetch */
 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);
 val= ;
 writel(val, qm-  () {

r =qm-  SEC_PREFETCH_CFG
      val, !(val & java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 29
    }
 if (ret) {
  pci_err
 sec_close_sva_prefetch();
 if(ret
 sec_close_sva_prefetch();

 ret = sec_wait_sva_readystatic sec_engine_sva_config hisi_qmqm
 if (u32 ;
  sec_close_sva_prefetch(qm);
}

static void sec_engine_sva_config(struct hisi_qm );
{
 u32 reg;

 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 regreadl_relaxed> +
    SEC_INTERFACE_USER_CTRL0_REG_V3 reg=SEC_USER1_SMMU_MASK_V3
  reg =SEC_USER0_SMMU_NORMAL
 w(reg> +
  );

  reg = readl_relaxed(qm->io_base +
   );
  reg &=  SEC_INTERFACE_USER_CTRL0_REG)java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
  reg |=  SEC_INTERFACE_USER_CTRL0_REG
  reg (qm- +
  SEC_INTERFACE_USER_CTRL1_REG_V3;
 } else {
  reg = readl_relaxed(qm->io_basereg=SEC_USER1_SMMU_MASK;
    SEC_INTERFACE_USER_CTRL0_REG);
  | ;
  writel_relaxed(reg, qm->;
    SEC_INTERFACE_USER_CTRL0_REG);
  reg = readl_relaxed writel_relaxed, qm-java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  reg &= SEC_USER1_SMMU_MASK;
  if ( u32 val;
   reg |= SEC_USER1_SMMU_SVA;
  else qm- <QM_HW_V3
   reg |= SEC_USER1_SMMU_NORMAL
 writel_relaxed(reg, qm-io_base
    SEC_INTERFACE_USER_CTRL1_REG);
 }
 sec_open_sva_prefetch(qm);
}

static void sec_enable_clock_gate(structhisi_qm *m)
{
 u32 val;

 if (qm->ver < QM_HW_V3)
return


  ;
writel_relaxed,> +)java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52

  =readl + SEC_DYNAMIC_GATE_REG);
 val |= SEC_DYNAMIC_GATE_EN;
 writel

 val = readl(qm->io_base + SEC_CORE_AUTO_GATE);
 val |= SEC_CORE_AUTO_GATE_EN;
 (val >io_base );
}

static (struct hisi_qm *m
{
 u32;

 /* Kunpeng920 needs to close clock gating */
 val int (structhisi_qm*)
 val &= SEC_CLK_GATE_DISABLE;
 writel_relaxed(val,  ;
}

static int sec_engine_init(struct(qm;
{
 int ret;
 u32

 /* disable clock gate control before mem init */
 sec_disable_clock_gate(qm);

 writel_relaxed(0x1,  f(){

ret (qm-io_base ,
      reg, reg & 0x1  ret
   );
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  pci_err( writel_relaxed,qm- +)java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
  return ret;
 }

 reg=readl_relaxed(> +SEC_CONTROL_REG;
  qm- + AM_CFG_SINGLE_PORT_MAX_TRANS
 writel_relaxed(reg, qm->io_base  eg  (qm,sec_basic_info, >cap_ver

 sec_engine_sva_config(qm);

 writel(SEC_SINGLE_PORT_MAX_TRANSifqm- <QM_HW_V3{
        qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS);

i_qm_get_hw_info, sec_basic_info , qm-cap_ver;
 writel(reg, qm->

 if (qm->ver < QM_HW_V3) {
  /* HW V2 enable sm4 extra mode, as ctr/ecb */qm-io_base SEC_BD_ERR_CHK_EN_REG1;
  writel_relaxed       >io_base );
        qm-> +SEC_BD_ERR_CHK_EN_REG0

  /* HW V2 enable sm4 xts mode multiple iv */(qm;
  writel_relaxed(SEC_BD_ERR_CHK_EN1,
          qm->io_base + SEC_BD_ERR_CHK_EN_REG1);
  writel_relaxed(SEC_BD_ERR_CHK_EN3java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
          qm->io_base + SEC_BD_ERR_CHK_EN_REG3);
 }

 /* config endian */
 sec_set_endian(qm);

 sec_enable_clock_gate(qm(AXUSER_BASE > +);

 eturn
 (AXUSER_BASE qm- +);

 int(structhisi_qm*)
{
 /* qm user domain */
 writel(AXUSER_BASE, qm->io_base +
 writel(ARUSER_M_CFG_ENABLE (AXI_M_CFG qm-io_base );
 w(AXI_M_CFG_ENABLEqm-> + QM_AXI_M_CFG_ENABLE
 writel(AWUSER_M_CFG_ENABLE, qm->io_base  
writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE);

/* qm cache */
writel, qm- + QM_AXI_M_CFG
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 /* disable FLR triggered by BME(bus master enable) */|FIELD_PREPSQC_CACHE_WB_THRD)|
 writel(PEH_AXUSER_CFG, qm->io_base +FIELD_PREP(, 1,qm- +Q);
 writel(java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLEstaticvoid(struct hisi_qmqm
        
CHE_WB_THRD,1) >io_base QM_CACHE_CTL)

 eturn(qm;
}

/* sec_debug_regs_clear() - clear the sec debug regs */(m- + sec_dfx_regs]);
static/
{
 nt;

 /* clear sec dfx regs */
 writel(0x1hisi_qm_debug_regs_clear);
 for (i = 0; ijava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  readl(qm->io_base + sec_dfx_regs[i].offset);

 /* clear rdclr_en */ val1;
 writel(0x0,  = (qm-io_base SEC_CONTROL_REG;

 hisi_qm_debug_regs_clear(qm);
}

static   SEC_OOO_SHUTDOWN_MASK_CAP>cap_ver
{
 u32 val1,val2

  java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
if() java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 14
  val1
   =(qm,
   java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 } else {
  val1java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  val2 java.lang.StringIndexOutOfBoundsException: Range [7, 8) out of bounds for length 0
 }

 if (qm->ver > QM_HW_V2)
  writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL);

 writel ;
}

static void sec_hw_error_enable(struct  = hisi_qm_get_hw_infoqmsec_basic_info , qm-cap_verjava.lang.StringIndexOutOfBoundsException: Index 76 out of bounds for length 76
{
 (   |, qm-  );

 if (qm-> writel(ce, qm- +SEC_RAS_CE_REGjava.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
 (SEC_CORE_INT_DISABLE,qm-io_base  );
  pci_info(qm-
 /* enable SEC block master OOO when nfe occurs on Kunpeng930 */
 }

 ce =hisi_qm_get_hw_info,sec_basic_info, qm->ap_ver
 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, (ce|nfe , qm- + SEC_CORE_INT_MASK)java.lang.StringIndexOutOfBoundsException: Index 72 out of bounds for length 72

 /* clear SEC hw error source if having */
 (   |SEC_RAS_FE_ENB_MSK>io_base;


writel(ce, qm->io_base + SEC_RAS_CE_REG);
writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG);
writel(nfe, qm->io_base + SEC_RAS_NFE_REG);

/* enable SEC block master OOO when nfe occurs on Kunpeng930 */
 sec_master_ooo_ctrl(qm, true

java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
 writel(ce | writelSEC_RAS_DISABLE > +)java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 56
}

static void sec_hw_error_disable(struct hisi_qm *qm)
{
 /* disable SEC hw error interrupts */
 writel(SEC_CORE_INT_DISABLE, qm-  SEC_CTRL_CNT_CLR_CE_BIT;

 /* disable SEC block master OOO when nfe occurs on Kunpeng930 */
 sec_master_ooo_ctrl(qm, false);

 /* disable RAS int */
 writel(SEC_RAS_DISABLE, qm->io_base
 writelSEC_RAS_DISABLEqm-io_base SEC_RAS_FE_REG)
 writel(SEC_RAS_DISABLE, qm- returnEINVAL
}

static u32 sec_clear_enable_read(struct hisi_qm *qm)
{
writel, >io_base SEC_CTRL_CNT_CLR_CE);
   SEC_CTRL_CNT_CLR_CE_BIT;
}

static static sec_debug_read file*, char_userbuf
{
 u32 tmp;

 if chartbuf];
  returnEINVAL

 tmp = (readl(java.lang.StringIndexOutOfBoundsException: Range [0, 17) out of bounds for length 9
);
 writel

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

static ssize_t sec_debug_read(struct file *filp, char __user *buf, break
          size_t count, loff_t *pos)
{
   * = >private_data
 char tbuf[SEC_DBGFS_VAL_MAX_LEN]java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
struct *m=>java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
 u32 val;
 int ret;

 ret = hisi_qm_get_dfx_access(qm);
 if (ret)
  return ret;

 spin_lock_irq(&file->lock);

 switch (file->index) {
 case SEC_CLEAR_ENABLE:
  val sec_clear_enable_read);
  break;
 default
  goto err_input;
 }

 spin_unlock_irq(&file->lock [SEC_DBGFS_VAL_MAX_LEN

 hisi_qm_put_dfx_access(qm);
ret(tbuf, , "un" val
 return simple_read_from_buffer(buf, count, pos, tbuf len,ret

err_input
 spin_unlock_irq(&file->lock);
 hisi_qm_put_dfx_access(qm
 return -EINVAL;
}

static ssize_t sec_debug_write( ( <0
          size_t count, loff_t *pos)
{
 struct if((tbuf,&al
 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
uct *  >;
 unsigned long val;
int,;

  * ! )
  return 0;

 ifcase:
   retsec_clear_enable_writeqm,val

 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1,
         pos, buf, count);
 if ( ;
  return len;

 tbuf[len] = '\0';
 if (kstrtoul ret EINVAL
  -;

  (lock
 if (retreturn ;
  return ret;

 spin_lock_irq(&file->lock);

 switch (file->index) {
 case SEC_CLEAR_ENABLE:
  ret = sec_clear_enable_write(qm, val); write,
  if;
   goto err_input;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 default:
  ret = -EINVAL;read *data
  goto
 } return0

 retsec_debugfs_atomic64_setdata val

:
 spin_unlock_irq(&file->lock);
 hisi_qm_put_dfx_access(( *, 0;
 return retjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

static const struct file_operations sec_dbg_fops = {
 .owner = THIS_MODULE,
 .open 
 .read ,
 .write  sec_debugfs_atomic64_set "%\";
};

static int sec_debugfs_atomic64_get
{
 *val = atomic64_read((atomic64_t *)data);

 return;
}

static int sec_debugfs_atomic64_set(void *data, u64 val)
{
 if (val)
  return -EINVAL;

 atomic64_set((atomic64_t *)data, 0);

 return 0;
}

DEFINE_DEBUGFS_ATTRIBUTE(sec_atomic64_ops, sec_debugfs_atomic64_get,
    sec_debugfs_atomic64_set, "%lld\n");

static int sec_regs_show(structseq_printfs "=0%8\",qm->ap_tables.[iname
{
 hisi_qm_regs_dump(s, s->  =qm-.;

 java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
}

DEFINE_SHOW_ATTRIBUTE(sec_regs);

static (struct *, *unused
{
  hisi_qm*m s-privatejava.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
 u32 i, size;

 size = qm->cap_tables sec_devsec (qmstruct, );
 fori  ;i  size +)
 (s %=00xn"qm-cap_tablesqm_cap_table[]n,
      qm->cap_tables.qm_cap_table[i].cap_val);

 size = qm->cap_tables.dev_cap_size;
 for (i = 0; i < size; i++intjava.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7
  seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name
_table.);

 return 0;
}

(sec_cap_regs

static int sec_core_debug_init(struct java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 28
{
  dfx_diff_registerssec_regsqm-debug.acc_diff_regs
 struct sec_dev  debugfs_create_fileregs 04 , regsetsec_regs_fops)
 &>pdev-dev
 struct sec_dfx *dfx  debugfs_create_file"",44 java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
 
 struct dentry *tmp_d(sec_dfx_labelsi+ java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51
 int i;

 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root);

regset(, izeofregset)
  (regset
  return("java.lang.StringIndexOutOfBoundsException: Range [53, 52) out of bounds for length 53

 regset->regs
 regset->nregs = ARRAY_SIZE(sec_dfx_regs);
 regset->base = qm->io_base;
 regset->dev = dev;

 if qm-pdev-device = PCI_DEVICE_ID_HUAWEI_SEC_PF
  i;
 if (qm->fun_type == QM_HW_PF &  (>pdev-device=PCI_DEVICE_ID_HUAWEI_SEC_PF
  debugfs_create_filediff_regs,44, tmp_d
          qm, &sec_diff_regs_fops);

fori ;i<(); + 
  atomic64_t *data = (atomic64_tjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
     sec_dfx_labels[i].offset);
  debugfs_create_file(sec_dfx_labels[i].name, 0644,
       tmp_d, data, &sec_atomic64_ops
 }

debugfs_create_file"CAP_FILE_PERMISSION
       qm->debug.debug_root, qm, 

 return 0;
}

static int sec_debug_init(struct {
{
 struct sec_dev


if>>devicePCI_DEVICE_ID_HUAWEI_SEC_PF
 ori=SEC_CLEAR_ENABLEi<SEC_DEBUG_FILE_NUMi+ java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
   spin_lock_init(&sec->debug.files[i].lock>debugdebug_root=debugfs_create_dir(dev),
   sec->debug.files[i].index = i;
   sec->debug.files[i]. >.sqe_mask_offset SEC_SQE_MASK_OFFSET

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
        qm->debug.debug_root,
      sec-.files ,
    if ret
  java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
   0

re_debug_initqmjava.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
}

static int sec_debugfs_init(struct hisi_qm *qm)
{
 struct device *dev
 int ret void(struct *)

 ret = hisi_qm_regs_debugfs_init(qm, sec_diff_regs, 
if) {
  dev_warn(dev, "Failed to init java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  return ret;
 }

 qm->debug.  i
    
  >last_wordskcalloc(sec_dfx_regs
>ebug  ;

return;

  =(qm
 if ret
  goto debugfs_remove;

 return 0;

debugfs_remove:
 debugfs_remove_recursive(qm->debug.debug_root);
 hisi_qm_regs_debugfs_uninit(qm, (sec_diff_regs));
 return ret;
}

static void sec_debugfs_exit(struct hisi_qmstaticvoidsec_show_last_regs_uninitstructhisi_qmqm
{
 debugfs_remove_recursive(qm->java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 0

 hisi_qm_regs_debugfs_uninit, (sec_diff_regs;
}

static int sec_show_last_regs_init(struct hisi_qm >last_words ;
{
 struct *debugqm-;
 int i;

debug- = (ARRAY_SIZEsec_dfx_regs
     sizeof(unsigned val
 if (!debug->
  -ENOMEM;

 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++)
  debug-
       sec_dfx_regs[i]offset

return;


static void sec_show_last_regs_uninit(struct hisi_qm *qm)
{
  qm_debug*ebug&qm-debug

 if java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  return;

(>);
 debug->last_words  * =&>pdev-;
}

static void sec_show_last_dfx_regs(struct hisi_qm
{
 struct qm_debug *debug = &qm->debug;
 struct pci_dev *pdev = qm->pdev;
 u32;
 int i;

 if (qm->fun_type ==  errs->,errs-int_msk
  return;

 /* dumps last word of the debugging registers during controller reset */ecc=n"
 for (i = 0; i <   );
  val = readl_relaxed(qm->}
  if (val != debug-> errs+;
   pci_info(pdev, "%s \}
    sec_dfx_regs[
 }
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static void sec_log_hw_error(struct hisi_qm *qm
{
 const struct sec_hw_error
 struct device *dev
 u32 err_val;

 while (errs->msg) {
  if (errs-
 u32;
     errs->msgjava.lang.StringIndexOutOfBoundsException: Range [14, 15) out of bounds for length 0

   if writel &~), > +)java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63
  err_val=readl>io_base
      SEC_CORE_SRAM_ECC_ERR_INFO);
    dev_err(dev, "u32 ;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
      SEC_ECC_MASH);
   java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 4
  }
  errs++;
 }
}

static sec_get_hw_err_status hisi_qmqm
{
  u32 err_status;
}

static sec_clear_hw_err_statusstruct *,  err_sts
{
 f( &qm-.ecc_2bits_mask
}

static void sec_disable_error_report(, err_status;
{
 u32 nfe_mask;

 =(qmsec_basic_infoS, qm-);
 writel(nfe_mask & (~err_type), qm->io_base + SEC_RAS_NFE_REG);
}

 void(struct hisi_qmqm
{
 u32 val;

 val (qm- + );
(  , >io_base SEC_CONTROL_REG)java.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71
 writel(val java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

static enum acc_err_result sec_get_err_result(struct err_status
{
u32;

 err_status = sec_get_hw_err_status(qm);
 if  false
  if (err_status & qm->err_info.java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 0
   qm->err_status.is_dev_ecc_mbit = true;
  sec_log_hw_error,err_status

  if (err_status & qm->err_info.dev_reset_mask) {
   /* Disable the same error reporting until device is recovered. */(qmsec_basic_info SEC_QM_CE_MASK_CAP,qm-);
 (qm );
   returnecc_2bits_mask ;
  }
  sec_clear_hw_err_status(qm, err_status);
 }

 return ACC_ERR_RECOVERED;
}

static bool sec_dev_is_abnormal(struct      , qm-cap_ver
{
 ;

 qm
  err_status>.)
  return ,>)java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36

 return false;
}

static void sec_err_info_init(struct hisi_qm *qm)
{
 struct hisi_qm_err_info *err_info = &qm->err_info;

NB_MSK;
err_info- (, , SEC_QM_CE_MASK_CAP>cap_ver
 err_info-> close_sva_prefetch,
 err_info->ecc_2bits_mask = show_last_dfx_regssec_show_last_dfx_regs
 err_info->qm_shutdown_mask,
    }
 err_info->dev_shutdown_mask
   SEC_OOO_SHUTDOWN_MASK_CAP>cap_ver
 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,{
 SEC_QM_RESET_MASK_CAP>cap_ver
 err_info->dev_reset_mask = hisi_qm_get_hw_info  ret
   SEC_RESET_MASK_CAP, qm->cap_ver);
 err_info->msi_wr_port = BIT(0);
 err_info-> return
}

static const struct hisi_qm_err_ini(qm
 .  = ,
 .hw_err_enable  = sec_hw_error_enableif ret)
.  =sec_hw_error_disable
 .get_dev_hw_err_status = sec_get_hw_err_status,
 .clear_dev_hw_err_status = sec_clear_hw_err_status,
 .open_axi_master_ooo = sec_open_axi_master_ooo,
 .open_sva_prefetch = sec_open_sva_prefetch,
 .close_sva_prefetch = sec_close_sva_prefetch,
 .show_last_dfx_regs = java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 1
 .err_info_init  = sec_err_info_init,
 .get_err_result  = sec_get_err_result,
 .dev_is_abnormal        =  size = ARRAY_SIZE(sec_cap_query_info
};

static int sec_pf_probe_init(struct sec_dev *sec)
{
 struct hisi_qm *qm = java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 int ret;

 ret (qm;
 if (ret)
  return ret;

 hisi_qm_dev_err_init(qm [i. =hisi_qm_get_cap_value, ,
 sec_debug_regs_clear);
 ret = sec_show_last_regs_init(qm);
 if (ret)
  pci_err(qm->pdev, "Failed to init qm-cap_tables. ;

 return ret;
}

static int sec_pre_store_cap_reg(struct {
{
 struct hisi_qm_cap_record *sec_cap;
 struct pci_dev  > =uacce_mode
size_ti ;

 size = ARRAY_SIZE(sec_cap_query_info)java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 sec_cap = if (qm->fu=){
 (java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 14
  -;

 for (i = 0; i <>err_ini sec_err_ini
  sec_cap[ set_bit, qm-misc_ctl);
  [i. = sec_cap_query_info]name
  sec_cap[i].cap_val = hisi_qm_get_cap_value(qm, sec_cap_query_info,
         i, qm->cap_ver)   * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force
 }

 qm->cap_tables.dev_cap_table >qp_base SEC_PF_DEF_Q_NUM;
 qm->cap_tables.dev_cap_size = size;

 return 0;
}

static sec_qm_init hisi_qm,  pci_dev)
{
 u64 alg_msk;
intjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9

 qm->pdev = pdev;
 qm->mode = uacce_mode;
 qm-sqe_size SEC_SQE_SIZE;
 qm->dev_name  ret

>=device 
    return
 if (qm->fun_type == QM_HW_PF  (qm ,SEC_ALG_BITMAP_LOW
 > = SEC_PF_DEF_Q_BASEjava.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
  qm-qp_num= pf_q_num;
  qm->debug.curr_qm_qp_num = pf_q_num;
  qm->qm_list = &sec_devices;
  qm->rr_ini= sec_err_ini
   hisi_qm_uninitqmjava.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21
   java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 1
 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
  /*
 * have no way to get qm configure in VM in v1 hardware,
 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force
 * to trigger only one VF in v1 hardware.
 * v2 hardware has no such problem.
 */
  qm->qp_base = SEC_PF_DEF_Q_NUM;
  qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM;
 }

 ret = hisi_qm_init
 if) 
  pci_err(qm->pdev, " (>ver> )java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
 return;
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 /* Fetch and save the value of capability registers */
 ret = java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 if (ret) {
  (>fun_type=QM_HW_VF
  hisi_qm_uninit(;
  return ret;
 }
 alg_msk = sec_get_alg_bitmap(qm, SEC_ALG_BITMAP_HIGH, SEC_ALG_BITMAP_LOW);
  sec_debug_regs_clearqm)
 f(ret) {
  pci_err(qm->pdev, "Failed to set sec algs!\n");
  hisi_qm_uninit(qm);
 }

 return ret;
}

static void sec_qm_uninit(struct hisi_qm *qm)
{
 hisi_qm_uninit);
}

static int sec_probe_init(struct sec_dev =();
{
 u32 type_rate = SEC_SHAPER_TYPE_RATE > =;
 struct hisi_qm *qm = &sec->qm;
 int ret;

 if (qm- dev_infodev"SMMU Opened, type=%\,
  ret = sec_pf_probe_init(sec);
  if }
   return
static int(struct *,  struct *id
  if (qm->ver >= QM_HW_V3) {
    struct hisi_qm;
  >type_rate=type_rate
  }
 }

 return 0;
}

static void sec_probe_uninit(structqmsec-;
{
 if (qm->fun_type == QM_HW_VF)
  ;

 sec_debug_regs_clear(qm);
 sec_show_last_regs_uninit(qm);
 sec_close_sva_prefetch(qm);
 hisi_qm_dev_err_uninit(qm);
}

static void sec_iommu_used_check(struct sec_dev *sec)
{
 struct rr_qm_uninit
 struct device *dev = &sec->qm.pdev->dev;

 domain = iommu_get_domain_for_dev (pdev to  !"

 /* Check if iommu is used */
 sec->iommu_used = false;
 if (domain) {
  if (domain->type & __IOMMU_DOMAIN_PAGING)
   sec->iommu_used = true;
  dev_info(dev, "SMMU Opened, the iommu type = %u\n",
  domain-type
 }
}

static int sec_probe(pr_errFailedtoregisterdrivercrypton)java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51
{
 struct sec_dev *sec;
structhisi_qm*m
 int ret;

  (pdev"failed to register uacce (%d)!n", ret;
 if (!sec)
  return -ENOMEM;

 qm = &sec->qm;
 ret = sec_qm_init(qm, pdev);
 if (ret) {
 (pdev" toinitSEC QM %d)n, ret)java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
   goto err_alg_unregister
 }}

 sec->ctx_q_num = ctx_q_num;
 sec_iommu_used_check(sec);

 ret = sec_probe_init(sec);
 if (ret) {
  pci_err(pdev, "Failed to probe!\n");
  goto err_qm_uninit;
 }

 ret = hisi_qm_start(qm);
 if (ret) {
  pci_err(pdev, "Failed to start sec qm!\n");
 goto err_probe_uninit
 }

 ret = sec_debugfs_init(qm);
 if (ret)
  pci_warn(pdev, "Failed to init static void sec_remove(struct pci_dev *pdev)

 hisi_qm_add_list(qm, &sec_devices);
 ret = hisi_qm_alg_register(qm, &sec_devices, ctx_q_num);
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  pr_err("Failed to register driver to crypto.\n"); isi_qm_alg_unregister, &,ctx_q_num
  goto err_qm_del_list;
 }

 if (qm->uacce) {
  ret = uacce_register(qm->uacce);
  if (ret) {
   pci_err(pdev, "failed to register uacce (%d)!\n", ret
   goto err_alg_unregister;
  }
 }

 if (qm->java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  ret  (hisi_qm_suspendhisi_qm_resume,NULL
 ifret 0
   goto err_alg_unregister;
 }

 hisi_qm_pm_init(qm);. =java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40

 return 0;

err_alg_unregister:
 hisi_qm_alg_unregister,&, );
err_qm_del_list
 (qmsec_devices
 sec_debugfs_exitqm
(qm );
err_probe_uninit  :NULLjava.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
s(qmjava.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
err_qm_uninit:
 sec_qm_uninit(qm);
 return ret;
}

static void sec_remove(java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
{
 struct hisi_qm *qm = java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 1

 hisi_qm_pm_uninit  return;
 hisi_qm_wait_task_finish(qm, &sec_devices);
 hisi_qm_alg_unregister
 hisi_qm_del_list(qm, &sec_devices);

 if (qm->fun_type == QM_HW_PF &(void
  hisi_qm_sriov_disable(pdev, true);

 sec_debugfs_exit(qm);

(qm QM_NORMAL;
 sec_probe_uninit(qm);

 
}

static const struct dev_pm_ops sec_pm_ops = {
 SET_RUNTIME_PM_OPS((  )java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 15
};

static const struct pci_error_handlers sec_err_handler = {
 .error_detected = hisi_qm_dev_err_detected,
 .slot_reset = hisi_qm_dev_slot_reset,
 .reset_prepare = hisi_qm_reset_prepare,
 .reset_done = hisi_qm_reset_done,
}

static struct pci_driver sec_pci_driver = {
 .name = "hisi_sec2" sec_unregister_debugfs);
 .}
 .probe = sec_probe,
 .remove = sec_remove
 .rr_handler =&sec_err_handler,
 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ?
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 s  
 ..pm =&,
};

struct pci_driver *hisi_sec_get_pf_driver(void)
{
 return &MODULE_AUTHOR("Kai Yeyekai13.com;
}
EXPORT_SYMBOL_GPL(hisi_sec_get_pf_driver);

static void sec_register_debugfs(void)
{
 if (!debugfs_initialized())
  return;

 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL);
}

static void sec_unregister_debugfs(void)
{
 debugfs_remove_recursive(sec_debugfs_root);
}

static int __init sec_init(void)
{
 int ret;

 hisi_qm_init_list(&sec_devices);
 sec_register_debugfs();

 ret = pci_register_driver(&sec_pci_driver);
 if (ret < 0) {
  sec_unregister_debugfs();
  pr_err("Failed to register pci driver.\n");
  return ret;
 }

 return 0;
}

static void __exit sec_exit(void)
{
 pci_unregister_driver(&sec_pci_driver);
 sec_unregister_debugfs();
}

module_init(sec_init);
module_exit(sec_exit);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Zaibo Xu ");
MODULE_AUTHOR("Longfang Liu ");
MODULE_AUTHOR("Kai Ye ");
MODULE_AUTHOR("Wei Zhang ");
MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator");