Quelle  cc_host_regs.h   Sprache: C

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2012-2019 ARM Limited or its affiliates. */

#ifndef __CC_HOST_H__
#define __CC_HOST_H__

// --------------------------------------
// BLOCK: HOST_P
// --------------------------------------


/* IRR */
#define CC_HOST_IRR_REG_OFFSET 0xA00UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SHIFT 0/
#define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SIZE0x1UL
#define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT 0x2UL
defineCC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SHIFT 0x3UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SHIFT 0x4UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SHIFT 0x5UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SHIFT 0x6UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SHIFT 0x7UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL
#define CC_HOST_IRR_AXI_ERR_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SHIFT 0x9UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SHIFT 0xAUL
#define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_GPR0_BIT_SHIFT 0xBUL
#define CC_HOST_IRR_GPR0_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SHIFT 0xCUL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SHIFT 0xDUL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SHIFT 0xEUL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SHIFT 0xFUL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SHIFT 0x10UL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SHIFT 0x11UL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SHIFT 0x12UL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT 0x13UL
#define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SHIFT 0x14UL
#define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SIZE 0x1UL
#define CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT 0x17UL
#define CC_HOST_IRR_AXIM_COMP_INT_BIT_SIZE 0x1UL
#define CC_HOST_SEP_SRAM_THRESHOLD_REG_OFFSET 0xA10UL
#define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SHIFT 0x0UL
#define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SIZE 0xCUL

/* IMR */
#define CC_HOST_IMR_REG_OFFSET 0x0A04UL
#define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT 0x1UL
#define// BLOCK: // --------------java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFTdefine 0x1UL
## CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SHIFT 0x3UL
#define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT 0x3UL
#define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SIZE 0x1UL
#define #define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SIZE
defineCC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SIZEx1UL# CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SIZE01UL
#defineCC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFTx5UL
#define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SIZE 0x1UL CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SIZEx1UL
defineCC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT 0x6UL
#define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SIZE 0x1UL
#define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT 0x7UL
#define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SIZE 0x1UL
#define CC_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL
#defineCC_HOST_IMR_AXI_ERR_MASK_BIT_SIZEx1UL
#define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT0x9UL
#define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SIZE 0x1UL
# CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT0xAUL
#define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SIZE 0x1UL
#define CC_HOST_IMR_GPR0_BIT_SHIFT 0xBUL
#define CC_HOST_IMR_GPR0_BIT_SIZE 0x1UL
#efine CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFTxCUL
#defineCC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SIZE
# CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFTxDUL
 0x1UL
#define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT 0xEUL# CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SHIFT 0
#define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SIZE
#define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT 0# CC_HOST_IRR_GPR0_BIT_SHIFT0java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
#define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SIZEjava.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
#define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT 0x10UL CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SHIFT
#define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SIZEjava.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
#define #efineCC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SIZEx1UL 0x10UL
#define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SIZE
#define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SHIFT
# CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SIZEx1ULdefine 0x12UL
#defineCC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SIZEx1UL
#define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL
#define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT 0x14UL
d CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SIZE0x1UL
#define# CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE01L
#define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL

/* ICR */
#define CC_HOST_ICR_REG_OFFSETdefineCC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SHIFT
# CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT02UL
#define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE01UL
#define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL
#define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE 0x1UL
#define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT 0xBULdefine 0x1UL
#defineCC_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE
#define# CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SHIFTx0L
#define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE
#define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0
#defineCC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE
#define #define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT
#define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT  0x0UL
#define CC_NVM_IS_IDLE_VALUE_BIT_SIZE   0x1UL
#define CC_SECURITY_DISABLED_REG_OFFSET  0x0A1CUL
#define CC_SECURITY_DISABLED_VALUE_BIT_SHIFT 0x0UL 0
define 0x1UL
#define CC_HOST_SIGNATURE_712_REG_OFFSET# CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFTjava.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 61
#define CC_HOST_SIGNATURE_630_REG_OFFSET 0x5UL
#define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL
#define CC_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL
#define CC_HOST_BOOT_REG_OFFSET 0xA28UL
#define CC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0#efineCC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT
#defineCC_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE
#define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT# CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT x7UL
#define CC_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL
#define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT 0x2UL
#define CC_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZEdefine 0x1UL
#define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT # CC_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL
#define CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE 0x1UL
##defineCC_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL
#define CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE 0x1UL
#define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL
#define CC_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE 0# CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SIZEx1UL
defineCC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFTx9UL
#define CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE 0x1UL
#define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT 0xAUL
#define CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL
#define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SIZEx1UL
#define CC_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZEx1UL
#define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT 0xCUL
#define CC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL
#define #define CC_HOST_IMR_GPR0_BIT_SIZE0java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
# CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT
#define CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFTjava.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 56
# CC_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZEx1UL
#define#define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SIZEjava.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
#define CC_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SIZE
#define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFTx10UL
#define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE 0x1UL
#define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT 0x11UL
#define CC_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE
#define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT#define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFTx12UL
#define CC_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE 0x1UL
#define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT 0x13UL
#define CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZEdefineCC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SIZE0
 CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT0java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63
#defineCC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT
#efine CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT 0x15UL
# CC_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE0
#define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFTx16UL
#define CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE 0x1UL
#define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL
#define CC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZEjava.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
#define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT 0x18UL# CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT0x2UL
#define CC_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZEx1UL
#define #define CC_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL
#define CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZEx1UL
#define CC_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFTxBUL
#defineCC_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE
#define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFTdefineCC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFTx13UL
#define CC_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE 0x1UL
#define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT 0x1CUL
#define CC_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT
#define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT0x1DUL
#define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL
#define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFTx1EUL
#define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL
#define CC_HOST_VERSION_712_REG_OFFSET 0xA40UL
#define CC_HOST_VERSION_630_REG_OFFSET0xAD8UL
#define CC_HOST_VERSION_VALUE_BIT_SHIFT0java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
#define CC_HOST_VERSION_VALUE_BIT_SIZE 0x20UL
#define CC_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL
#define CC_HOST_KFDE0_VALID_VALUE_BIT_SHIFT 0x0UL
#define CC_HOST_KFDE0_VALID_VALUE_BIT_SIZEx1UL
#define CC_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL
#define CC_HOST_KFDE1_VALID_VALUE_BIT_SHIFT 0x0UL
#define CC_HOST_KFDE1_VALID_VALUE_BIT_SIZEx1UL
#define CC_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL
#define CC_HOST_KFDE2_VALID_VALUE_BIT_SHIFT 0x0UL
#define CC_HOST_KFDE2_VALID_VALUE_BIT_SIZE0java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
#define CC_HOST_KFDE3_VALID_REG_OFFSET0xA6CUL
#define CC_HOST_KFDE3_VALID_VALUE_BIT_SHIFT 0x0UL
#define CC_HOST_KFDE3_VALID_VALUE_BIT_SIZE 0x1UL
#define CC_HOST_GPR0_REG_OFFSETdefineCC_HOST_SIGNATURE_VALUE_BIT_SHIFT
defineCC_HOST_GPR0_VALUE_BIT_SHIFT 0x0UL
# CC_HOST_GPR0_VALUE_BIT_SIZEx20UL
 CC_GPR_HOST_REG_OFFSET0java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
#defineCC_GPR_HOST_VALUE_BIT_SHIFTjava.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
#define CC_GPR_HOST_VALUE_BIT_SIZEx20UL
# CC_HOST_POWER_DOWN_EN_REG_OFFSET0A78UL
# 0x0UL
#define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE 0x1UL
#define CC_HOST_REMOVE_INPUT_PINS_REG_OFFSETx0A7CUL
#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SHIFT CC_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT
#defineIZE 0x1UL
#define# CC_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT
#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SIZE
  0
#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SIZE
#define# CC_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT
#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SIZE
#define # CC_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFTxAUL
#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SIZE 01java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
#defineCC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SHIFT
#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SIZE  0xCUL
##efineCC_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZEx1UL
define 0x1UL
#define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SHIFT 0x7UL
#define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SIZE
// --------------------------------------
// BLOCK: ID_REGISTERS
// --------------------------------------
#define CC_PERIPHERAL_ID_4_REG_OFFSET 0x0FD0UL
##efine 0x1UL
#define CC_PERIPHERAL_ID_4_VALUE_BIT_SIZE 0x4UL# 0xFUL
# CC_PIDRESERVED0_REG_OFFSET 0x0FD4UL
#define CC_PIDRESERVED1_REG_OFFSETx0FD8UL
#define CC_PIDRESERVED2_REG_OFFSET 0x0FDCUL
#define #define CC_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE
#define CC_PERIPHERAL_ID_0_VALUE_BIT_SHIFT 0x0UL
#define CC_PERIPHERAL_ID_0_VALUE_BIT_SIZE 0x8UL
#define CC_PERIPHERAL_ID_1_REG_OFFSET 0x0FE4UL
#define CC_PERIPHERAL_ID_1_PART_1_BIT_SHIFT 0x0UL
#define CC_PERIPHERAL_ID_1_PART_1_BIT_SIZE 0x4UL
#define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SHIFT 0x4UL
#define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SIZE
#define CC_PERIPHERAL_ID_2_REG_OFFSETx0FE8UL
#define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SHIFT 0x0UL
#define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SIZE 0x3UL
define 0x3UL
#define# CC_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT013UL
#define CC_PERIPHERAL_ID_2_REVISION_BIT_SHIFT 0x4UL
define 0x4UL
#define CC_PERIPHERAL_ID_3_REG_OFFSET 0x0FECUL
#define CC_PERIPHERAL_ID_3_CMOD_BIT_SHIFT 0x0UL
#define CC_PERIPHERAL_ID_3_CMOD_BIT_SIZE 0# CC_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE
#define CC_PERIPHERAL_ID_3_REVAND_BIT_SHIFTx4UL
#define#define  0x1UL
#define # CC_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT
# CC_COMPONENT_ID_0_VALUE_BIT_SHIFT 0x0UL
#define CC_COMPONENT_ID_0_VALUE_BIT_SIZE 0x8UL
#define CC_COMPONENT_ID_1_REG_OFFSET 0x0FF4UL#efineCC_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT
#define CC_COMPONENT_ID_1_PRMBL_1_BIT_SHIFTx0UL
#define CC_COMPONENT_ID_1_PRMBL_1_BIT_SIZE 0x4UL
#define CC_COMPONENT_ID_1_CLASS_BIT_SHIFT  0
#defineCC_COMPONENT_ID_1_CLASS_BIT_SIZE
#define# CC_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE
#define CC_COMPONENT_ID_2_VALUE_BIT_SHIFT 0
#define CC_COMPONENT_ID_2_VALUE_BIT_SIZEdefine 0x1UL
define 0x0FFCUL
define 0x0UL
#define CC_COMPONENT_ID_3_VALUE_BIT_SIZE 0x8UL#define  0x1CUL
// --------------------------------------
// BLOCK: HOST_SRAM
// --------------------------------------
#define CC_SRAM_DATA_REG_OFFSETxF00UL
#define CC_SRAM_DATA_VALUE_BIT_SHIFT 0x0ULdefine 0x1UL
#define CC_SRAM_DATA_VALUE_BIT_SIZE #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT01EUL
define 0xF04UL
#define CC_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL
# 0xFUL
#define CC_SRAM_DATA_READY_REG_OFFSET # CC_HOST_VERSION_630_REG_OFFSET 0xAD8UL
#define CC_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL
#define CC_HOST_VERSION_VALUE_BIT_SIZE02UL

#endif //__CC_HOST_H__