Quelle  am4372.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for AM4372 SoC
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/am4.h>

/ {
 compatible = "ti,am4372", "ti,am43";
 interrupt-parent = <&wakeupgen>;
 #address-cells = <1>;
 #size-cells = <1>;
 chosen { };

 memory@0 {
  device_type = "memory";
  reg = <0 0>;
 };

 aliases {
  i2c0 = &i2c0;
  i2c1 = &i2c1;
  i2c2 = &i2c2;
  serial0 = &uart0;
  serial1 = &uart1;
  serial2 = &uart2;
  serial3 = &uart3;
  serial4 = &uart4;
  serial5 = &uart5;
  ethernet0 = &cpsw_port1;
  ethernet1 = &cpsw_port2;
  spi0 = &qspi;
 };

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;
  cpu: cpu@0 {
   compatible = "arm,cortex-a9";
   enable-method = "ti,am4372";
   device_type = "cpu";
   reg = <0>;

   clocks = <&dpll_mpu_ck>;
   clock-names = "cpu";

   operating-points-v2 = <&cpu0_opp_table>;

   clock-latency = <300000>; /* From omap-cpufreq driver */
   cpu-idle-states = <&mpu_gate>;
  };

  idle-states {
   mpu_gate: mpu_gate {
    compatible = "arm,idle-state";
    entry-latency-us = <40>;
    exit-latency-us = <100>;
    min-residency-us = <300>;
    local-timer-stop;
   };
  };
 };

 cpu0_opp_table: opp-table {
  compatible = "operating-points-v2-ti-cpu";
  syscon = <&scm_conf>;

  opp-50-300000000 {
   /* OPP50 */
   opp-hz = /bits/ 64 <300000000>;
   opp-microvolt = <950000 931000 969000>;
   opp-supported-hw = <0xFF 0x01>;
   opp-suspend;
  };

  opp-100-600000000 {
   /* OPP100 */
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <1100000 1078000 1122000>;
   opp-supported-hw = <0xFF 0x04>;
  };

  opp-120-720000000 {
   /* OPP120 */
   opp-hz = /bits/ 64 <720000000>;
   opp-microvolt = <1200000 1176000 1224000>;
   opp-supported-hw = <0xFF 0x08>;
  };

  opp-800000000 {
   /* OPP Turbo */
   opp-hz = /bits/ 64 <800000000>;
   opp-microvolt = <1260000 1234800 1285200>;
   opp-supported-hw = <0xFF 0x10>;
  };

  opp-1000000000 {
   /* OPP Nitro */
   opp-hz = /bits/ 64 <1000000000>;
   opp-microvolt = <1325000 1298500 1351500>;
   opp-supported-hw = <0xFF 0x20>;
  };
 };

 soc {
  compatible = "ti,omap-infra";
 };

 gic: interrupt-controller@48241000 {
  compatible = "arm,cortex-a9-gic";
  interrupt-controller;
  #interrupt-cells = <3>;
  reg = <0x48241000 0x1000>,
        <0x48240100 0x0100>;
  interrupt-parent = <&gic>;
 };

 wakeupgen: interrupt-controller@48281000 {
  compatible = "ti,omap4-wugen-mpu";
  interrupt-controller;
  #interrupt-cells = <3>;
  reg = <0x48281000 0x1000>;
  interrupt-parent = <&gic>;
 };

 scu: scu@48240000 {
  compatible = "arm,cortex-a9-scu";
  reg = <0x48240000 0x100>;
 };

 global_timer: timer@48240200 {
  compatible = "arm,cortex-a9-global-timer";
  reg = <0x48240200 0x100>;
  interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
  interrupt-parent = <&gic>;
  clocks = <&mpu_periphclk>;
 };

 local_timer: timer@48240600 {
  compatible = "arm,cortex-a9-twd-timer";
  reg = <0x48240600 0x100>;
  interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
  interrupt-parent = <&gic>;
  clocks = <&mpu_periphclk>;
 };

 cache-controller@48242000 {
  compatible = "arm,pl310-cache";
  reg = <0x48242000 0x1000>;
  cache-unified;
  cache-level = <2>;
 };

 ocp@44000000 {
  compatible = "simple-pm-bus";
  power-domains = <&prm_per>;
  clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
  clock-names = "fck";
  #address-cells = <1>;
  #size-cells = <1>;
  ranges;
  ti,no-idle;

  l3-noc@44000000 {
   compatible = "ti,am4372-l3-noc";
   reg = <0x44000000 0x400000>,
         <0x44800000 0x400000>;
   interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  };

  l4_wkup: interconnect@44c00000 {
  };
  l4_per: interconnect@48000000 {
  };
  l4_fast: interconnect@4a000000 {
  };

  target-module@4c000000 {
   compatible = "ti,sysc-omap4-simple", "ti,sysc";
   reg = <0x4c000000 0x4>;
   reg-names = "rev";
   clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
   clock-names = "fck";
   ti,no-idle;
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x4c000000 0x1000000>;

   emif: emif@0 {
    compatible = "ti,emif-am4372";
    reg = <0 0x1000000>;
    interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
    sram = <&pm_sram_code
     &pm_sram_data>;
   };
  };

  target-module@49000000 {
   compatible = "ti,sysc-omap4", "ti,sysc";
   reg = <0x49000000 0x4>;
   reg-names = "rev";
   clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x49000000 0x10000>;

   edma: dma@0 {
    compatible = "ti,edma3-tpcc";
    reg = <0 0x10000>;
    reg-names = "edma3_cc";
    interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-names = "edma3_ccint", "edma3_mperr",
        "edma3_ccerrint";
    dma-requests = <64>;
    #dma-cells = <2>;

    ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
        <&edma_tptc2 0>;

    ti,edma-memcpy-channels = <58 59>;
   };
  };

  target-module@49800000 {
   compatible = "ti,sysc-omap4", "ti,sysc";
   reg = <0x49800000 0x4>,
         <0x49800010 0x4>;
   reg-names = "rev", "sysc";
   ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
   ti,sysc-midle = <SYSC_IDLE_FORCE>;
   ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_SMART>;
   clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x49800000 0x100000>;

   edma_tptc0: dma@0 {
    compatible = "ti,edma3-tptc";
    reg = <0 0x100000>;
    interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-names = "edma3_tcerrint";
   };
  };

  target-module@49900000 {
   compatible = "ti,sysc-omap4", "ti,sysc";
   reg = <0x49900000 0x4>,
         <0x49900010 0x4>;
   reg-names = "rev", "sysc";
   ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
   ti,sysc-midle = <SYSC_IDLE_FORCE>;
   ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_SMART>;
   clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x49900000 0x100000>;

   edma_tptc1: dma@0 {
    compatible = "ti,edma3-tptc";
    reg = <0 0x100000>;
    interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-names = "edma3_tcerrint";
   };
  };

  target-module@49a00000 {
   compatible = "ti,sysc-omap4", "ti,sysc";
   reg = <0x49a00000 0x4>,
         <0x49a00010 0x4>;
   reg-names = "rev", "sysc";
   ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
   ti,sysc-midle = <SYSC_IDLE_FORCE>;
   ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_SMART>;
   clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x49a00000 0x100000>;

   edma_tptc2: dma@0 {
    compatible = "ti,edma3-tptc";
    reg = <0 0x100000>;
    interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-names = "edma3_tcerrint";
   };
  };

  target-module@47810000 {
   compatible = "ti,sysc-omap2", "ti,sysc";
   reg = <0x478102fc 0x4>,
         <0x47810110 0x4>,
         <0x47810114 0x4>;
   reg-names = "rev", "sysc", "syss";
   ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
      SYSC_OMAP2_ENAWAKEUP |
      SYSC_OMAP2_SOFTRESET |
      SYSC_OMAP2_AUTOIDLE)>;
   ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_NO>,
     <SYSC_IDLE_SMART>;
   ti,syss-mask = <1>;
   clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x47810000 0x1000>;

   mmc3: mmc@0 {
    compatible = "ti,am437-sdhci";
    ti,needs-special-reset;
    interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
    reg = <0x0 0x1000>;
    status = "disabled";
   };
  };

  sham_target: target-module@53100000 {
   compatible = "ti,sysc-omap3-sham", "ti,sysc";
   reg = <0x53100100 0x4>,
         <0x53100110 0x4>,
         <0x53100114 0x4>;
   reg-names = "rev", "sysc", "syss";
   ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
      SYSC_OMAP2_AUTOIDLE)>;
   ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_NO>,
     <SYSC_IDLE_SMART>;
   ti,syss-mask = <1>;
   /* Domains (P, C): per_pwrdm, l3_clkdm */
   clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x53100000 0x1000>;

   sham: sham@0 {
    compatible = "ti,omap5-sham";
    reg = <0 0x300>;
    dmas = <&edma 36 0>;
    dma-names = "rx";
    interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
   };
  };

  aes_target: target-module@53501000 {
   compatible = "ti,sysc-omap2", "ti,sysc";
   reg = <0x53501080 0x4>,
         <0x53501084 0x4>,
         <0x53501088 0x4>;
   reg-names = "rev", "sysc", "syss";
   ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
      SYSC_OMAP2_AUTOIDLE)>;
   ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_NO>,
     <SYSC_IDLE_SMART>,
     <SYSC_IDLE_SMART_WKUP>;
   ti,syss-mask = <1>;
   /* Domains (P, C): per_pwrdm, l3_clkdm */
   clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x53501000 0x1000>;

   aes: aes@0 {
    compatible = "ti,omap4-aes";
    reg = <0 0xa0>;
    interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
    dmas = <&edma 6 0>,
          <&edma 5 0>;
    dma-names = "tx", "rx";
   };
  };

  des_target: target-module@53701000 {
   compatible = "ti,sysc-omap2", "ti,sysc";
   reg = <0x53701030 0x4>,
         <0x53701034 0x4>,
         <0x53701038 0x4>;
   reg-names = "rev", "sysc", "syss";
   ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
      SYSC_OMAP2_AUTOIDLE)>;
   ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_NO>,
     <SYSC_IDLE_SMART>,
     <SYSC_IDLE_SMART_WKUP>;
   ti,syss-mask = <1>;
   /* Domains (P, C): per_pwrdm, l3_clkdm */
   clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0 0x53701000 0x1000>;

   des: des@0 {
    compatible = "ti,omap4-des";
    reg = <0 0xa0>;
    interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
    dmas = <&edma 34 0>,
           <&edma 33 0>;
    dma-names = "tx", "rx";
   };
  };

  pruss_tm: target-module@54400000 {
   compatible = "ti,sysc-pruss", "ti,sysc";
   reg = <0x54426000 0x4>,
         <0x54426004 0x4>;
   reg-names = "rev", "sysc";
   ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
      SYSC_PRUSS_SUB_MWAIT)>;
   ti,sysc-midle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_NO>,
     <SYSC_IDLE_SMART>;
   ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_NO>,
     <SYSC_IDLE_SMART>;
   clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
   clock-names = "fck";
   resets = <&prm_per 1>;
   reset-names = "rstctrl";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x54400000 0x80000>;

   pruss1: pruss@0 {
    compatible = "ti,am4376-pruss1";
    reg = <0x0 0x40000>;
    #address-cells = <1>;
    #size-cells = <1>;
    ranges;

    pruss1_mem: memories@0 {
     reg = <0x0 0x2000>,
           <0x2000 0x2000>,
           <0x10000 0x8000>;
     reg-names = "dram0", "dram1",
          "shrdram2";
    };

    pruss1_cfg: cfg@26000 {
     compatible = "ti,pruss-cfg", "syscon";
     reg = <0x26000 0x2000>;
     #address-cells = <1>;
     #size-cells = <1>;
     ranges = <0x0 0x26000 0x2000>;

     clocks {
      #address-cells = <1>;
      #size-cells = <0>;

      pruss1_iepclk_mux: iepclk-mux@30 {
       reg = <0x30>;
       #clock-cells = <0>;
       clocks = <&sysclk_div>,     /* icss_iep_gclk */
         <&pruss_ocp_gclk>; /* icss_ocp_gclk */
      };
     };
    };

    pruss1_mii_rt: mii-rt@32000 {
     compatible = "ti,pruss-mii", "syscon";
     reg = <0x32000 0x58>;
    };

    pruss1_intc: interrupt-controller@20000 {
     compatible = "ti,pruss-intc";
     reg = <0x20000 0x2000>;
     interrupt-controller;
     #interrupt-cells = <3>;
     interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
           <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
           <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
           <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
           <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
           <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
           <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
     interrupt-names = "host_intr0", "host_intr1",
         "host_intr2", "host_intr3",
         "host_intr4",
         "host_intr6", "host_intr7";
     ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
    };

    pru1_0: pru@34000 {
     compatible = "ti,am4376-pru";
     reg = <0x34000 0x3000>,
           <0x22000 0x400>,
           <0x22400 0x100>;
     reg-names = "iram", "control", "debug";
     firmware-name = "am437x-pru1_0-fw";
    };

    pru1_1: pru@38000 {
     compatible = "ti,am4376-pru";
     reg = <0x38000 0x3000>,
           <0x24000 0x400>,
           <0x24400 0x100>;
     reg-names = "iram", "control", "debug";
     firmware-name = "am437x-pru1_1-fw";
    };

    pruss1_mdio: mdio@32400 {
     compatible = "ti,davinci_mdio";
     reg = <0x32400 0x90>;
     clocks = <&dpll_core_m4_ck>;
     clock-names = "fck";
     bus_freq = <1000000>;
     #address-cells = <1>;
     #size-cells = <0>;
    };
   };

   pruss0: pruss@40000 {
    compatible = "ti,am4376-pruss0";
    reg = <0x40000 0x40000>;
    #address-cells = <1>;
    #size-cells = <1>;
    ranges;

    pruss0_mem: memories@40000 {
     reg = <0x40000 0x1000>,
           <0x42000 0x1000>;
     reg-names = "dram0", "dram1";
    };

    pruss0_cfg: cfg@66000 {
     compatible = "ti,pruss-cfg", "syscon";
     reg = <0x66000 0x2000>;
     #address-cells = <1>;
     #size-cells = <1>;
     ranges = <0x0 0x66000 0x2000>;

     clocks {
      #address-cells = <1>;
      #size-cells = <0>;

      pruss0_iepclk_mux: iepclk-mux@30 {
       reg = <0x30>;
       #clock-cells = <0>;
       clocks = <&sysclk_div>,     /* icss_iep_gclk */
         <&pruss_ocp_gclk>; /* icss_ocp_gclk */
      };
     };
    };

    pruss0_mii_rt: mii-rt@72000 {
     compatible = "ti,pruss-mii", "syscon";
     reg = <0x72000 0x58>;
     status = "disabled";
    };

    pruss0_intc: interrupt-controller@60000 {
     compatible = "ti,pruss-intc";
     reg = <0x60000 0x2000>;
     interrupt-controller;
     #interrupt-cells = <3>;
     interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
           <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
           <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
           <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
           <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
           <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
           <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
     interrupt-names = "host_intr0", "host_intr1",
         "host_intr2", "host_intr3",
         "host_intr4",
         "host_intr6", "host_intr7";
     ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
    };

    pru0_0: pru@74000 {
     compatible = "ti,am4376-pru";
     reg = <0x74000 0x1000>,
           <0x62000 0x400>,
           <0x62400 0x100>;
     reg-names = "iram", "control", "debug";
     firmware-name = "am437x-pru0_0-fw";
    };

    pru0_1: pru@78000 {
     compatible = "ti,am4376-pru";
     reg = <0x78000 0x1000>,
           <0x64000 0x400>,
           <0x64400 0x100>;
     reg-names = "iram", "control", "debug";
     firmware-name = "am437x-pru0_1-fw";
    };
   };
  };

  target-module@50000000 {
   compatible = "ti,sysc-omap2", "ti,sysc";
   reg = <0x50000000 4>,
         <0x50000010 4>,
         <0x50000014 4>;
   reg-names = "rev", "sysc", "syss";
   ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_NO>,
     <SYSC_IDLE_SMART>;
   ti,syss-mask = <1>;
   clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
     <0x00000000 0x00000000 0x40000000>; /* data */

   gpmc: gpmc@50000000 {
    compatible = "ti,am3352-gpmc";
    dmas = <&edma 52 0>;
    dma-names = "rxtx";
    clocks = <&l3s_gclk>;
    clock-names = "fck";
    reg = <0x50000000 0x2000>;
    interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
    gpmc,num-cs = <7>;
    gpmc,num-waitpins = <2>;
    #address-cells = <2>;
    #size-cells = <1>;
    interrupt-controller;
    #interrupt-cells = <2>;
    gpio-controller;
    #gpio-cells = <2>;
    status = "disabled";
   };
  };

  target-module@47900000 {
   compatible = "ti,sysc-omap4", "ti,sysc";
   reg = <0x47900000 0x4>,
         <0x47900010 0x4>;
   reg-names = "rev", "sysc";
   ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_NO>,
     <SYSC_IDLE_SMART>,
     <SYSC_IDLE_SMART_WKUP>;
   clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0x0 0x47900000 0x1000>,
     <0x30000000 0x30000000 0x4000000>;

   qspi: spi@0 {
    compatible = "ti,am4372-qspi";
    reg = <0 0x100>,
          <0x30000000 0x4000000>;
    reg-names = "qspi_base", "qspi_mmap";
    clocks = <&dpll_per_m2_div4_ck>;
    clock-names = "fck";
    #address-cells = <1>;
    #size-cells = <0>;
    interrupts = <0 138 0x4>;
    num-cs = <4>;
   };
  };

  target-module@40300000 {
   compatible = "ti,sysc-omap4-simple", "ti,sysc";
   clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
   clock-names = "fck";
   ti,no-idle;
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0 0x40300000 0x40000>;

   ocmcram: sram@0 {
    compatible = "mmio-sram";
    reg = <0 0x40000>; /* 256k */
    ranges = <0 0 0x40000>;
    #address-cells = <1>;
    #size-cells = <1>;

    pm_sram_code: pm-code-sram@0 {
     compatible = "ti,sram";
     reg = <0x0 0x1000>;
     protect-exec;
    };

    pm_sram_data: pm-data-sram@1000 {
     compatible = "ti,sram";
     reg = <0x1000 0x1000>;
     pool;
    };
   };
  };

  target-module@56000000 {
   compatible = "ti,sysc-omap4", "ti,sysc";
   reg = <0x5600fe00 0x4>,
         <0x5600fe10 0x4>;
   reg-names = "rev", "sysc";
   ti,sysc-midle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_NO>,
     <SYSC_IDLE_SMART>;
   ti,sysc-sidle = <SYSC_IDLE_FORCE>,
     <SYSC_IDLE_NO>,
     <SYSC_IDLE_SMART>;
   clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
   clock-names = "fck";
   power-domains = <&prm_gfx>;
   resets = <&prm_gfx 0>;
   reset-names = "rstctrl";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0 0x56000000 0x1000000>;

   gpu@0 {
    compatible = "ti,omap3630-gpu", "img,powervr-sgx530";
    reg = <0x0 0x10000>; /* 64kB */
    interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
   };
  };
 };
};

#include "am437x-l4.dtsi"
#include "am43xx-clocks.dtsi"

&prcm {
 prm_mpu: prm@300 {
  compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  reg = <0x300 0x100>;
  #power-domain-cells = <0>;
 };

 prm_gfx: prm@400 {
  compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  reg = <0x400 0x100>;
  #power-domain-cells = <0>;
  #reset-cells = <1>;
 };

 prm_rtc: prm@500 {
  compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  reg = <0x500 0x100>;
  #power-domain-cells = <0>;
 };

 prm_tamper: prm@600 {
  compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  reg = <0x600 0x100>;
  #power-domain-cells = <0>;
 };

 prm_cefuse: prm@700 {
  compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  reg = <0x700 0x100>;
  #power-domain-cells = <0>;
 };

 prm_per: prm@800 {
  compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  reg = <0x800 0x100>;
  #reset-cells = <1>;
  #power-domain-cells = <0>;
 };

 prm_wkup: prm@2000 {
  compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  reg = <0x2000 0x100>;
  #reset-cells = <1>;
  #power-domain-cells = <0>;
 };

 prm_device: prm@4000 {
  compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  reg = <0x4000 0x100>;
  #reset-cells = <1>;
 };
};

/* Preferred always-on timer for clocksource */
&timer1_target {
 ti,no-reset-on-init;
 ti,no-idle;
 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
   <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
 clock-names = "fck", "ick";
 timer@0 {
  assigned-clocks = <&timer1_fck>;
  assigned-clock-parents = <&sys_clkin_ck>;
 };
};

/* Preferred timer for clockevent */
&timer2_target {
 ti,no-reset-on-init;
 ti,no-idle;
 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
   <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
 clock-names = "fck", "ick";
 timer@0 {
  assigned-clocks = <&timer2_fck>;
  assigned-clock-parents = <&sys_clkin_ck>;
 };
};