| Quellcodebibliothek Statistik Leitseite products/sources/formale Sprachen/C/Linux/arch/arm64/boot/dts/amlogic/ (Open Source Betriebssystem Version 6.17.9©) Datei vom 24.10.2025 mit Größe 45 kB |
|
Quelle meson-axg.dtsi Sprache: unbekannt |
|
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* * Copyright (c) 2017 Amlogic, Inc. All rights reserved. */ #include <dt-bindings/clock/axg-aoclkc.h> #include <dt-bindings/clock/axg-audio-clkc.h> #include <dt-bindings/clock/axg-clkc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/meson-axg-gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> #include <dt-bindings/reset/amlogic,meson-axg-reset.h> #include <dt-bindings/power/meson-axg-power.h> / { compatible = "amlogic,meson-axg"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; tdmif_a: audio-controller-0 { compatible = "amlogic,axg-tdm-iface"; #sound-dai-cells = <0>; sound-name-prefix = "TDM_A"; clocks = <&clkc_audio AUD_CLKID_MST_A_SCLK>, <&clkc_audio AUD_CLKID_MST_A_LRCLK>, <&clkc_audio AUD_CLKID_MST_A_MCLK>; clock-names = "sclk", "lrclk", "mclk"; status = "disabled"; }; tdmif_b: audio-controller-1 { compatible = "amlogic,axg-tdm-iface"; #sound-dai-cells = <0>; sound-name-prefix = "TDM_B"; clocks = <&clkc_audio AUD_CLKID_MST_B_SCLK>, <&clkc_audio AUD_CLKID_MST_B_LRCLK>, <&clkc_audio AUD_CLKID_MST_B_MCLK>; clock-names = "sclk", "lrclk", "mclk"; status = "disabled"; }; tdmif_c: audio-controller-2 { compatible = "amlogic,axg-tdm-iface"; #sound-dai-cells = <0>; sound-name-prefix = "TDM_C"; clocks = <&clkc_audio AUD_CLKID_MST_C_SCLK>, <&clkc_audio AUD_CLKID_MST_C_LRCLK>, <&clkc_audio AUD_CLKID_MST_C_MCLK>; clock-names = "sclk", "lrclk", "mclk"; status = "disabled"; }; arm-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; cpus { #address-cells = <0x2>; #size-cells = <0x0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>; #cooling-cells = <2>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>; #cooling-cells = <2>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>; #cooling-cells = <2>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>; #cooling-cells = <2>; }; l2: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-unified; }; }; sm: secure-monitor { compatible = "amlogic,meson-gxbb-sm"; }; efuse: efuse { compatible = "amlogic,meson-gxbb-efuse"; clocks = <&clkc CLKID_EFUSE>; #address-cells = <1>; #size-cells = <1>; read-only; secure-monitor = <&sm>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; /* 16 MiB reserved for Hardware ROM Firmware */ hwrom_reserved: hwrom@0 { reg = <0x0 0x0 0x0 0x1000000>; no-map; }; /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ secmon_reserved: secmon@5000000 { reg = <0x0 0x05000000 0x0 0x300000>; no-map; }; }; scpi { compatible = "arm,scpi-pre-1.0"; mboxes = <&mailbox 1 &mailbox 2>; shmem = <&cpu_scp_lpri &cpu_scp_hpri>; scpi_clocks: clocks { compatible = "arm,scpi-clocks"; scpi_dvfs: clocks-0 { compatible = "arm,scpi-dvfs-clocks"; #clock-cells = <1>; clock-indices = <0>; clock-output-names = "vcpu"; }; }; scpi_sensors: sensors { compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; #thermal-sensor-cells = <1>; }; }; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; pcieA: pcie@f9800000 { compatible = "amlogic,axg-pcie", "snps,dw-pcie"; reg = <0x0 0xf9800000 0x0 0x400000>, <0x0 0xff646000 0x0 0x2000>, <0x0 0xf9f00000 0x0 0x100000>; reg-names = "elbi", "cfg", "config"; interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; bus-range = <0x0 0xff>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>; clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>; clock-names = "general", "pclk", "port"; resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; reset-names = "port", "apb"; num-lanes = <1>; phys = <&pcie_phy>; phy-names = "pcie"; status = "disabled"; }; pcieB: pcie@fa000000 { compatible = "amlogic,axg-pcie", "snps,dw-pcie"; reg = <0x0 0xfa000000 0x0 0x400000>, <0x0 0xff648000 0x0 0x2000>, <0x0 0xfa400000 0x0 0x100000>; reg-names = "elbi", "cfg", "config"; interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; bus-range = <0x0 0xff>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>; clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>; clock-names = "general", "pclk", "port"; resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>; reset-names = "port", "apb"; num-lanes = <1>; phys = <&pcie_phy>; phy-names = "pcie"; status = "disabled"; }; usb: usb@ffe09080 { compatible = "amlogic,meson-axg-usb-ctrl"; reg = <0x0 0xffe09080 0x0 0x20>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; clock-names = "usb_ctrl", "ddr"; resets = <&reset RESET_USB_OTG>; dr_mode = "otg"; phys = <&usb2_phy1>; phy-names = "usb2-phy1"; dwc2: usb@ff400000 { compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; reg = <0x0 0xff400000 0x0 0x40000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clkc CLKID_USB1>; clock-names = "otg"; phys = <&usb2_phy1>; dr_mode = "peripheral"; g-rx-fifo-size = <192>; g-np-tx-fifo-size = <128>; g-tx-fifo-size = <128 128 16 16 16>; }; dwc3: usb@ff500000 { compatible = "snps,dwc3"; reg = <0x0 0xff500000 0x0 0x100000>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; }; }; ethmac: ethernet@ff3f0000 { compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.70a", "snps,dwmac"; reg = <0x0 0xff3f0000 0x0 0x10000>, <0x0 0xff634540 0x0 0x8>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; clocks = <&clkc CLKID_ETH>, <&clkc CLKID_FCLK_DIV2>, <&clkc CLKID_MPLL2>, <&clkc CLKID_FCLK_DIV2>; clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; rx-fifo-depth = <4096>; tx-fifo-depth = <2048>; power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>; status = "disabled"; }; pcie_phy: phy@ff644000 { compatible = "amlogic,axg-pcie-phy"; reg = <0x0 0xff644000 0x0 0x1c>; resets = <&reset RESET_PCIE_PHY>; phys = <&mipi_pcie_analog_dphy>; phy-names = "analog"; #phy-cells = <0>; }; pdm: audio-controller@ff632000 { compatible = "amlogic,axg-pdm"; reg = <0x0 0xff632000 0x0 0x34>; #sound-dai-cells = <0>; sound-name-prefix = "PDM"; clocks = <&clkc_audio AUD_CLKID_PDM>, <&clkc_audio AUD_CLKID_PDM_DCLK>, <&clkc_audio AUD_CLKID_PDM_SYSCLK>; clock-names = "pclk", "dclk", "sysclk"; status = "disabled"; }; periphs: bus@ff634000 { compatible = "simple-bus"; reg = <0x0 0xff634000 0x0 0x2000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; hwrng: rng@18 { compatible = "amlogic,meson-rng"; reg = <0x0 0x18 0x0 0x4>; clocks = <&clkc CLKID_RNG0>; clock-names = "core"; }; pinctrl_periphs: pinctrl@480 { compatible = "amlogic,meson-axg-periphs-pinctrl"; #address-cells = <2>; #size-cells = <2>; ranges; gpio: bank@480 { reg = <0x0 0x00480 0x0 0x40>, <0x0 0x004e8 0x0 0x14>, <0x0 0x00520 0x0 0x14>, <0x0 0x00430 0x0 0x3c>; reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl_periphs 0 0 86>; }; i2c0_pins: i2c0 { mux { groups = "i2c0_sck", "i2c0_sda"; function = "i2c0"; bias-disable; }; }; i2c1_x_pins: i2c1_x { mux { groups = "i2c1_sck_x", "i2c1_sda_x"; function = "i2c1"; bias-disable; }; }; i2c1_z_pins: i2c1_z { mux { groups = "i2c1_sck_z", "i2c1_sda_z"; function = "i2c1"; bias-disable; }; }; i2c2_a_pins: i2c2_a { mux { groups = "i2c2_sck_a", "i2c2_sda_a"; function = "i2c2"; bias-disable; }; }; i2c2_x_pins: i2c2_x { mux { groups = "i2c2_sck_x", "i2c2_sda_x"; function = "i2c2"; bias-disable; }; }; i2c3_a6_pins: i2c3_a6 { mux { groups = "i2c3_sda_a6", "i2c3_sck_a7"; function = "i2c3"; bias-disable; }; }; i2c3_a12_pins: i2c3_a12 { mux { groups = "i2c3_sda_a12", "i2c3_sck_a13"; function = "i2c3"; bias-disable; }; }; i2c3_a19_pins: i2c3_a19 { mux { groups = "i2c3_sda_a19", "i2c3_sck_a20"; function = "i2c3"; bias-disable; }; }; emmc_pins: emmc { mux-0 { groups = "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", "emmc_cmd"; function = "emmc"; bias-pull-up; }; mux-1 { groups = "emmc_clk"; function = "emmc"; bias-disable; }; }; nand_all_pins: nand-all-pins { mux { groups = "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", "nand_ce0", "nand_ale", "nand_cle", "nand_wen_clk", "nand_ren_wr"; function = "nand"; input-enable; bias-pull-up; }; }; emmc_ds_pins: emmc_ds { mux { groups = "emmc_ds"; function = "emmc"; bias-pull-down; }; }; emmc_clk_gate_pins: emmc_clk_gate { mux { groups = "BOOT_8"; function = "gpio_periphs"; bias-pull-down; }; }; eth_rgmii_x_pins: eth-x-rgmii { mux { groups = "eth_mdio_x", "eth_mdc_x", "eth_rgmii_rx_clk_x", "eth_rx_dv_x", "eth_rxd0_x", "eth_rxd1_x", "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", "eth_txen_x", "eth_txd0_x", "eth_txd1_x", "eth_txd2_rgmii", "eth_txd3_rgmii"; function = "eth"; bias-disable; }; }; eth_rgmii_y_pins: eth-y-rgmii { mux { groups = "eth_mdio_y", "eth_mdc_y", "eth_rgmii_rx_clk_y", "eth_rx_dv_y", "eth_rxd0_y", "eth_rxd1_y", "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", "eth_txen_y", "eth_txd0_y", "eth_txd1_y", "eth_txd2_rgmii", "eth_txd3_rgmii"; function = "eth"; bias-disable; }; }; eth_rmii_x_pins: eth-x-rmii { mux { groups = "eth_mdio_x", "eth_mdc_x", "eth_rgmii_rx_clk_x", "eth_rx_dv_x", "eth_rxd0_x", "eth_rxd1_x", "eth_txen_x", "eth_txd0_x", "eth_txd1_x"; function = "eth"; bias-disable; }; }; eth_rmii_y_pins: eth-y-rmii { mux { groups = "eth_mdio_y", "eth_mdc_y", "eth_rgmii_rx_clk_y", "eth_rx_dv_y", "eth_rxd0_y", "eth_rxd1_y", "eth_txen_y", "eth_txd0_y", "eth_txd1_y"; function = "eth"; bias-disable; }; }; mclk_b_pins: mclk_b { mux { groups = "mclk_b"; function = "mclk_b"; bias-disable; }; }; mclk_c_pins: mclk_c { mux { groups = "mclk_c"; function = "mclk_c"; bias-disable; }; }; pdm_dclk_a14_pins: pdm_dclk_a14 { mux { groups = "pdm_dclk_a14"; function = "pdm"; bias-disable; }; }; pdm_dclk_a19_pins: pdm_dclk_a19 { mux { groups = "pdm_dclk_a19"; function = "pdm"; bias-disable; }; }; pdm_din0_pins: pdm_din0 { mux { groups = "pdm_din0"; function = "pdm"; bias-disable; }; }; pdm_din1_pins: pdm_din1 { mux { groups = "pdm_din1"; function = "pdm"; bias-disable; }; }; pdm_din2_pins: pdm_din2 { mux { groups = "pdm_din2"; function = "pdm"; bias-disable; }; }; pdm_din3_pins: pdm_din3 { mux { groups = "pdm_din3"; function = "pdm"; bias-disable; }; }; pwm_a_a_pins: pwm_a_a { mux { groups = "pwm_a_a"; function = "pwm_a"; bias-disable; }; }; pwm_a_x18_pins: pwm_a_x18 { mux { groups = "pwm_a_x18"; function = "pwm_a"; bias-disable; }; }; pwm_a_x20_pins: pwm_a_x20 { mux { groups = "pwm_a_x20"; function = "pwm_a"; bias-disable; }; }; pwm_a_z_pins: pwm_a_z { mux { groups = "pwm_a_z"; function = "pwm_a"; bias-disable; }; }; pwm_b_a_pins: pwm_b_a { mux { groups = "pwm_b_a"; function = "pwm_b"; bias-disable; }; }; pwm_b_x_pins: pwm_b_x { mux { groups = "pwm_b_x"; function = "pwm_b"; bias-disable; }; }; pwm_b_z_pins: pwm_b_z { mux { groups = "pwm_b_z"; function = "pwm_b"; bias-disable; }; }; pwm_c_a_pins: pwm_c_a { mux { groups = "pwm_c_a"; function = "pwm_c"; bias-disable; }; }; pwm_c_x10_pins: pwm_c_x10 { mux { groups = "pwm_c_x10"; function = "pwm_c"; bias-disable; }; }; pwm_c_x17_pins: pwm_c_x17 { mux { groups = "pwm_c_x17"; function = "pwm_c"; bias-disable; }; }; pwm_d_x11_pins: pwm_d_x11 { mux { groups = "pwm_d_x11"; function = "pwm_d"; bias-disable; }; }; pwm_d_x16_pins: pwm_d_x16 { mux { groups = "pwm_d_x16"; function = "pwm_d"; bias-disable; }; }; sdio_pins: sdio { mux-0 { groups = "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_cmd"; function = "sdio"; bias-pull-up; }; mux-1 { groups = "sdio_clk"; function = "sdio"; bias-disable; }; }; sdio_clk_gate_pins: sdio_clk_gate { mux { groups = "GPIOX_4"; function = "gpio_periphs"; bias-pull-down; }; }; spdif_in_z_pins: spdif_in_z { mux { groups = "spdif_in_z"; function = "spdif_in"; bias-disable; }; }; spdif_in_a1_pins: spdif_in_a1 { mux { groups = "spdif_in_a1"; function = "spdif_in"; bias-disable; }; }; spdif_in_a7_pins: spdif_in_a7 { mux { groups = "spdif_in_a7"; function = "spdif_in"; bias-disable; }; }; spdif_in_a19_pins: spdif_in_a19 { mux { groups = "spdif_in_a19"; function = "spdif_in"; bias-disable; }; }; spdif_in_a20_pins: spdif_in_a20 { mux { groups = "spdif_in_a20"; function = "spdif_in"; bias-disable; }; }; spdif_out_a1_pins: spdif_out_a1 { mux { groups = "spdif_out_a1"; function = "spdif_out"; bias-disable; }; }; spdif_out_a11_pins: spdif_out_a11 { mux { groups = "spdif_out_a11"; function = "spdif_out"; bias-disable; }; }; spdif_out_a19_pins: spdif_out_a19 { mux { groups = "spdif_out_a19"; function = "spdif_out"; bias-disable; }; }; spdif_out_a20_pins: spdif_out_a20 { mux { groups = "spdif_out_a20"; function = "spdif_out"; bias-disable; }; }; spdif_out_z_pins: spdif_out_z { mux { groups = "spdif_out_z"; function = "spdif_out"; bias-disable; }; }; spi0_pins: spi0 { mux { groups = "spi0_miso", "spi0_mosi", "spi0_clk"; function = "spi0"; bias-disable; }; }; spi0_ss0_pins: spi0_ss0 { mux { groups = "spi0_ss0"; function = "spi0"; bias-disable; }; }; spi0_ss1_pins: spi0_ss1 { mux { groups = "spi0_ss1"; function = "spi0"; bias-disable; }; }; spi0_ss2_pins: spi0_ss2 { mux { groups = "spi0_ss2"; function = "spi0"; bias-disable; }; }; spi1_a_pins: spi1_a { mux { groups = "spi1_miso_a", "spi1_mosi_a", "spi1_clk_a"; function = "spi1"; bias-disable; }; }; spi1_ss0_a_pins: spi1_ss0_a { mux { groups = "spi1_ss0_a"; function = "spi1"; bias-disable; }; }; spi1_ss1_pins: spi1_ss1 { mux { groups = "spi1_ss1"; function = "spi1"; bias-disable; }; }; spi1_x_pins: spi1_x { mux { groups = "spi1_miso_x", "spi1_mosi_x", "spi1_clk_x"; function = "spi1"; bias-disable; }; }; spi1_ss0_x_pins: spi1_ss0_x { mux { groups = "spi1_ss0_x"; function = "spi1"; bias-disable; }; }; tdma_din0_pins: tdma_din0 { mux { groups = "tdma_din0"; function = "tdma"; bias-disable; }; }; tdma_dout0_x14_pins: tdma_dout0_x14 { mux { groups = "tdma_dout0_x14"; function = "tdma"; bias-disable; }; }; tdma_dout0_x15_pins: tdma_dout0_x15 { mux { groups = "tdma_dout0_x15"; function = "tdma"; bias-disable; }; }; tdma_dout1_pins: tdma_dout1 { mux { groups = "tdma_dout1"; function = "tdma"; bias-disable; }; }; tdma_din1_pins: tdma_din1 { mux { groups = "tdma_din1"; function = "tdma"; bias-disable; }; }; tdma_fs_pins: tdma_fs { mux { groups = "tdma_fs"; function = "tdma"; bias-disable; }; }; tdma_fs_slv_pins: tdma_fs_slv { mux { groups = "tdma_fs_slv"; function = "tdma"; bias-disable; }; }; tdma_sclk_pins: tdma_sclk { mux { groups = "tdma_sclk"; function = "tdma"; bias-disable; }; }; tdma_sclk_slv_pins: tdma_sclk_slv { mux { groups = "tdma_sclk_slv"; function = "tdma"; bias-disable; }; }; tdmb_din0_pins: tdmb_din0 { mux { groups = "tdmb_din0"; function = "tdmb"; bias-disable; }; }; tdmb_din1_pins: tdmb_din1 { mux { groups = "tdmb_din1"; function = "tdmb"; bias-disable; }; }; tdmb_din2_pins: tdmb_din2 { mux { groups = "tdmb_din2"; function = "tdmb"; bias-disable; }; }; tdmb_din3_pins: tdmb_din3 { mux { groups = "tdmb_din3"; function = "tdmb"; bias-disable; }; }; tdmb_dout0_pins: tdmb_dout0 { mux { groups = "tdmb_dout0"; function = "tdmb"; bias-disable; }; }; tdmb_dout1_pins: tdmb_dout1 { mux { groups = "tdmb_dout1"; function = "tdmb"; bias-disable; }; }; tdmb_dout2_pins: tdmb_dout2 { mux { groups = "tdmb_dout2"; function = "tdmb"; bias-disable; }; }; tdmb_dout3_pins: tdmb_dout3 { mux { groups = "tdmb_dout3"; function = "tdmb"; bias-disable; }; }; tdmb_fs_pins: tdmb_fs { mux { groups = "tdmb_fs"; function = "tdmb"; bias-disable; }; }; tdmb_fs_slv_pins: tdmb_fs_slv { mux { groups = "tdmb_fs_slv"; function = "tdmb"; bias-disable; }; }; tdmb_sclk_pins: tdmb_sclk { mux { groups = "tdmb_sclk"; function = "tdmb"; bias-disable; }; }; tdmb_sclk_slv_pins: tdmb_sclk_slv { mux { groups = "tdmb_sclk_slv"; function = "tdmb"; bias-disable; }; }; tdmc_fs_pins: tdmc_fs { mux { groups = "tdmc_fs"; function = "tdmc"; bias-disable; }; }; tdmc_fs_slv_pins: tdmc_fs_slv { mux { groups = "tdmc_fs_slv"; function = "tdmc"; bias-disable; }; }; tdmc_sclk_pins: tdmc_sclk { mux { groups = "tdmc_sclk"; function = "tdmc"; bias-disable; }; }; tdmc_sclk_slv_pins: tdmc_sclk_slv { mux { groups = "tdmc_sclk_slv"; function = "tdmc"; bias-disable; }; }; tdmc_din0_pins: tdmc_din0 { mux { groups = "tdmc_din0"; function = "tdmc"; bias-disable; }; }; tdmc_din1_pins: tdmc_din1 { mux { groups = "tdmc_din1"; function = "tdmc"; bias-disable; }; }; tdmc_din2_pins: tdmc_din2 { mux { groups = "tdmc_din2"; function = "tdmc"; bias-disable; }; }; tdmc_din3_pins: tdmc_din3 { mux { groups = "tdmc_din3"; function = "tdmc"; bias-disable; }; }; tdmc_dout0_pins: tdmc_dout0 { mux { groups = "tdmc_dout0"; function = "tdmc"; bias-disable; }; }; tdmc_dout1_pins: tdmc_dout1 { mux { groups = "tdmc_dout1"; function = "tdmc"; bias-disable; }; }; tdmc_dout2_pins: tdmc_dout2 { mux { groups = "tdmc_dout2"; function = "tdmc"; bias-disable; }; }; tdmc_dout3_pins: tdmc_dout3 { mux { groups = "tdmc_dout3"; function = "tdmc"; bias-disable; }; }; uart_a_pins: uart_a { mux { groups = "uart_tx_a", "uart_rx_a"; function = "uart_a"; bias-pull-up; }; }; uart_a_cts_rts_pins: uart_a_cts_rts { mux { groups = "uart_cts_a", "uart_rts_a"; function = "uart_a"; bias-disable; }; }; uart_b_x_pins: uart_b_x { mux { groups = "uart_tx_b_x", "uart_rx_b_x"; function = "uart_b"; bias-pull-up; }; }; uart_b_x_cts_rts_pins: uart_b_x_cts_rts { mux { groups = "uart_cts_b_x", "uart_rts_b_x"; function = "uart_b"; bias-disable; }; }; uart_b_z_pins: uart_b_z { mux { groups = "uart_tx_b_z", "uart_rx_b_z"; function = "uart_b"; bias-pull-up; }; }; uart_b_z_cts_rts_pins: uart_b_z_cts_rts { mux { groups = "uart_cts_b_z", "uart_rts_b_z"; function = "uart_b"; bias-disable; }; }; uart_ao_b_z_pins: uart_ao_b_z { mux { groups = "uart_ao_tx_b_z", "uart_ao_rx_b_z"; function = "uart_ao_b_z"; bias-pull-up; }; }; uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { mux { groups = "uart_ao_cts_b_z", "uart_ao_rts_b_z"; function = "uart_ao_b_z"; bias-disable; }; }; }; }; hiubus: bus@ff63c000 { compatible = "simple-bus"; reg = <0x0 0xff63c000 0x0 0x1c00>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; sysctrl: system-controller@0 { compatible = "amlogic,meson-axg-hhi-sysctrl", "simple-mfd", "syscon"; reg = <0 0 0 0x400>; clkc: clock-controller { compatible = "amlogic,axg-clkc"; #clock-cells = <1>; clocks = <&xtal>; clock-names = "xtal"; }; pwrc: power-controller { compatible = "amlogic,meson-axg-pwrc"; #power-domain-cells = <1>; amlogic,ao-sysctrl = <&sysctrl_AO>; resets = <&reset RESET_VIU>, <&reset RESET_VENC>, <&reset RESET_VCBUS>, <&reset RESET_VENCL>, <&reset RESET_VID_LOCK>; reset-names = "viu", "venc", "vcbus", "vencl", "vid_lock"; clocks = <&clkc CLKID_VPU>, <&clkc CLKID_VAPB>; clock-names = "vpu", "vapb"; /* * VPU clocking is provided by two identical clock paths * VPU_0 and VPU_1 muxed to a single clock by a glitch * free mux to safely change frequency while running. * Same for VAPB but with a final gate after the glitch free mux. */ assigned-clocks = <&clkc CLKID_VPU_0_SEL>, <&clkc CLKID_VPU_0>, <&clkc CLKID_VPU>, /* Glitch free mux */ <&clkc CLKID_VAPB_0_SEL>, <&clkc CLKID_VAPB_0>, <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>, <0>, /* Do Nothing */ <&clkc CLKID_VPU_0>, <&clkc CLKID_FCLK_DIV4>, <0>, /* Do Nothing */ <&clkc CLKID_VAPB_0>; assigned-clock-rates = <0>, /* Do Nothing */ <250000000>, <0>, /* Do Nothing */ <0>, /* Do Nothing */ <250000000>, <0>; /* Do Nothing */ }; mipi_pcie_analog_dphy: phy { compatible = "amlogic,axg-mipi-pcie-analog-phy"; #phy-cells = <0>; status = "disabled"; }; }; }; mailbox: mailbox@ff63c404 { compatible = "amlogic,meson-gxbb-mhu"; reg = <0 0xff63c404 0 0x4c>; interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; #mbox-cells = <1>; }; mipi_dphy: phy@ff640000 { compatible = "amlogic,axg-mipi-dphy"; reg = <0x0 0xff640000 0x0 0x100>; clocks = <&clkc CLKID_MIPI_DSI_PHY>; clock-names = "pclk"; resets = <&reset RESET_MIPI_PHY>; reset-names = "phy"; phys = <&mipi_pcie_analog_dphy>; phy-names = "analog"; #phy-cells = <0>; status = "disabled"; }; audio: bus@ff642000 { compatible = "simple-bus"; reg = <0x0 0xff642000 0x0 0x2000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; clkc_audio: clock-controller@0 { compatible = "amlogic,axg-audio-clkc"; reg = <0x0 0x0 0x0 0xb4>; #clock-cells = <1>; clocks = <&clkc CLKID_AUDIO>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL3>, <&clkc CLKID_HIFI_PLL>, <&clkc CLKID_FCLK_DIV3>, <&clkc CLKID_FCLK_DIV4>, <&clkc CLKID_GP0_PLL>; clock-names = "pclk", "mst_in0", "mst_in1", "mst_in2", "mst_in3", "mst_in4", "mst_in5", "mst_in6", "mst_in7"; resets = <&reset RESET_AUDIO>; }; toddr_a: audio-controller@100 { compatible = "amlogic,axg-toddr"; reg = <0x0 0x100 0x0 0x2c>; #sound-dai-cells = <0>; sound-name-prefix = "TODDR_A"; interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc_audio AUD_CLKID_TODDR_A>; resets = <&arb AXG_ARB_TODDR_A>; amlogic,fifo-depth = <512>; status = "disabled"; }; toddr_b: audio-controller@140 { compatible = "amlogic,axg-toddr"; reg = <0x0 0x140 0x0 0x2c>; #sound-dai-cells = <0>; sound-name-prefix = "TODDR_B"; interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc_audio AUD_CLKID_TODDR_B>; resets = <&arb AXG_ARB_TODDR_B>; amlogic,fifo-depth = <256>; status = "disabled"; }; toddr_c: audio-controller@180 { compatible = "amlogic,axg-toddr"; reg = <0x0 0x180 0x0 0x2c>; #sound-dai-cells = <0>; sound-name-prefix = "TODDR_C"; interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc_audio AUD_CLKID_TODDR_C>; resets = <&arb AXG_ARB_TODDR_C>; amlogic,fifo-depth = <256>; status = "disabled"; }; frddr_a: audio-controller@1c0 { compatible = "amlogic,axg-frddr"; reg = <0x0 0x1c0 0x0 0x2c>; #sound-dai-cells = <0>; sound-name-prefix = "FRDDR_A"; interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; resets = <&arb AXG_ARB_FRDDR_A>; amlogic,fifo-depth = <512>; status = "disabled"; }; frddr_b: audio-controller@200 { compatible = "amlogic,axg-frddr"; reg = <0x0 0x200 0x0 0x2c>; #sound-dai-cells = <0>; sound-name-prefix = "FRDDR_B"; interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; resets = <&arb AXG_ARB_FRDDR_B>; amlogic,fifo-depth = <256>; status = "disabled"; }; frddr_c: audio-controller@240 { compatible = "amlogic,axg-frddr"; reg = <0x0 0x240 0x0 0x2c>; #sound-dai-cells = <0>; sound-name-prefix = "FRDDR_C"; interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; resets = <&arb AXG_ARB_FRDDR_C>; amlogic,fifo-depth = <256>; status = "disabled"; }; arb: reset-controller@280 { compatible = "amlogic,meson-axg-audio-arb"; reg = <0x0 0x280 0x0 0x4>; #reset-cells = <1>; clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; }; tdmin_a: audio-controller@300 { compatible = "amlogic,axg-tdmin"; reg = <0x0 0x300 0x0 0x40>; sound-name-prefix = "TDMIN_A"; clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; clock-names = "pclk", "sclk", "sclk_sel", "lrclk", "lrclk_sel"; status = "disabled"; }; tdmin_b: audio-controller@340 { compatible = "amlogic,axg-tdmin"; reg = <0x0 0x340 0x0 0x40>; sound-name-prefix = "TDMIN_B"; clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; clock-names = "pclk", "sclk", "sclk_sel", "lrclk", "lrclk_sel"; status = "disabled"; }; tdmin_c: audio-controller@380 { compatible = "amlogic,axg-tdmin"; reg = <0x0 0x380 0x0 0x40>; sound-name-prefix = "TDMIN_C"; clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; clock-names = "pclk", "sclk", "sclk_sel", "lrclk", "lrclk_sel"; status = "disabled"; }; tdmin_lb: audio-controller@3c0 { compatible = "amlogic,axg-tdmin"; reg = <0x0 0x3c0 0x0 0x40>; sound-name-prefix = "TDMIN_LB"; clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; clock-names = "pclk", "sclk", "sclk_sel", "lrclk", "lrclk_sel"; status = "disabled"; }; spdifin: audio-controller@400 { compatible = "amlogic,axg-spdifin"; reg = <0x0 0x400 0x0 0x30>; #sound-dai-cells = <0>; sound-name-prefix = "SPDIFIN"; interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; clock-names = "pclk", "refclk"; status = "disabled"; }; spdifout: audio-controller@480 { compatible = "amlogic,axg-spdifout"; reg = <0x0 0x480 0x0 0x50>; #sound-dai-cells = <0>; sound-name-prefix = "SPDIFOUT"; clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; clock-names = "pclk", "mclk"; status = "disabled"; }; tdmout_a: audio-controller@500 { compatible = "amlogic,axg-tdmout"; reg = <0x0 0x500 0x0 0x40>; sound-name-prefix = "TDMOUT_A"; clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; clock-names = "pclk", "sclk", "sclk_sel", "lrclk", "lrclk_sel"; status = "disabled"; }; tdmout_b: audio-controller@540 { compatible = "amlogic,axg-tdmout"; reg = <0x0 0x540 0x0 0x40>; sound-name-prefix = "TDMOUT_B"; clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; clock-names = "pclk", "sclk", "sclk_sel", "lrclk", "lrclk_sel"; status = "disabled"; }; tdmout_c: audio-controller@580 { compatible = "amlogic,axg-tdmout"; reg = <0x0 0x580 0x0 0x40>; sound-name-prefix = "TDMOUT_C"; clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; clock-names = "pclk", "sclk", "sclk_sel", "lrclk", "lrclk_sel"; status = "disabled"; }; }; aobus: bus@ff800000 { compatible = "simple-bus"; reg = <0x0 0xff800000 0x0 0x100000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; sysctrl_AO: sys-ctrl@0 { compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; reg = <0x0 0x0 0x0 0x100>; clkc_AO: clock-controller { compatible = "amlogic,meson-axg-aoclkc"; #clock-cells = <1>; #reset-cells = <1>; clocks = <&xtal>, <&clkc CLKID_CLK81>; clock-names = "xtal", "mpeg-clk"; }; }; pinctrl_aobus: pinctrl@14 { compatible = "amlogic,meson-axg-aobus-pinctrl"; #address-cells = <2>; #size-cells = <2>; ranges; gpio_ao: bank@14 { reg = <0x0 0x00014 0x0 0x8>, <0x0 0x0002c 0x0 0x4>, <0x0 0x00024 0x0 0x8>; reg-names = "mux", "pull", "gpio"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl_aobus 0 0 15>; }; i2c_ao_sck_4_pins: i2c_ao_sck_4 { mux { groups = "i2c_ao_sck_4"; function = "i2c_ao"; bias-disable; }; }; i2c_ao_sck_8_pins: i2c_ao_sck_8 { mux { groups = "i2c_ao_sck_8"; function = "i2c_ao"; bias-disable; }; }; i2c_ao_sck_10_pins: i2c_ao_sck_10 { mux { groups = "i2c_ao_sck_10"; function = "i2c_ao"; bias-disable; }; }; i2c_ao_sda_5_pins: i2c_ao_sda_5 { mux { groups = "i2c_ao_sda_5"; function = "i2c_ao"; bias-disable; }; }; i2c_ao_sda_9_pins: i2c_ao_sda_9 { mux { groups = "i2c_ao_sda_9"; function = "i2c_ao"; bias-disable; }; }; i2c_ao_sda_11_pins: i2c_ao_sda_11 { mux { groups = "i2c_ao_sda_11"; function = "i2c_ao"; bias-disable; }; }; remote_input_ao_pins: remote_input_ao { mux { groups = "remote_input_ao"; function = "remote_input_ao"; bias-disable; }; }; uart_ao_a_pins: uart_ao_a { mux { groups = "uart_ao_tx_a", "uart_ao_rx_a"; function = "uart_ao_a"; bias-pull-up; }; }; uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { mux { groups = "uart_ao_cts_a", "uart_ao_rts_a"; function = "uart_ao_a"; bias-disable; }; }; uart_ao_b_pins: uart_ao_b { mux { groups = "uart_ao_tx_b", "uart_ao_rx_b"; function = "uart_ao_b"; bias-pull-up; }; }; uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { mux { groups = "uart_ao_cts_b", "uart_ao_rts_b"; function = "uart_ao_b"; bias-disable; }; }; }; sec_AO: ao-secure@140 { compatible = "amlogic,meson-gx-ao-secure", "syscon"; reg = <0x0 0x140 0x0 0x140>; amlogic,has-chip-id; }; pwm_AO_cd: pwm@2000 { compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x02000 0x0 0x20>; clocks = <&xtal>, <&clkc_AO CLKID_AO_CLK81>, <&clkc CLKID_FCLK_DIV4>, <&clkc CLKID_FCLK_DIV5>; #pwm-cells = <3>; status = "disabled"; }; uart_AO: serial@3000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x3000 0x0 0x18>; interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; uart_AO_B: serial@4000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x4000 0x0 0x18>; interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; i2c_AO: i2c@5000 { compatible = "amlogic,meson-axg-i2c"; reg = <0x0 0x05000 0x0 0x20>; interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc CLKID_AO_I2C>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; pwm_AO_ab: pwm@7000 { compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x07000 0x0 0x20>; clocks = <&xtal>, <&clkc_AO CLKID_AO_CLK81>, <&clkc CLKID_FCLK_DIV4>, <&clkc CLKID_FCLK_DIV5>; #pwm-cells = <3>; status = "disabled"; }; ir: ir@8000 { compatible = "amlogic,meson-gxbb-ir"; reg = <0x0 0x8000 0x0 0x20>; interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; saradc: adc@9000 { compatible = "amlogic,meson-axg-saradc", "amlogic,meson-saradc"; reg = <0x0 0x9000 0x0 0x38>; #io-channel-cells = <1>; interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; clocks = <&xtal>, <&clkc_AO CLKID_AO_SAR_ADC>, <&clkc_AO CLKID_AO_SAR_ADC_CLK>, <&clkc_AO CLKID_AO_SAR_ADC_SEL>; clock-names = "clkin", "core", "adc_clk", "adc_sel"; status = "disabled"; }; }; ge2d: ge2d@ff940000 { compatible = "amlogic,axg-ge2d"; reg = <0x0 0xff940000 0x0 0x10000>; interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc CLKID_VAPB>; resets = <&reset RESET_GE2D>; }; gic: interrupt-controller@ffc01000 { compatible = "arm,gic-400"; reg = <0x0 0xffc01000 0 0x1000>, <0x0 0xffc02000 0 0x2000>, <0x0 0xffc04000 0 0x2000>, <0x0 0xffc06000 0 0x2000>; interrupt-controller; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; #interrupt-cells = <3>; #address-cells = <0>; }; cbus: bus@ffd00000 { compatible = "simple-bus"; reg = <0x0 0xffd00000 0x0 0x25000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; reset: reset-controller@1004 { compatible = "amlogic,meson-axg-reset"; reg = <0x0 0x01004 0x0 0x9c>; #reset-cells = <1>; }; gpio_intc: interrupt-controller@f080 { compatible = "amlogic,meson-axg-gpio-intc", "amlogic,meson-gpio-intc"; reg = <0x0 0xf080 0x0 0x10>; interrupt-controller; #interrupt-cells = <2>; amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; }; watchdog@f0d0 { compatible = "amlogic,meson-gxbb-wdt"; reg = <0x0 0xf0d0 0x0 0x10>; clocks = <&xtal>; }; pwm_ab: pwm@1b000 { compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x1b000 0x0 0x20>; clocks = <&xtal>, <&clkc CLKID_FCLK_DIV5>, <&clkc CLKID_FCLK_DIV4>, <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; pwm_cd: pwm@1a000 { compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x1a000 0x0 0x20>; clocks = <&xtal>, <&clkc CLKID_FCLK_DIV5>, <&clkc CLKID_FCLK_DIV4>, <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; spicc0: spi@13000 { compatible = "amlogic,meson-axg-spicc"; reg = <0x0 0x13000 0x0 0x3c>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clkc CLKID_SPICC0>; clock-names = "core"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spicc1: spi@15000 { compatible = "amlogic,meson-axg-spicc"; reg = <0x0 0x15000 0x0 0x3c>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clkc CLKID_SPICC1>; clock-names = "core"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; clk_msr: clock-measure@18000 { compatible = "amlogic,meson-axg-clk-measure"; reg = <0x0 0x18000 0x0 0x10>; }; i2c3: i2c@1c000 { compatible = "amlogic,meson-axg-i2c"; reg = <0x0 0x1c000 0x0 0x20>; interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc CLKID_I2C>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@1d000 { compatible = "amlogic,meson-axg-i2c"; reg = <0x0 0x1d000 0x0 0x20>; interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc CLKID_I2C>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@1e000 { compatible = "amlogic,meson-axg-i2c"; reg = <0x0 0x1e000 0x0 0x20>; interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc CLKID_I2C>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c0: i2c@1f000 { compatible = "amlogic,meson-axg-i2c"; reg = <0x0 0x1f000 0x0 0x20>; interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc CLKID_I2C>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; uart_B: serial@23000 { compatible = "amlogic,meson-gx-uart"; reg = <0x0 0x23000 0x0 0x18>; interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; status = "disabled"; clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; uart_A: serial@24000 { compatible = "amlogic,meson-gx-uart"; reg = <0x0 0x24000 0x0 0x18>; interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; status = "disabled"; clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; clock-names = "xtal", "pclk", "baud"; fifo-size = <128>; }; }; apb: bus@ffe00000 { compatible = "simple-bus"; reg = <0x0 0xffe00000 0x0 0x200000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; sd_emmc_b: mmc@5000 { compatible = "amlogic,meson-axg-mmc"; reg = <0x0 0x5000 0x0 0x800>; interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; clocks = <&clkc CLKID_SD_EMMC_B>, <&clkc CLKID_SD_EMMC_B_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; }; sd_emmc_c: mmc@7000 { compatible = "amlogic,meson-axg-mmc"; reg = <0x0 0x7000 0x0 0x800>; interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; clocks = <&clkc CLKID_SD_EMMC_C>, <&clkc CLKID_SD_EMMC_C_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; }; nfc: nand-controller@7800 { compatible = "amlogic,meson-axg-nfc"; reg = <0x0 0x7800 0x0 0x100>, <0x0 0x7000 0x0 0x800>; reg-names = "nfc", "emmc"; pinctrl-0 = <&nand_all_pins>; pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; clocks = <&clkc CLKID_SD_EMMC_C>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "device"; }; usb2_phy1: phy@9020 { compatible = "amlogic,meson-gxl-usb2-phy"; #phy-cells = <0>; reg = <0x0 0x9020 0x0 0x20>; clocks = <&clkc CLKID_USB>; clock-names = "phy"; resets = <&reset RESET_USB_OTG>; reset-names = "phy"; }; }; sram: sram@fffc0000 { compatible = "mmio-sram"; reg = <0x0 0xfffc0000 0x0 0x20000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0xfffc0000 0x20000>; cpu_scp_lpri: scp-sram@13000 { compatible = "amlogic,meson-axg-scp-shmem"; reg = <0x13000 0x400>; }; cpu_scp_hpri: scp-sram@13400 { compatible = "amlogic,meson-axg-scp-shmem"; reg = <0x13400 0x400>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; }; xtal: xtal-clk { compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "xtal"; #clock-cells = <0>; }; }; [ Dauer der Verarbeitung: 0.24 Sekunden (vorverarbeitet) ] |
2026-04-07