| Quellcodebibliothek Statistik Leitseite products/sources/formale Sprachen/C/Linux/arch/arm64/boot/dts/nvidia/ (Open Source Betriebssystem Version 6.17.9©) Datei vom 24.10.2025 mit Größe 159 kB |
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Quelle tegra234.dtsi Sprache: unbekannt |
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// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/tegra234-clock.h> #include <dt-bindings/gpio/tegra234-gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/tegra186-hsp.h> #include <dt-bindings/memory/tegra234-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> #include <dt-bindings/power/tegra234-powergate.h> #include <dt-bindings/reset/tegra234-reset.h> #include <dt-bindings/thermal/tegra234-bpmp-thermal.h> / { compatible = "nvidia,tegra234"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { i2c0 = &gen1_i2c; i2c1 = &gen2_i2c; i2c2 = &cam_i2c; i2c3 = &dp_aux_ch1_i2c; i2c4 = &bpmp_i2c; i2c5 = &dp_aux_ch0_i2c; i2c6 = &dp_aux_ch2_i2c; i2c7 = &gen8_i2c; i2c8 = &dp_aux_ch3_i2c; }; bus@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; misc@100000 { compatible = "nvidia,tegra234-misc"; reg = <0x0 0x00100000 0x0 0xf000>, <0x0 0x0010f000 0x0 0x1000>; status = "okay"; }; timer@2080000 { compatible = "nvidia,tegra234-timer"; reg = <0x0 0x02080000 0x0 0x00121000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; gpio: gpio@2200000 { compatible = "nvidia,tegra234-gpio"; reg-names = "security", "gpio"; reg = <0x0 0x02200000 0x0 0x10000>, <0x0 0x02210000 0x0 0x10000>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; interrupt-controller; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pinmux 0 0 164>; }; pinmux: pinmux@2430000 { compatible = "nvidia,tegra234-pinmux"; reg = <0x0 0x2430000 0x0 0x19100>; }; gpcdma: dma-controller@2600000 { compatible = "nvidia,tegra234-gpcdma", "nvidia,tegra186-gpcdma"; reg = <0x0 0x2600000 0x0 0x210000>; resets = <&bpmp TEGRA234_RESET_GPCDMA>; reset-names = "gpcdma"; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; dma-channel-mask = <0xfffffffe>; dma-coherent; }; aconnect@2900000 { compatible = "nvidia,tegra234-aconnect", "nvidia,tegra210-aconnect"; clocks = <&bpmp TEGRA234_CLK_APE>, <&bpmp TEGRA234_CLK_APB2APE>; clock-names = "ape", "apb2ape"; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; tegra_ahub: ahub@2900800 { compatible = "nvidia,tegra234-ahub"; reg = <0x0 0x02900800 0x0 0x800>; clocks = <&bpmp TEGRA234_CLK_AHUB>; clock-names = "ahub"; assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clock-rates = <81600000>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; reg = <0x0 0x2901000 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S1>, <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-rates = <1536000>; sound-name-prefix = "I2S1"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; i2s1_cif: endpoint { remote-endpoint = <&xbar_i2s1>; }; }; i2s1_port: port@1 { reg = <1>; i2s1_dap: endpoint { dai-format = "i2s"; /* placeholder for external codec */ }; }; }; }; tegra_i2s2: i2s@2901100 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; reg = <0x0 0x2901100 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S2>, <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-rates = <1536000>; sound-name-prefix = "I2S2"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; i2s2_cif: endpoint { remote-endpoint = <&xbar_i2s2>; }; }; i2s2_port: port@1 { reg = <1>; i2s2_dap: endpoint { dai-format = "i2s"; /* placeholder for external codec */ }; }; }; }; tegra_i2s3: i2s@2901200 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; reg = <0x0 0x2901200 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S3>, <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-rates = <1536000>; sound-name-prefix = "I2S3"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; i2s3_cif: endpoint { remote-endpoint = <&xbar_i2s3>; }; }; i2s3_port: port@1 { reg = <1>; i2s3_dap: endpoint { dai-format = "i2s"; /* placeholder for external codec */ }; }; }; }; tegra_i2s4: i2s@2901300 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; reg = <0x0 0x2901300 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S4>, <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-rates = <1536000>; sound-name-prefix = "I2S4"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; i2s4_cif: endpoint { remote-endpoint = <&xbar_i2s4>; }; }; i2s4_port: port@1 { reg = <1>; i2s4_dap: endpoint { dai-format = "i2s"; /* placeholder for external codec */ }; }; }; }; tegra_i2s5: i2s@2901400 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; reg = <0x0 0x2901400 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S5>, <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-rates = <1536000>; sound-name-prefix = "I2S5"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; i2s5_cif: endpoint { remote-endpoint = <&xbar_i2s5>; }; }; i2s5_port: port@1 { reg = <1>; i2s5_dap: endpoint { dai-format = "i2s"; /* placeholder for external codec */ }; }; }; }; tegra_i2s6: i2s@2901500 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; reg = <0x0 0x2901500 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S6>, <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-rates = <1536000>; sound-name-prefix = "I2S6"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; i2s6_cif: endpoint { remote-endpoint = <&xbar_i2s6>; }; }; i2s6_port: port@1 { reg = <1>; i2s6_dap: endpoint { dai-format = "i2s"; /* placeholder for external codec */ }; }; }; }; tegra_sfc1: sfc@2902000 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; reg = <0x0 0x2902000 0x0 0x200>; sound-name-prefix = "SFC1"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; sfc1_cif_in: endpoint { remote-endpoint = <&xbar_sfc1_in>; }; }; sfc1_out_port: port@1 { reg = <1>; sfc1_cif_out: endpoint { remote-endpoint = <&xbar_sfc1_out>; }; }; }; }; tegra_sfc2: sfc@2902200 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; reg = <0x0 0x2902200 0x0 0x200>; sound-name-prefix = "SFC2"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; sfc2_cif_in: endpoint { remote-endpoint = <&xbar_sfc2_in>; }; }; sfc2_out_port: port@1 { reg = <1>; sfc2_cif_out: endpoint { remote-endpoint = <&xbar_sfc2_out>; }; }; }; }; tegra_sfc3: sfc@2902400 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; reg = <0x0 0x2902400 0x0 0x200>; sound-name-prefix = "SFC3"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; sfc3_cif_in: endpoint { remote-endpoint = <&xbar_sfc3_in>; }; }; sfc3_out_port: port@1 { reg = <1>; sfc3_cif_out: endpoint { remote-endpoint = <&xbar_sfc3_out>; }; }; }; }; tegra_sfc4: sfc@2902600 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; reg = <0x0 0x2902600 0x0 0x200>; sound-name-prefix = "SFC4"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; sfc4_cif_in: endpoint { remote-endpoint = <&xbar_sfc4_in>; }; }; sfc4_out_port: port@1 { reg = <1>; sfc4_cif_out: endpoint { remote-endpoint = <&xbar_sfc4_out>; }; }; }; }; tegra_amx1: amx@2903000 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; reg = <0x0 0x2903000 0x0 0x100>; sound-name-prefix = "AMX1"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; amx1_in1: endpoint { remote-endpoint = <&xbar_amx1_in1>; }; }; port@1 { reg = <1>; amx1_in2: endpoint { remote-endpoint = <&xbar_amx1_in2>; }; }; port@2 { reg = <2>; amx1_in3: endpoint { remote-endpoint = <&xbar_amx1_in3>; }; }; port@3 { reg = <3>; amx1_in4: endpoint { remote-endpoint = <&xbar_amx1_in4>; }; }; amx1_out_port: port@4 { reg = <4>; amx1_out: endpoint { remote-endpoint = <&xbar_amx1_out>; }; }; }; }; tegra_amx2: amx@2903100 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; reg = <0x0 0x2903100 0x0 0x100>; sound-name-prefix = "AMX2"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; amx2_in1: endpoint { remote-endpoint = <&xbar_amx2_in1>; }; }; port@1 { reg = <1>; amx2_in2: endpoint { remote-endpoint = <&xbar_amx2_in2>; }; }; port@2 { reg = <2>; amx2_in3: endpoint { remote-endpoint = <&xbar_amx2_in3>; }; }; port@3 { reg = <3>; amx2_in4: endpoint { remote-endpoint = <&xbar_amx2_in4>; }; }; amx2_out_port: port@4 { reg = <4>; amx2_out: endpoint { remote-endpoint = <&xbar_amx2_out>; }; }; }; }; tegra_amx3: amx@2903200 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; reg = <0x0 0x2903200 0x0 0x100>; sound-name-prefix = "AMX3"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; amx3_in1: endpoint { remote-endpoint = <&xbar_amx3_in1>; }; }; port@1 { reg = <1>; amx3_in2: endpoint { remote-endpoint = <&xbar_amx3_in2>; }; }; port@2 { reg = <2>; amx3_in3: endpoint { remote-endpoint = <&xbar_amx3_in3>; }; }; port@3 { reg = <3>; amx3_in4: endpoint { remote-endpoint = <&xbar_amx3_in4>; }; }; amx3_out_port: port@4 { reg = <4>; amx3_out: endpoint { remote-endpoint = <&xbar_amx3_out>; }; }; }; }; tegra_amx4: amx@2903300 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; reg = <0x0 0x2903300 0x0 0x100>; sound-name-prefix = "AMX4"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; amx4_in1: endpoint { remote-endpoint = <&xbar_amx4_in1>; }; }; port@1 { reg = <1>; amx4_in2: endpoint { remote-endpoint = <&xbar_amx4_in2>; }; }; port@2 { reg = <2>; amx4_in3: endpoint { remote-endpoint = <&xbar_amx4_in3>; }; }; port@3 { reg = <3>; amx4_in4: endpoint { remote-endpoint = <&xbar_amx4_in4>; }; }; amx4_out_port: port@4 { reg = <4>; amx4_out: endpoint { remote-endpoint = <&xbar_amx4_out>; }; }; }; }; tegra_adx1: adx@2903800 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; reg = <0x0 0x2903800 0x0 0x100>; sound-name-prefix = "ADX1"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; adx1_in: endpoint { remote-endpoint = <&xbar_adx1_in>; }; }; adx1_out1_port: port@1 { reg = <1>; adx1_out1: endpoint { remote-endpoint = <&xbar_adx1_out1>; }; }; adx1_out2_port: port@2 { reg = <2>; adx1_out2: endpoint { remote-endpoint = <&xbar_adx1_out2>; }; }; adx1_out3_port: port@3 { reg = <3>; adx1_out3: endpoint { remote-endpoint = <&xbar_adx1_out3>; }; }; adx1_out4_port: port@4 { reg = <4>; adx1_out4: endpoint { remote-endpoint = <&xbar_adx1_out4>; }; }; }; }; tegra_adx2: adx@2903900 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; reg = <0x0 0x2903900 0x0 0x100>; sound-name-prefix = "ADX2"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; adx2_in: endpoint { remote-endpoint = <&xbar_adx2_in>; }; }; adx2_out1_port: port@1 { reg = <1>; adx2_out1: endpoint { remote-endpoint = <&xbar_adx2_out1>; }; }; adx2_out2_port: port@2 { reg = <2>; adx2_out2: endpoint { remote-endpoint = <&xbar_adx2_out2>; }; }; adx2_out3_port: port@3 { reg = <3>; adx2_out3: endpoint { remote-endpoint = <&xbar_adx2_out3>; }; }; adx2_out4_port: port@4 { reg = <4>; adx2_out4: endpoint { remote-endpoint = <&xbar_adx2_out4>; }; }; }; }; tegra_adx3: adx@2903a00 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; reg = <0x0 0x2903a00 0x0 0x100>; sound-name-prefix = "ADX3"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; adx3_in: endpoint { remote-endpoint = <&xbar_adx3_in>; }; }; adx3_out1_port: port@1 { reg = <1>; adx3_out1: endpoint { remote-endpoint = <&xbar_adx3_out1>; }; }; adx3_out2_port: port@2 { reg = <2>; adx3_out2: endpoint { remote-endpoint = <&xbar_adx3_out2>; }; }; adx3_out3_port: port@3 { reg = <3>; adx3_out3: endpoint { remote-endpoint = <&xbar_adx3_out3>; }; }; adx3_out4_port: port@4 { reg = <4>; adx3_out4: endpoint { remote-endpoint = <&xbar_adx3_out4>; }; }; }; }; tegra_adx4: adx@2903b00 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; reg = <0x0 0x2903b00 0x0 0x100>; sound-name-prefix = "ADX4"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; adx4_in: endpoint { remote-endpoint = <&xbar_adx4_in>; }; }; adx4_out1_port: port@1 { reg = <1>; adx4_out1: endpoint { remote-endpoint = <&xbar_adx4_out1>; }; }; adx4_out2_port: port@2 { reg = <2>; adx4_out2: endpoint { remote-endpoint = <&xbar_adx4_out2>; }; }; adx4_out3_port: port@3 { reg = <3>; adx4_out3: endpoint { remote-endpoint = <&xbar_adx4_out3>; }; }; adx4_out4_port: port@4 { reg = <4>; adx4_out4: endpoint { remote-endpoint = <&xbar_adx4_out4>; }; }; }; }; tegra_dmic1: dmic@2904000 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; reg = <0x0 0x2904000 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC1>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-rates = <3072000>; sound-name-prefix = "DMIC1"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dmic1_cif: endpoint { remote-endpoint = <&xbar_dmic1>; }; }; dmic1_port: port@1 { reg = <1>; dmic1_dap: endpoint { /* placeholder for external codec */ }; }; }; }; tegra_dmic2: dmic@2904100 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; reg = <0x0 0x2904100 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC2>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-rates = <3072000>; sound-name-prefix = "DMIC2"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dmic2_cif: endpoint { remote-endpoint = <&xbar_dmic2>; }; }; dmic2_port: port@1 { reg = <1>; dmic2_dap: endpoint { /* placeholder for external codec */ }; }; }; }; tegra_dmic3: dmic@2904200 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; reg = <0x0 0x2904200 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC3>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-rates = <3072000>; sound-name-prefix = "DMIC3"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dmic3_cif: endpoint { remote-endpoint = <&xbar_dmic3>; }; }; dmic3_port: port@1 { reg = <1>; dmic3_dap: endpoint { /* placeholder for external codec */ }; }; }; }; tegra_dmic4: dmic@2904300 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; reg = <0x0 0x2904300 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC4>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-rates = <3072000>; sound-name-prefix = "DMIC4"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dmic4_cif: endpoint { remote-endpoint = <&xbar_dmic4>; }; }; dmic4_port: port@1 { reg = <1>; dmic4_dap: endpoint { /* placeholder for external codec */ }; }; }; }; tegra_dspk1: dspk@2905000 { compatible = "nvidia,tegra234-dspk", "nvidia,tegra186-dspk"; reg = <0x0 0x2905000 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DSPK1>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-rates = <12288000>; sound-name-prefix = "DSPK1"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dspk1_cif: endpoint { remote-endpoint = <&xbar_dspk1>; }; }; dspk1_port: port@1 { reg = <1>; dspk1_dap: endpoint { /* placeholder for external codec */ }; }; }; }; tegra_dspk2: dspk@2905100 { compatible = "nvidia,tegra234-dspk", "nvidia,tegra186-dspk"; reg = <0x0 0x2905100 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DSPK2>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-rates = <12288000>; sound-name-prefix = "DSPK2"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dspk2_cif: endpoint { remote-endpoint = <&xbar_dspk2>; }; }; dspk2_port: port@1 { reg = <1>; dspk2_dap: endpoint { /* placeholder for external codec */ }; }; }; }; tegra_ope1: processing-engine@2908000 { compatible = "nvidia,tegra234-ope", "nvidia,tegra210-ope"; reg = <0x0 0x2908000 0x0 0x100>; sound-name-prefix = "OPE1"; #address-cells = <2>; #size-cells = <2>; ranges; equalizer@2908100 { compatible = "nvidia,tegra234-peq", "nvidia,tegra210-peq"; reg = <0x0 0x2908100 0x0 0x100>; }; dynamic-range-compressor@2908200 { compatible = "nvidia,tegra234-mbdrc", "nvidia,tegra210-mbdrc"; reg = <0x0 0x2908200 0x0 0x200>; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0x0>; ope1_cif_in_ep: endpoint { remote-endpoint = <&xbar_ope1_in_ep>; }; }; ope1_out_port: port@1 { reg = <0x1>; ope1_cif_out_ep: endpoint { remote-endpoint = <&xbar_ope1_out_ep>; }; }; }; }; tegra_mvc1: mvc@290a000 { compatible = "nvidia,tegra234-mvc", "nvidia,tegra210-mvc"; reg = <0x0 0x290a000 0x0 0x200>; sound-name-prefix = "MVC1"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mvc1_cif_in: endpoint { remote-endpoint = <&xbar_mvc1_in>; }; }; mvc1_out_port: port@1 { reg = <1>; mvc1_cif_out: endpoint { remote-endpoint = <&xbar_mvc1_out>; }; }; }; }; tegra_mvc2: mvc@290a200 { compatible = "nvidia,tegra234-mvc", "nvidia,tegra210-mvc"; reg = <0x0 0x290a200 0x0 0x200>; sound-name-prefix = "MVC2"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mvc2_cif_in: endpoint { remote-endpoint = <&xbar_mvc2_in>; }; }; mvc2_out_port: port@1 { reg = <1>; mvc2_cif_out: endpoint { remote-endpoint = <&xbar_mvc2_out>; }; }; }; }; tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra234-amixer", "nvidia,tegra210-amixer"; reg = <0x0 0x290bb00 0x0 0x800>; sound-name-prefix = "MIXER1"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0x0>; mix_in1: endpoint { remote-endpoint = <&xbar_mix_in1>; }; }; port@1 { reg = <0x1>; mix_in2: endpoint { remote-endpoint = <&xbar_mix_in2>; }; }; port@2 { reg = <0x2>; mix_in3: endpoint { remote-endpoint = <&xbar_mix_in3>; }; }; port@3 { reg = <0x3>; mix_in4: endpoint { remote-endpoint = <&xbar_mix_in4>; }; }; port@4 { reg = <0x4>; mix_in5: endpoint { remote-endpoint = <&xbar_mix_in5>; }; }; port@5 { reg = <0x5>; mix_in6: endpoint { remote-endpoint = <&xbar_mix_in6>; }; }; port@6 { reg = <0x6>; mix_in7: endpoint { remote-endpoint = <&xbar_mix_in7>; }; }; port@7 { reg = <0x7>; mix_in8: endpoint { remote-endpoint = <&xbar_mix_in8>; }; }; port@8 { reg = <0x8>; mix_in9: endpoint { remote-endpoint = <&xbar_mix_in9>; }; }; port@9 { reg = <0x9>; mix_in10: endpoint { remote-endpoint = <&xbar_mix_in10>; }; }; mix_out1_port: port@a { reg = <0xa>; mix_out1: endpoint { remote-endpoint = <&xbar_mix_out1>; }; }; mix_out2_port: port@b { reg = <0xb>; mix_out2: endpoint { remote-endpoint = <&xbar_mix_out2>; }; }; mix_out3_port: port@c { reg = <0xc>; mix_out3: endpoint { remote-endpoint = <&xbar_mix_out3>; }; }; mix_out4_port: port@d { reg = <0xd>; mix_out4: endpoint { remote-endpoint = <&xbar_mix_out4>; }; }; mix_out5_port: port@e { reg = <0xe>; mix_out5: endpoint { remote-endpoint = <&xbar_mix_out5>; }; }; }; }; tegra_admaif: admaif@290f000 { compatible = "nvidia,tegra234-admaif", "nvidia,tegra186-admaif"; reg = <0x0 0x0290f000 0x0 0x1000>; dmas = <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>, <&adma 3>, <&adma 3>, <&adma 4>, <&adma 4>, <&adma 5>, <&adma 5>, <&adma 6>, <&adma 6>, <&adma 7>, <&adma 7>, <&adma 8>, <&adma 8>, <&adma 9>, <&adma 9>, <&adma 10>, <&adma 10>, <&adma 11>, <&adma 11>, <&adma 12>, <&adma 12>, <&adma 13>, <&adma 13>, <&adma 14>, <&adma 14>, <&adma 15>, <&adma 15>, <&adma 16>, <&adma 16>, <&adma 17>, <&adma 17>, <&adma 18>, <&adma 18>, <&adma 19>, <&adma 19>, <&adma 20>, <&adma 20>; dma-names = "rx1", "tx1", "rx2", "tx2", "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", "rx9", "tx9", "rx10", "tx10", "rx11", "tx11", "rx12", "tx12", "rx13", "tx13", "rx14", "tx14", "rx15", "tx15", "rx16", "tx16", "rx17", "tx17", "rx18", "tx18", "rx19", "tx19", "rx20", "tx20"; interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu_niso0 TEGRA234_SID_APE>; ports { #address-cells = <1>; #size-cells = <0>; admaif0_port: port@0 { reg = <0x0>; admaif0: endpoint { remote-endpoint = <&xbar_admaif0>; }; }; admaif1_port: port@1 { reg = <0x1>; admaif1: endpoint { remote-endpoint = <&xbar_admaif1>; }; }; admaif2_port: port@2 { reg = <0x2>; admaif2: endpoint { remote-endpoint = <&xbar_admaif2>; }; }; admaif3_port: port@3 { reg = <0x3>; admaif3: endpoint { remote-endpoint = <&xbar_admaif3>; }; }; admaif4_port: port@4 { reg = <0x4>; admaif4: endpoint { remote-endpoint = <&xbar_admaif4>; }; }; admaif5_port: port@5 { reg = <0x5>; admaif5: endpoint { remote-endpoint = <&xbar_admaif5>; }; }; admaif6_port: port@6 { reg = <0x6>; admaif6: endpoint { remote-endpoint = <&xbar_admaif6>; }; }; admaif7_port: port@7 { reg = <0x7>; admaif7: endpoint { remote-endpoint = <&xbar_admaif7>; }; }; admaif8_port: port@8 { reg = <0x8>; admaif8: endpoint { remote-endpoint = <&xbar_admaif8>; }; }; admaif9_port: port@9 { reg = <0x9>; admaif9: endpoint { remote-endpoint = <&xbar_admaif9>; }; }; admaif10_port: port@a { reg = <0xa>; admaif10: endpoint { remote-endpoint = <&xbar_admaif10>; }; }; admaif11_port: port@b { reg = <0xb>; admaif11: endpoint { remote-endpoint = <&xbar_admaif11>; }; }; admaif12_port: port@c { reg = <0xc>; admaif12: endpoint { remote-endpoint = <&xbar_admaif12>; }; }; admaif13_port: port@d { reg = <0xd>; admaif13: endpoint { remote-endpoint = <&xbar_admaif13>; }; }; admaif14_port: port@e { reg = <0xe>; admaif14: endpoint { remote-endpoint = <&xbar_admaif14>; }; }; admaif15_port: port@f { reg = <0xf>; admaif15: endpoint { remote-endpoint = <&xbar_admaif15>; }; }; admaif16_port: port@10 { reg = <0x10>; admaif16: endpoint { remote-endpoint = <&xbar_admaif16>; }; }; admaif17_port: port@11 { reg = <0x11>; admaif17: endpoint { remote-endpoint = <&xbar_admaif17>; }; }; admaif18_port: port@12 { reg = <0x12>; admaif18: endpoint { remote-endpoint = <&xbar_admaif18>; }; }; admaif19_port: port@13 { reg = <0x13>; admaif19: endpoint { remote-endpoint = <&xbar_admaif19>; }; }; }; }; tegra_asrc: asrc@2910000 { compatible = "nvidia,tegra234-asrc", "nvidia,tegra186-asrc"; reg = <0x0 0x2910000 0x0 0x2000>; sound-name-prefix = "ASRC1"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0x0>; asrc_in1_ep: endpoint { remote-endpoint = <&xbar_asrc_in1_ep>; }; }; port@1 { reg = <0x1>; asrc_in2_ep: endpoint { remote-endpoint = <&xbar_asrc_in2_ep>; }; }; port@2 { reg = <0x2>; asrc_in3_ep: endpoint { remote-endpoint = <&xbar_asrc_in3_ep>; }; }; port@3 { reg = <0x3>; asrc_in4_ep: endpoint { remote-endpoint = <&xbar_asrc_in4_ep>; }; }; port@4 { reg = <0x4>; asrc_in5_ep: endpoint { remote-endpoint = <&xbar_asrc_in5_ep>; }; }; port@5 { reg = <0x5>; asrc_in6_ep: endpoint { remote-endpoint = <&xbar_asrc_in6_ep>; }; }; port@6 { reg = <0x6>; asrc_in7_ep: endpoint { remote-endpoint = <&xbar_asrc_in7_ep>; }; }; asrc_out1_port: port@7 { reg = <0x7>; asrc_out1_ep: endpoint { remote-endpoint = <&xbar_asrc_out1_ep>; }; }; asrc_out2_port: port@8 { reg = <0x8>; asrc_out2_ep: endpoint { remote-endpoint = <&xbar_asrc_out2_ep>; }; }; asrc_out3_port: port@9 { reg = <0x9>; asrc_out3_ep: endpoint { remote-endpoint = <&xbar_asrc_out3_ep>; }; }; asrc_out4_port: port@a { reg = <0xa>; asrc_out4_ep: endpoint { remote-endpoint = <&xbar_asrc_out4_ep>; }; }; asrc_out5_port: port@b { reg = <0xb>; asrc_out5_ep: endpoint { remote-endpoint = <&xbar_asrc_out5_ep>; }; }; asrc_out6_port: port@c { reg = <0xc>; asrc_out6_ep: endpoint { remote-endpoint = <&xbar_asrc_out6_ep>; }; }; }; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0x0>; xbar_admaif0: endpoint { remote-endpoint = <&admaif0>; }; }; port@1 { reg = <0x1>; xbar_admaif1: endpoint { remote-endpoint = <&admaif1>; }; }; port@2 { reg = <0x2>; xbar_admaif2: endpoint { remote-endpoint = <&admaif2>; }; }; port@3 { reg = <0x3>; xbar_admaif3: endpoint { remote-endpoint = <&admaif3>; }; }; port@4 { reg = <0x4>; xbar_admaif4: endpoint { remote-endpoint = <&admaif4>; }; }; port@5 { reg = <0x5>; xbar_admaif5: endpoint { remote-endpoint = <&admaif5>; }; }; port@6 { reg = <0x6>; xbar_admaif6: endpoint { remote-endpoint = <&admaif6>; }; }; port@7 { reg = <0x7>; xbar_admaif7: endpoint { remote-endpoint = <&admaif7>; }; }; port@8 { reg = <0x8>; xbar_admaif8: endpoint { remote-endpoint = <&admaif8>; }; }; port@9 { reg = <0x9>; xbar_admaif9: endpoint { remote-endpoint = <&admaif9>; }; }; port@a { reg = <0xa>; xbar_admaif10: endpoint { remote-endpoint = <&admaif10>; }; }; port@b { reg = <0xb>; xbar_admaif11: endpoint { remote-endpoint = <&admaif11>; }; }; port@c { reg = <0xc>; xbar_admaif12: endpoint { remote-endpoint = <&admaif12>; }; }; port@d { reg = <0xd>; xbar_admaif13: endpoint { remote-endpoint = <&admaif13>; }; }; port@e { reg = <0xe>; xbar_admaif14: endpoint { remote-endpoint = <&admaif14>; }; }; port@f { reg = <0xf>; xbar_admaif15: endpoint { remote-endpoint = <&admaif15>; }; }; port@10 { reg = <0x10>; xbar_admaif16: endpoint { remote-endpoint = <&admaif16>; }; }; port@11 { reg = <0x11>; xbar_admaif17: endpoint { remote-endpoint = <&admaif17>; }; }; port@12 { reg = <0x12>; xbar_admaif18: endpoint { remote-endpoint = <&admaif18>; }; }; port@13 { reg = <0x13>; xbar_admaif19: endpoint { remote-endpoint = <&admaif19>; }; }; xbar_i2s1_port: port@14 { reg = <0x14>; xbar_i2s1: endpoint { remote-endpoint = <&i2s1_cif>; }; }; xbar_i2s2_port: port@15 { reg = <0x15>; xbar_i2s2: endpoint { remote-endpoint = <&i2s2_cif>; }; }; xbar_i2s3_port: port@16 { reg = <0x16>; xbar_i2s3: endpoint { remote-endpoint = <&i2s3_cif>; }; }; xbar_i2s4_port: port@17 { reg = <0x17>; xbar_i2s4: endpoint { remote-endpoint = <&i2s4_cif>; }; }; xbar_i2s5_port: port@18 { reg = <0x18>; xbar_i2s5: endpoint { remote-endpoint = <&i2s5_cif>; }; }; xbar_i2s6_port: port@19 { reg = <0x19>; xbar_i2s6: endpoint { remote-endpoint = <&i2s6_cif>; }; }; xbar_dmic1_port: port@1a { reg = <0x1a>; xbar_dmic1: endpoint { remote-endpoint = <&dmic1_cif>; }; }; xbar_dmic2_port: port@1b { reg = <0x1b>; xbar_dmic2: endpoint { remote-endpoint = <&dmic2_cif>; }; }; xbar_dmic3_port: port@1c { reg = <0x1c>; xbar_dmic3: endpoint { remote-endpoint = <&dmic3_cif>; }; }; xbar_dmic4_port: port@1d { reg = <0x1d>; xbar_dmic4: endpoint { remote-endpoint = <&dmic4_cif>; }; }; xbar_dspk1_port: port@1e { reg = <0x1e>; xbar_dspk1: endpoint { remote-endpoint = <&dspk1_cif>; }; }; xbar_dspk2_port: port@1f { reg = <0x1f>; xbar_dspk2: endpoint { remote-endpoint = <&dspk2_cif>; }; }; xbar_sfc1_in_port: port@20 { reg = <0x20>; xbar_sfc1_in: endpoint { remote-endpoint = <&sfc1_cif_in>; }; }; port@21 { reg = <0x21>; xbar_sfc1_out: endpoint { remote-endpoint = <&sfc1_cif_out>; }; }; xbar_sfc2_in_port: port@22 { reg = <0x22>; xbar_sfc2_in: endpoint { remote-endpoint = <&sfc2_cif_in>; }; }; port@23 { reg = <0x23>; xbar_sfc2_out: endpoint { remote-endpoint = <&sfc2_cif_out>; }; }; xbar_sfc3_in_port: port@24 { reg = <0x24>; xbar_sfc3_in: endpoint { remote-endpoint = <&sfc3_cif_in>; }; }; port@25 { reg = <0x25>; xbar_sfc3_out: endpoint { remote-endpoint = <&sfc3_cif_out>; }; }; xbar_sfc4_in_port: port@26 { reg = <0x26>; xbar_sfc4_in: endpoint { remote-endpoint = <&sfc4_cif_in>; }; }; port@27 { reg = <0x27>; xbar_sfc4_out: endpoint { remote-endpoint = <&sfc4_cif_out>; }; }; xbar_mvc1_in_port: port@28 { reg = <0x28>; xbar_mvc1_in: endpoint { remote-endpoint = <&mvc1_cif_in>; }; }; port@29 { reg = <0x29>; xbar_mvc1_out: endpoint { remote-endpoint = <&mvc1_cif_out>; }; }; xbar_mvc2_in_port: port@2a { reg = <0x2a>; xbar_mvc2_in: endpoint { remote-endpoint = <&mvc2_cif_in>; }; }; port@2b { reg = <0x2b>; xbar_mvc2_out: endpoint { remote-endpoint = <&mvc2_cif_out>; }; }; xbar_amx1_in1_port: port@2c { reg = <0x2c>; xbar_amx1_in1: endpoint { remote-endpoint = <&amx1_in1>; }; }; xbar_amx1_in2_port: port@2d { reg = <0x2d>; xbar_amx1_in2: endpoint { remote-endpoint = <&amx1_in2>; }; }; xbar_amx1_in3_port: port@2e { reg = <0x2e>; xbar_amx1_in3: endpoint { remote-endpoint = <&amx1_in3>; }; }; xbar_amx1_in4_port: port@2f { reg = <0x2f>; xbar_amx1_in4: endpoint { remote-endpoint = <&amx1_in4>; }; }; port@30 { reg = <0x30>; xbar_amx1_out: endpoint { remote-endpoint = <&amx1_out>; }; }; xbar_amx2_in1_port: port@31 { reg = <0x31>; xbar_amx2_in1: endpoint { remote-endpoint = <&amx2_in1>; }; }; xbar_amx2_in2_port: port@32 { reg = <0x32>; xbar_amx2_in2: endpoint { remote-endpoint = <&amx2_in2>; }; }; xbar_amx2_in3_port: port@33 { reg = <0x33>; xbar_amx2_in3: endpoint { remote-endpoint = <&amx2_in3>; }; }; xbar_amx2_in4_port: port@34 { reg = <0x34>; xbar_amx2_in4: endpoint { remote-endpoint = <&amx2_in4>; }; }; port@35 { reg = <0x35>; xbar_amx2_out: endpoint { remote-endpoint = <&amx2_out>; }; }; xbar_amx3_in1_port: port@36 { reg = <0x36>; xbar_amx3_in1: endpoint { remote-endpoint = <&amx3_in1>; }; }; xbar_amx3_in2_port: port@37 { reg = <0x37>; xbar_amx3_in2: endpoint { remote-endpoint = <&amx3_in2>; }; }; xbar_amx3_in3_port: port@38 { reg = <0x38>; xbar_amx3_in3: endpoint { remote-endpoint = <&amx3_in3>; }; }; xbar_amx3_in4_port: port@39 { reg = <0x39>; xbar_amx3_in4: endpoint { remote-endpoint = <&amx3_in4>; }; }; port@3a { reg = <0x3a>; xbar_amx3_out: endpoint { remote-endpoint = <&amx3_out>; }; }; xbar_amx4_in1_port: port@3b { reg = <0x3b>; xbar_amx4_in1: endpoint { remote-endpoint = <&amx4_in1>; }; }; xbar_amx4_in2_port: port@3c { reg = <0x3c>; xbar_amx4_in2: endpoint { remote-endpoint = <&amx4_in2>; }; }; xbar_amx4_in3_port: port@3d { reg = <0x3d>; xbar_amx4_in3: endpoint { remote-endpoint = <&amx4_in3>; }; }; xbar_amx4_in4_port: port@3e { reg = <0x3e>; xbar_amx4_in4: endpoint { remote-endpoint = <&amx4_in4>; }; }; port@3f { reg = <0x3f>; xbar_amx4_out: endpoint { remote-endpoint = <&amx4_out>; }; }; xbar_adx1_in_port: port@40 { reg = <0x40>; xbar_adx1_in: endpoint { remote-endpoint = <&adx1_in>; }; }; port@41 { reg = <0x41>; xbar_adx1_out1: endpoint { remote-endpoint = <&adx1_out1>; }; }; port@42 { reg = <0x42>; xbar_adx1_out2: endpoint { remote-endpoint = <&adx1_out2>; }; }; port@43 { reg = <0x43>; xbar_adx1_out3: endpoint { remote-endpoint = <&adx1_out3>; }; }; port@44 { reg = <0x44>; xbar_adx1_out4: endpoint { remote-endpoint = <&adx1_out4>; }; }; xbar_adx2_in_port: port@45 { reg = <0x45>; xbar_adx2_in: endpoint { remote-endpoint = <&adx2_in>; }; }; port@46 { reg = <0x46>; xbar_adx2_out1: endpoint { remote-endpoint = <&adx2_out1>; }; }; port@47 { reg = <0x47>; xbar_adx2_out2: endpoint { remote-endpoint = <&adx2_out2>; }; }; port@48 { reg = <0x48>; xbar_adx2_out3: endpoint { remote-endpoint = <&adx2_out3>; }; }; port@49 { reg = <0x49>; xbar_adx2_out4: endpoint { remote-endpoint = <&adx2_out4>; }; }; xbar_adx3_in_port: port@4a { reg = <0x4a>; xbar_adx3_in: endpoint { remote-endpoint = <&adx3_in>; }; }; port@4b { reg = <0x4b>; xbar_adx3_out1: endpoint { remote-endpoint = <&adx3_out1>; }; }; port@4c { reg = <0x4c>; xbar_adx3_out2: endpoint { remote-endpoint = <&adx3_out2>; }; }; port@4d { reg = <0x4d>; xbar_adx3_out3: endpoint { remote-endpoint = <&adx3_out3>; }; }; port@4e { reg = <0x4e>; xbar_adx3_out4: endpoint { remote-endpoint = <&adx3_out4>; }; }; xbar_adx4_in_port: port@4f { reg = <0x4f>; xbar_adx4_in: endpoint { remote-endpoint = <&adx4_in>; }; }; port@50 { reg = <0x50>; xbar_adx4_out1: endpoint { remote-endpoint = <&adx4_out1>; }; }; port@51 { reg = <0x51>; xbar_adx4_out2: endpoint { remote-endpoint = <&adx4_out2>; }; }; port@52 { reg = <0x52>; xbar_adx4_out3: endpoint { remote-endpoint = <&adx4_out3>; }; }; port@53 { reg = <0x53>; xbar_adx4_out4: endpoint { remote-endpoint = <&adx4_out4>; }; }; xbar_mix_in1_port: port@54 { reg = <0x54>; xbar_mix_in1: endpoint { remote-endpoint = <&mix_in1>; }; }; xbar_mix_in2_port: port@55 { reg = <0x55>; xbar_mix_in2: endpoint { remote-endpoint = <&mix_in2>; }; }; xbar_mix_in3_port: port@56 { reg = <0x56>; xbar_mix_in3: endpoint { remote-endpoint = <&mix_in3>; }; }; xbar_mix_in4_port: port@57 { reg = <0x57>; xbar_mix_in4: endpoint { remote-endpoint = <&mix_in4>; }; }; xbar_mix_in5_port: port@58 { reg = <0x58>; xbar_mix_in5: endpoint { remote-endpoint = <&mix_in5>; }; }; xbar_mix_in6_port: port@59 { reg = <0x59>; xbar_mix_in6: endpoint { remote-endpoint = <&mix_in6>; }; }; xbar_mix_in7_port: port@5a { reg = <0x5a>; xbar_mix_in7: endpoint { remote-endpoint = <&mix_in7>; }; }; xbar_mix_in8_port: port@5b { reg = <0x5b>; xbar_mix_in8: endpoint { remote-endpoint = <&mix_in8>; }; }; xbar_mix_in9_port: port@5c { reg = <0x5c>; xbar_mix_in9: endpoint { remote-endpoint = <&mix_in9>; }; }; xbar_mix_in10_port: port@5d { reg = <0x5d>; xbar_mix_in10: endpoint { remote-endpoint = <&mix_in10>; }; }; port@5e { reg = <0x5e>; xbar_mix_out1: endpoint { remote-endpoint = <&mix_out1>; }; }; port@5f { reg = <0x5f>; xbar_mix_out2: endpoint { remote-endpoint = <&mix_out2>; }; }; port@60 { reg = <0x60>; xbar_mix_out3: endpoint { remote-endpoint = <&mix_out3>; }; }; port@61 { reg = <0x61>; xbar_mix_out4: endpoint { remote-endpoint = <&mix_out4>; }; }; port@62 { reg = <0x62>; xbar_mix_out5: endpoint { remote-endpoint = <&mix_out5>; }; }; xbar_asrc_in1_port: port@63 { reg = <0x63>; xbar_asrc_in1_ep: endpoint { remote-endpoint = <&asrc_in1_ep>; }; }; port@64 { reg = <0x64>; xbar_asrc_out1_ep: endpoint { remote-endpoint = <&asrc_out1_ep>; }; }; xbar_asrc_in2_port: port@65 { reg = <0x65>; xbar_asrc_in2_ep: endpoint { remote-endpoint = <&asrc_in2_ep>; }; }; port@66 { reg = <0x66>; xbar_asrc_out2_ep: endpoint { remote-endpoint = <&asrc_out2_ep>; }; }; xbar_asrc_in3_port: port@67 { reg = <0x67>; xbar_asrc_in3_ep: endpoint { remote-endpoint = <&asrc_in3_ep>; }; }; port@68 { reg = <0x68>; xbar_asrc_out3_ep: endpoint { remote-endpoint = <&asrc_out3_ep>; }; }; xbar_asrc_in4_port: port@69 { reg = <0x69>; xbar_asrc_in4_ep: endpoint { remote-endpoint = <&asrc_in4_ep>; }; }; port@6a { reg = <0x6a>; xbar_asrc_out4_ep: endpoint { remote-endpoint = <&asrc_out4_ep>; }; }; xbar_asrc_in5_port: port@6b { reg = <0x6b>; xbar_asrc_in5_ep: endpoint { remote-endpoint = <&asrc_in5_ep>; }; }; port@6c { reg = <0x6c>; xbar_asrc_out5_ep: endpoint { remote-endpoint = <&asrc_out5_ep>; }; }; xbar_asrc_in6_port: port@6d { reg = <0x6d>; xbar_asrc_in6_ep: endpoint { remote-endpoint = <&asrc_in6_ep>; }; }; port@6e { reg = <0x6e>; xbar_asrc_out6_ep: endpoint { remote-endpoint = <&asrc_out6_ep>; }; }; xbar_asrc_in7_port: port@6f { reg = <0x6f>; xbar_asrc_in7_ep: endpoint { remote-endpoint = <&asrc_in7_ep>; }; }; xbar_ope1_in_port: port@70 { reg = <0x70>; xbar_ope1_in_ep: endpoint { remote-endpoint = <&ope1_cif_in_ep>; }; }; port@71 { reg = <0x71>; xbar_ope1_out_ep: endpoint { remote-endpoint = <&ope1_cif_out_ep>; }; }; }; }; adma: dma-controller@2930000 { compatible = "nvidia,tegra234-adma", "nvidia,tegra186-adma"; reg = <0x0 0x02930000 0x0 0x20000>; interrupt-parent = <&agic>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; clocks = <&bpmp TEGRA234_CLK_AHUB>; clock-names = "d_audio"; status = "disabled"; }; agic: interrupt-controller@2a40000 { compatible = "nvidia,tegra234-agic", "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x02a41000 0x0 0x1000>, <0x0 0x02a42000 0x0 0x2000>; interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&bpmp TEGRA234_CLK_APE>; clock-names = "clk"; status = "disabled"; }; }; mc: memory-controller@2c00000 { compatible = "nvidia,tegra234-mc"; reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ <0x0 0x01700000 0x0 0x10000>, /* MC8 */ <0x0 0x01710000 0x0 0x10000>, /* MC9 */ <0x0 0x01720000 0x0 0x10000>, /* MC10 */ <0x0 0x01730000 0x0 0x10000>, /* MC11 */ <0x0 0x01740000 0x0 0x10000>, /* MC12 */ <0x0 0x01750000 0x0 0x10000>, /* MC13 */ <0x0 0x01760000 0x0 0x10000>, /* MC14 */ <0x0 0x01770000 0x0 0x10000>; /* MC15 */ reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; #interconnect-cells = <1>; status = "okay"; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; /* * Bit 39 of addresses passing through the memory * controller selects the XBAR format used when memory * is accessed. This is used to transparently access * memory in the XBAR format used by the discrete GPU * (bit 39 set) or Tegra (bit 39 clear). * * As a consequence, the operating system must ensure * that bit 39 is never used implicitly, for example * via an I/O virtual address mapping of an IOMMU. If * devices require access to the XBAR switch, their * drivers must set this bit explicitly. * * Limit the DMA range for memory clients to [38:0]. */ dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; emc: external-memory-controller@2c60000 { compatible = "nvidia,tegra234-emc"; reg = <0x0 0x02c60000 0x0 0x90000>, <0x0 0x01780000 0x0 0x80000>; interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_EMC>; clock-names = "emc"; status = "okay"; #interconnect-cells = <0>; nvidia,bpmp = <&bpmp>; }; }; uarta: serial@3100000 { compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x10000>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_UARTA>; resets = <&bpmp TEGRA234_RESET_UARTA>; dmas = <&gpcdma 8>, <&gpcdma 8>; dma-names = "rx", "tx"; status = "disabled"; }; uarte: serial@3140000 { compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03140000 0x0 0x10000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_UARTE>; resets = <&bpmp TEGRA234_RESET_UARTE>; dmas = <&gpcdma 20>, <&gpcdma 20>; dma-names = "rx", "tx"; status = "disabled"; }; gen1_i2c: i2c@3160000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x3160000 0x0 0x100>; status = "disabled"; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA234_CLK_I2C1>, <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C1>; reset-names = "i2c"; dmas = <&gpcdma 21>, <&gpcdma 21>; dma-names = "rx", "tx"; }; cam_i2c: i2c@3180000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x3180000 0x0 0x100>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; clock-frequency = <400000>; clocks = <&bpmp TEGRA234_CLK_I2C3>, <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C3>; reset-names = "i2c"; dmas = <&gpcdma 23>, <&gpcdma 23>; dma-names = "rx", "tx"; }; dp_aux_ch1_i2c: i2c@3190000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x3190000 0x0 0x100>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C4>, <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C4>; reset-names = "i2c"; dmas = <&gpcdma 26>, <&gpcdma 26>; dma-names = "rx", "tx"; }; dp_aux_ch0_i2c: i2c@31b0000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x31b0000 0x0 0x100>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C6>, <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C6>; reset-names = "i2c"; dmas = <&gpcdma 30>, <&gpcdma 30>; dma-names = "rx", "tx"; }; dp_aux_ch2_i2c: i2c@31c0000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x31c0000 0x0 0x100>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C7>, <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C7>; reset-names = "i2c"; dmas = <&gpcdma 27>, <&gpcdma 27>; dma-names = "rx", "tx"; }; uarti: serial@31d0000 { compatible = "arm,sbsa-uart"; reg = <0x0 0x31d0000 0x0 0x10000>; interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; dp_aux_ch3_i2c: i2c@31e0000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x31e0000 0x0 0x100>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C9>, <&bpmp TEGRA234_CLK_PLLP_OUT0>; assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C9>; reset-names = "i2c"; dmas = <&gpcdma 31>, <&gpcdma 31>; dma-names = "rx", "tx"; }; spi@3210000 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x03210000 0x0 0x1000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&bpmp TEGRA234_CLK_SPI1>; assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; clock-names = "spi"; iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; resets = <&bpmp TEGRA234_RESET_SPI1>; reset-names = "spi"; dmas = <&gpcdma 15>, <&gpcdma 15>; dma-names = "rx", "tx"; dma-coherent; status = "disabled"; }; spi@3230000 { compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; reg = <0x0 0x03230000 0x0 0x1000>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&bpmp TEGRA234_CLK_SPI3>; clock-names = "spi"; iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_SPI3>; reset-names = "spi"; dmas = <&gpcdma 17>, <&gpcdma 17>; dma-names = "rx", "tx"; dma-coherent; status = "disabled"; }; spi@3270000 { compatible = "nvidia,tegra234-qspi"; reg = <0x0 0x3270000 0x0 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, <&bpmp TEGRA234_CLK_QSPI0_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA234_RESET_QSPI0>; iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>; assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, <&bpmp TEGRA234_CLK_QSPI0_PM>; assigned-clock-rates = <199999999 99999999>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; status = "disabled"; }; pwm1: pwm@3280000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x0 0x3280000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM1>; resets = <&bpmp TEGRA234_RESET_PWM1>; reset-names = "pwm"; status = "disabled"; #pwm-cells = <2>; }; pwm2: pwm@3290000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x0 0x3290000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM2>; resets = <&bpmp TEGRA234_RESET_PWM2>; reset-names = "pwm"; status = "disabled"; #pwm-cells = <2>; }; pwm3: pwm@32a0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x0 0x32a0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM3>; resets = <&bpmp TEGRA234_RESET_PWM3>; reset-names = "pwm"; status = "disabled"; #pwm-cells = <2>; }; pwm5: pwm@32c0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x0 0x32c0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM5>; resets = <&bpmp TEGRA234_RESET_PWM5>; reset-names = "pwm"; status = "disabled"; #pwm-cells = <2>; }; pwm6: pwm@32d0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x0 0x32d0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM6>; resets = <&bpmp TEGRA234_RESET_PWM6>; reset-names = "pwm"; status = "disabled"; #pwm-cells = <2>; }; pwm7: pwm@32e0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x0 0x32e0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM7>; resets = <&bpmp TEGRA234_RESET_PWM7>; reset-names = "pwm"; status = "disabled"; #pwm-cells = <2>; }; pwm8: pwm@32f0000 { --> -------------------- --> maximum size reached --> -------------------- [ Dauer der Verarbeitung: 0.49 Sekunden (vorverarbeitet) ] |
2026-04-07