Quelle  sc7180.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: BSD-3-Clause
/*
 * SC7180 SoC device tree source
 *
 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
 */

#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sc7180.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/thermal/thermal.h>

/ {
 interrupt-parent = <&intc>;

 #address-cells = <2>;
 #size-cells = <2>;

 aliases {
  mmc1 = &sdhc_1;
  mmc2 = &sdhc_2;
  i2c0 = &i2c0;
  i2c1 = &i2c1;
  i2c2 = &i2c2;
  i2c3 = &i2c3;
  i2c4 = &i2c4;
  i2c5 = &i2c5;
  i2c6 = &i2c6;
  i2c7 = &i2c7;
  i2c8 = &i2c8;
  i2c9 = &i2c9;
  i2c10 = &i2c10;
  i2c11 = &i2c11;
  spi0 = &spi0;
  spi1 = &spi1;
  spi3 = &spi3;
  spi5 = &spi5;
  spi6 = &spi6;
  spi8 = &spi8;
  spi10 = &spi10;
  spi11 = &spi11;
 };

 chosen { };

 clocks {
  xo_board: xo-board {
   compatible = "fixed-clock";
   clock-frequency = <38400000>;
   #clock-cells = <0>;
  };

  sleep_clk: sleep-clk {
   compatible = "fixed-clock";
   clock-frequency = <32764>;
   #clock-cells = <0>;
  };
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "qcom,kryo468";
   reg = <0x0 0x0>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd0>;
   power-domain-names = "psci";
   capacity-dmips-mhz = <415>;
   dynamic-power-coefficient = <137>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   next-level-cache = <&l2_0>;
   #cooling-cells = <2>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   l2_0: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
    l3_0: l3-cache {
     compatible = "cache";
     cache-level = <3>;
     cache-unified;
    };
   };
  };

  cpu1: cpu@100 {
   device_type = "cpu";
   compatible = "qcom,kryo468";
   reg = <0x0 0x100>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd1>;
   power-domain-names = "psci";
   capacity-dmips-mhz = <415>;
   dynamic-power-coefficient = <137>;
   next-level-cache = <&l2_100>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   #cooling-cells = <2>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   l2_100: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu2: cpu@200 {
   device_type = "cpu";
   compatible = "qcom,kryo468";
   reg = <0x0 0x200>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd2>;
   power-domain-names = "psci";
   capacity-dmips-mhz = <415>;
   dynamic-power-coefficient = <137>;
   next-level-cache = <&l2_200>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   #cooling-cells = <2>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   l2_200: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu3: cpu@300 {
   device_type = "cpu";
   compatible = "qcom,kryo468";
   reg = <0x0 0x300>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd3>;
   power-domain-names = "psci";
   capacity-dmips-mhz = <415>;
   dynamic-power-coefficient = <137>;
   next-level-cache = <&l2_300>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   #cooling-cells = <2>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   l2_300: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu4: cpu@400 {
   device_type = "cpu";
   compatible = "qcom,kryo468";
   reg = <0x0 0x400>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd4>;
   power-domain-names = "psci";
   capacity-dmips-mhz = <415>;
   dynamic-power-coefficient = <137>;
   next-level-cache = <&l2_400>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   #cooling-cells = <2>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   l2_400: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu5: cpu@500 {
   device_type = "cpu";
   compatible = "qcom,kryo468";
   reg = <0x0 0x500>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd5>;
   power-domain-names = "psci";
   capacity-dmips-mhz = <415>;
   dynamic-power-coefficient = <137>;
   next-level-cache = <&l2_500>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   #cooling-cells = <2>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   l2_500: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu6: cpu@600 {
   device_type = "cpu";
   compatible = "qcom,kryo468";
   reg = <0x0 0x600>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   power-domains = <&cpu_pd6>;
   power-domain-names = "psci";
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <480>;
   next-level-cache = <&l2_600>;
   operating-points-v2 = <&cpu6_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   #cooling-cells = <2>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   l2_600: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu7: cpu@700 {
   device_type = "cpu";
   compatible = "qcom,kryo468";
   reg = <0x0 0x700>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   power-domains = <&cpu_pd7>;
   power-domain-names = "psci";
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <480>;
   next-level-cache = <&l2_700>;
   operating-points-v2 = <&cpu6_opp_table>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   #cooling-cells = <2>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   l2_700: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu0>;
    };

    core1 {
     cpu = <&cpu1>;
    };

    core2 {
     cpu = <&cpu2>;
    };

    core3 {
     cpu = <&cpu3>;
    };

    core4 {
     cpu = <&cpu4>;
    };

    core5 {
     cpu = <&cpu5>;
    };

    core6 {
     cpu = <&cpu6>;
    };

    core7 {
     cpu = <&cpu7>;
    };
   };
  };

  idle_states: idle-states {
   entry-method = "psci";

   little_cpu_sleep_0: cpu-sleep-0-0 {
    compatible = "arm,idle-state";
    idle-state-name = "little-power-down";
    arm,psci-suspend-param = <0x40000003>;
    entry-latency-us = <549>;
    exit-latency-us = <901>;
    min-residency-us = <1774>;
    local-timer-stop;
   };

   little_cpu_sleep_1: cpu-sleep-0-1 {
    compatible = "arm,idle-state";
    idle-state-name = "little-rail-power-down";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <702>;
    exit-latency-us = <915>;
    min-residency-us = <4001>;
    local-timer-stop;
   };

   big_cpu_sleep_0: cpu-sleep-1-0 {
    compatible = "arm,idle-state";
    idle-state-name = "big-power-down";
    arm,psci-suspend-param = <0x40000003>;
    entry-latency-us = <523>;
    exit-latency-us = <1244>;
    min-residency-us = <2207>;
    local-timer-stop;
   };

   big_cpu_sleep_1: cpu-sleep-1-1 {
    compatible = "arm,idle-state";
    idle-state-name = "big-rail-power-down";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <526>;
    exit-latency-us = <1854>;
    min-residency-us = <5555>;
    local-timer-stop;
   };
  };

  domain_idle_states: domain-idle-states {
   cluster_sleep_pc: cluster-sleep-0 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x41000044>;
    entry-latency-us = <2752>;
    exit-latency-us = <3048>;
    min-residency-us = <6118>;
   };

   cluster_sleep_cx_ret: cluster-sleep-1 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x41001244>;
    entry-latency-us = <3638>;
    exit-latency-us = <4562>;
    min-residency-us = <8467>;
   };

   cluster_aoss_sleep: cluster-sleep-2 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x4100b244>;
    entry-latency-us = <3263>;
    exit-latency-us = <6562>;
    min-residency-us = <9826>;
   };
  };
 };

 firmware {
  scm: scm {
   compatible = "qcom,scm-sc7180", "qcom,scm";
  };
 };

 memory@80000000 {
  device_type = "memory";
  /* We expect the bootloader to fill in the size */
  reg = <0 0x80000000 0 0>;
 };

 cpu0_opp_table: opp-table-cpu0 {
  compatible = "operating-points-v2";
  opp-shared;

  cpu0_opp1: opp-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   opp-peak-kBps = <1200000 4800000>;
  };

  cpu0_opp2: opp-576000000 {
   opp-hz = /bits/ 64 <576000000>;
   opp-peak-kBps = <1200000 4800000>;
  };

  cpu0_opp3: opp-768000000 {
   opp-hz = /bits/ 64 <768000000>;
   opp-peak-kBps = <1200000 4800000>;
  };

  cpu0_opp4: opp-1017600000 {
   opp-hz = /bits/ 64 <1017600000>;
   opp-peak-kBps = <1804000 8908800>;
  };

  cpu0_opp5: opp-1248000000 {
   opp-hz = /bits/ 64 <1248000000>;
   opp-peak-kBps = <2188000 12902400>;
  };

  cpu0_opp6: opp-1324800000 {
   opp-hz = /bits/ 64 <1324800000>;
   opp-peak-kBps = <2188000 12902400>;
  };

  cpu0_opp7: opp-1516800000 {
   opp-hz = /bits/ 64 <1516800000>;
   opp-peak-kBps = <3072000 15052800>;
  };

  cpu0_opp8: opp-1612800000 {
   opp-hz = /bits/ 64 <1612800000>;
   opp-peak-kBps = <3072000 15052800>;
  };

  cpu0_opp9: opp-1708800000 {
   opp-hz = /bits/ 64 <1708800000>;
   opp-peak-kBps = <3072000 15052800>;
  };

  cpu0_opp10: opp-1804800000 {
   opp-hz = /bits/ 64 <1804800000>;
   opp-peak-kBps = <4068000 22425600>;
  };
 };

 cpu6_opp_table: opp-table-cpu6 {
  compatible = "operating-points-v2";
  opp-shared;

  cpu6_opp1: opp-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   opp-peak-kBps = <2188000 8908800>;
  };

  cpu6_opp2: opp-652800000 {
   opp-hz = /bits/ 64 <652800000>;
   opp-peak-kBps = <2188000 8908800>;
  };

  cpu6_opp3: opp-825600000 {
   opp-hz = /bits/ 64 <825600000>;
   opp-peak-kBps = <2188000 8908800>;
  };

  cpu6_opp4: opp-979200000 {
   opp-hz = /bits/ 64 <979200000>;
   opp-peak-kBps = <2188000 8908800>;
  };

  cpu6_opp5: opp-1113600000 {
   opp-hz = /bits/ 64 <1113600000>;
   opp-peak-kBps = <2188000 8908800>;
  };

  cpu6_opp6: opp-1267200000 {
   opp-hz = /bits/ 64 <1267200000>;
   opp-peak-kBps = <4068000 12902400>;
  };

  cpu6_opp7: opp-1555200000 {
   opp-hz = /bits/ 64 <1555200000>;
   opp-peak-kBps = <4068000 15052800>;
  };

  cpu6_opp8: opp-1708800000 {
   opp-hz = /bits/ 64 <1708800000>;
   opp-peak-kBps = <6220000 19353600>;
  };

  cpu6_opp9: opp-1843200000 {
   opp-hz = /bits/ 64 <1843200000>;
   opp-peak-kBps = <6220000 19353600>;
  };

  cpu6_opp10: opp-1900800000 {
   opp-hz = /bits/ 64 <1900800000>;
   opp-peak-kBps = <6220000 22425600>;
  };

  cpu6_opp11: opp-1996800000 {
   opp-hz = /bits/ 64 <1996800000>;
   opp-peak-kBps = <6220000 22425600>;
  };

  cpu6_opp12: opp-2112000000 {
   opp-hz = /bits/ 64 <2112000000>;
   opp-peak-kBps = <6220000 22425600>;
  };

  cpu6_opp13: opp-2208000000 {
   opp-hz = /bits/ 64 <2208000000>;
   opp-peak-kBps = <7216000 22425600>;
  };

  cpu6_opp14: opp-2323200000 {
   opp-hz = /bits/ 64 <2323200000>;
   opp-peak-kBps = <7216000 22425600>;
  };

  cpu6_opp15: opp-2400000000 {
   opp-hz = /bits/ 64 <2400000000>;
   opp-peak-kBps = <8532000 23347200>;
  };

  cpu6_opp16: opp-2553600000 {
   opp-hz = /bits/ 64 <2553600000>;
   opp-peak-kBps = <8532000 23347200>;
  };
 };

 qspi_opp_table: opp-table-qspi {
  compatible = "operating-points-v2";

  opp-75000000 {
   opp-hz = /bits/ 64 <75000000>;
   required-opps = <&rpmhpd_opp_low_svs>;
  };

  opp-150000000 {
   opp-hz = /bits/ 64 <150000000>;
   required-opps = <&rpmhpd_opp_svs>;
  };

  opp-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   required-opps = <&rpmhpd_opp_nom>;
  };
 };

 qup_opp_table: opp-table-qup {
  compatible = "operating-points-v2";

  opp-75000000 {
   opp-hz = /bits/ 64 <75000000>;
   required-opps = <&rpmhpd_opp_low_svs>;
  };

  opp-100000000 {
   opp-hz = /bits/ 64 <100000000>;
   required-opps = <&rpmhpd_opp_svs>;
  };

  opp-128000000 {
   opp-hz = /bits/ 64 <128000000>;
   required-opps = <&rpmhpd_opp_nom>;
  };
 };

 pmu {
  compatible = "arm,armv8-pmuv3";
  interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";

  cpu_pd0: power-domain-cpu0 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
  };

  cpu_pd1: power-domain-cpu1 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
  };

  cpu_pd2: power-domain-cpu2 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
  };

  cpu_pd3: power-domain-cpu3 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
  };

  cpu_pd4: power-domain-cpu4 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
  };

  cpu_pd5: power-domain-cpu5 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
  };

  cpu_pd6: power-domain-cpu6 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
  };

  cpu_pd7: power-domain-cpu7 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
  };

  cluster_pd: power-domain-cluster {
   #power-domain-cells = <0>;
   domain-idle-states = <&cluster_sleep_pc
           &cluster_sleep_cx_ret
           &cluster_aoss_sleep>;
  };
 };

 reserved_memory: reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  hyp_mem: memory@80000000 {
   reg = <0x0 0x80000000 0x0 0x600000>;
   no-map;
  };

  xbl_mem: memory@80600000 {
   reg = <0x0 0x80600000 0x0 0x200000>;
   no-map;
  };

  aop_mem: memory@80800000 {
   reg = <0x0 0x80800000 0x0 0x20000>;
   no-map;
  };

  aop_cmd_db_mem: memory@80820000 {
   reg = <0x0 0x80820000 0x0 0x20000>;
   compatible = "qcom,cmd-db";
   no-map;
  };

  sec_apps_mem: memory@808ff000 {
   reg = <0x0 0x808ff000 0x0 0x1000>;
   no-map;
  };

  smem_mem: memory@80900000 {
   reg = <0x0 0x80900000 0x0 0x200000>;
   no-map;
  };

  tz_mem: memory@80b00000 {
   reg = <0x0 0x80b00000 0x0 0x3900000>;
   no-map;
  };

  ipa_fw_mem: memory@8b700000 {
   reg = <0 0x8b700000 0 0x10000>;
   no-map;
  };

  rmtfs_mem: memory@94600000 {
   compatible = "qcom,rmtfs-mem";
   reg = <0x0 0x94600000 0x0 0x200000>;
   no-map;

   qcom,client-id = <1>;
   qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
  };
 };

 smem {
  compatible = "qcom,smem";
  memory-region = <&smem_mem>;
  hwlocks = <&tcsr_mutex 3>;
 };

 smp2p-cdsp {
  compatible = "qcom,smp2p";
  qcom,smem = <94>, <432>;

  interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;

  mboxes = <&apss_shared 6>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <5>;

  cdsp_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  cdsp_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";

   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-lpass {
  compatible = "qcom,smp2p";
  qcom,smem = <443>, <429>;

  interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

  mboxes = <&apss_shared 10>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <2>;

  adsp_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  adsp_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";

   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-mpss {
  compatible = "qcom,smp2p";
  qcom,smem = <435>, <428>;
  interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
  mboxes = <&apss_shared 14>;
  qcom,local-pid = <0>;
  qcom,remote-pid = <1>;

  modem_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  modem_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  ipa_smp2p_out: ipa-ap-to-modem {
   qcom,entry-name = "ipa";
   #qcom,smem-state-cells = <1>;
  };

  ipa_smp2p_in: ipa-modem-to-ap {
   qcom,entry-name = "ipa";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 soc: soc@0 {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0 0 0 0 0x10 0>;
  dma-ranges = <0 0 0 0 0x10 0>;
  compatible = "simple-bus";

  gcc: clock-controller@100000 {
   compatible = "qcom,gcc-sc7180";
   reg = <0 0x00100000 0 0x1f0000>;
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&rpmhcc RPMH_CXO_CLK_A>,
     <&sleep_clk>;
   clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
   power-domains = <&rpmhpd SC7180_CX>;
  };

  qfprom: efuse@784000 {
   compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
   reg = <0 0x00784000 0 0x7a0>,
         <0 0x00780000 0 0x7a0>,
         <0 0x00782000 0 0x100>,
         <0 0x00786000 0 0x1fff>;

   clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
   clock-names = "core";
   #address-cells = <1>;
   #size-cells = <1>;

   qusb2p_hstx_trim: hstx-trim-primary@25b {
    reg = <0x25b 0x1>;
    bits = <1 3>;
   };

   gpu_speed_bin: gpu-speed-bin@1d2 {
    reg = <0x1d2 0x2>;
    bits = <5 8>;
   };
  };

  sdhc_1: mmc@7c4000 {
   compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
   reg = <0 0x007c4000 0 0x1000>,
    <0 0x007c5000 0 0x1000>;
   reg-names = "hc", "cqhci";

   iommus = <&apps_smmu 0x60 0x0>;
   interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
     <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "hc_irq", "pwr_irq";

   clocks = <&gcc GCC_SDCC1_AHB_CLK>,
     <&gcc GCC_SDCC1_APPS_CLK>,
     <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "iface", "core", "xo";
   interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
     <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
   interconnect-names = "sdhc-ddr","cpu-sdhc";
   power-domains = <&rpmhpd SC7180_CX>;
   operating-points-v2 = <&sdhc1_opp_table>;

   bus-width = <8>;
   non-removable;
   supports-cqe;

   mmc-ddr-1_8v;
   mmc-hs200-1_8v;
   mmc-hs400-1_8v;
   mmc-hs400-enhanced-strobe;

   status = "disabled";

   sdhc1_opp_table: opp-table {
    compatible = "operating-points-v2";

    opp-100000000 {
     opp-hz = /bits/ 64 <100000000>;
     required-opps = <&rpmhpd_opp_low_svs>;
     opp-peak-kBps = <1800000 600000>;
     opp-avg-kBps = <100000 0>;
    };

    opp-384000000 {
     opp-hz = /bits/ 64 <384000000>;
     required-opps = <&rpmhpd_opp_nom>;
     opp-peak-kBps = <5400000 1600000>;
     opp-avg-kBps = <390000 0>;
    };
   };
  };

  qupv3_id_0: geniqup@8c0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0 0x008c0000 0 0x6000>;
   clock-names = "m-ahb", "s-ahb";
   clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   iommus = <&apps_smmu 0x43 0x0>;
   status = "disabled";

   i2c0: i2c@880000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00880000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c0_default>;
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7180_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   spi0: spi@880000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00880000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   uart0: serial@880000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00880000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart0_default>;
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c1: i2c@884000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00884000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c1_default>;
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7180_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   spi1: spi@884000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00884000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   uart1: serial@884000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00884000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart1_default>;
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c2: i2c@888000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00888000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c2_default>;
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7180_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   uart2: serial@888000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00888000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart2_default>;
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c3: i2c@88c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0088c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c3_default>;
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7180_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   spi3: spi@88c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0088c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   uart3: serial@88c000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x0088c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart3_default>;
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c4: i2c@890000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00890000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c4_default>;
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7180_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   uart4: serial@890000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00890000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart4_default>;
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c5: i2c@894000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00894000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c5_default>;
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7180_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   spi5: spi@894000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00894000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   uart5: serial@894000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00894000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart5_default>;
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };
  };

  qupv3_id_1: geniqup@ac0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0 0x00ac0000 0 0x6000>;
   clock-names = "m-ahb", "s-ahb";
   clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   iommus = <&apps_smmu 0x4c3 0x0>;
   status = "disabled";

   i2c6: i2c@a80000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a80000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c6_default>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7180_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   spi6: spi@a80000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a80000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   uart6: serial@a80000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a80000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart6_default>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c7: i2c@a84000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a84000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c7_default>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7180_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   uart7: serial@a84000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a84000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart7_default>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c8: i2c@a88000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a88000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c8_default>;
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7180_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   spi8: spi@a88000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a88000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   uart8: serial@a88000 {
    compatible = "qcom,geni-debug-uart";
    reg = <0 0x00a88000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart8_default>;
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c9: i2c@a8c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a8c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c9_default>;
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7180_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   uart9: serial@a8c000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a8c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart9_default>;
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c10: i2c@a90000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a90000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c10_default>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7180_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   spi10: spi@a90000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a90000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   uart10: serial@a90000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a90000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart10_default>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c11: i2c@a94000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a94000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c11_default>;
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7180_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    status = "disabled";
   };

   spi11: spi@a94000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a94000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   uart11: serial@a94000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a94000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart11_default>;
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7180_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };
  };

  config_noc: interconnect@1500000 {
   compatible = "qcom,sc7180-config-noc";
   reg = <0 0x01500000 0 0x28000>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  system_noc: interconnect@1620000 {
   compatible = "qcom,sc7180-system-noc";
   reg = <0 0x01620000 0 0x17080>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  mc_virt: interconnect@1638000 {
   compatible = "qcom,sc7180-mc-virt";
   reg = <0 0x01638000 0 0x1000>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  qup_virt: interconnect@1650000 {
   compatible = "qcom,sc7180-qup-virt";
   reg = <0 0x01650000 0 0x1000>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  aggre1_noc: interconnect@16e0000 {
   compatible = "qcom,sc7180-aggre1-noc";
   reg = <0 0x016e0000 0 0x15080>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  aggre2_noc: interconnect@1705000 {
   compatible = "qcom,sc7180-aggre2-noc";
   reg = <0 0x01705000 0 0x9000>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  compute_noc: interconnect@170e000 {
   compatible = "qcom,sc7180-compute-noc";
   reg = <0 0x0170e000 0 0x6000>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  mmss_noc: interconnect@1740000 {
   compatible = "qcom,sc7180-mmss-noc";
   reg = <0 0x01740000 0 0x1c100>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  ufs_mem_hc: ufshc@1d84000 {
   compatible = "qcom,sc7180-ufshc", "qcom,ufshc",
         "jedec,ufs-2.0";
   reg = <0 0x01d84000 0 0x3000>;
   interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
   phys = <&ufs_mem_phy>;
   phy-names = "ufsphy";
   lanes-per-direction = <1>;
   #reset-cells = <1>;
   resets = <&gcc GCC_UFS_PHY_BCR>;
   reset-names = "rst";

   power-domains = <&gcc UFS_PHY_GDSC>;

   iommus = <&apps_smmu 0xa0 0x0>;

   clock-names = "core_clk",
          "bus_aggr_clk",
          "iface_clk",
          "core_clk_unipro",
          "ref_clk",
          "tx_lane0_sync_clk",
          "rx_lane0_sync_clk";
   clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
     <&gcc GCC_UFS_PHY_AHB_CLK>,
     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
     <&rpmhcc RPMH_CXO_CLK>,
     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
   freq-table-hz = <50000000 200000000>,
     <0 0>,
     <0 0>,
     <37500000 150000000>,
     <0 0>,
     <0 0>,
     <0 0>;

   interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
     <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
      &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
   interconnect-names = "ufs-ddr", "cpu-ufs";

   qcom,ice = <&ice>;

   status = "disabled";
  };

  ufs_mem_phy: phy@1d87000 {
   compatible = "qcom,sc7180-qmp-ufs-phy";
   reg = <0 0x01d87000 0 0x1000>;
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
     <&gcc GCC_UFS_MEM_CLKREF_CLK>;
   clock-names = "ref",
          "ref_aux",
          "qref";
   power-domains = <&gcc UFS_PHY_GDSC>;
   resets = <&ufs_mem_hc 0>;
   reset-names = "ufsphy";
   #phy-cells = <0>;
   status = "disabled";
  };

  ice: crypto@1d90000 {
   compatible = "qcom,sc7180-inline-crypto-engine",
         "qcom,inline-crypto-engine";
   reg = <0 0x01d90000 0 0x8000>;
   clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
  };

  ipa: ipa@1e40000 {
   compatible = "qcom,sc7180-ipa";

   iommus = <&apps_smmu 0x440 0x0>,
     <&apps_smmu 0x442 0x0>;
   reg = <0 0x01e40000 0 0x7000>,
         <0 0x01e47000 0 0x2000>,
         <0 0x01e04000 0 0x2c000>;
   reg-names = "ipa-reg",
        "ipa-shared",
        "gsi";

   interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
           <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
           <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
           <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "ipa",
       "gsi",
       "ipa-clock-query",
       "ipa-setup-ready";

   clocks = <&rpmhcc RPMH_IPA_CLK>;
   clock-names = "core";

   interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
     <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
     <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
   interconnect-names = "memory",
          "imem",
          "config";

   qcom,qmp = <&aoss_qmp>;

   qcom,smem-states = <&ipa_smp2p_out 0>,
        <&ipa_smp2p_out 1>;
   qcom,smem-state-names = "ipa-clock-enabled-valid",
      "ipa-clock-enabled";

   status = "disabled";
  };

  tcsr_mutex: hwlock@1f40000 {
   compatible = "qcom,tcsr-mutex";
   reg = <0 0x01f40000 0 0x20000>;
   #hwlock-cells = <1>;
  };

  tcsr_regs_1: syscon@1f60000 {
   compatible = "qcom,sc7180-tcsr", "syscon";
   reg = <0 0x01f60000 0 0x20000>;
  };

  tcsr_regs_2: syscon@1fc0000 {
   compatible = "qcom,sc7180-tcsr", "syscon";
   reg = <0 0x01fc0000 0 0x40000>;
  };

  tlmm: pinctrl@3500000 {
   compatible = "qcom,sc7180-pinctrl";
   reg = <0 0x03500000 0 0x300000>,
         <0 0x03900000 0 0x300000>,
         <0 0x03d00000 0 0x300000>;
   reg-names = "west", "north", "south";
   interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
   gpio-ranges = <&tlmm 0 0 120>;
   wakeup-parent = <&pdc>;

   dp_hot_plug_det: dp-hot-plug-det-state {
    pins = "gpio117";
    function = "dp_hot";
   };

   qspi_clk: qspi-clk-state {
    pins = "gpio63";
    function = "qspi_clk";
   };

   qspi_cs0: qspi-cs0-state {
    pins = "gpio68";
    function = "qspi_cs";
   };

   qspi_cs1: qspi-cs1-state {
    pins = "gpio72";
    function = "qspi_cs";
   };

   qspi_data0: qspi-data0-state {
    pins = "gpio64";
    function = "qspi_data";
   };

   qspi_data1: qspi-data1-state {
    pins = "gpio65";
    function = "qspi_data";
   };

   qspi_data23: qspi-data23-state {
    pins = "gpio66", "gpio67";
    function = "qspi_data";
   };

   qup_i2c0_default: qup-i2c0-default-state {
    pins = "gpio34", "gpio35";
    function = "qup00";
   };

   qup_i2c1_default: qup-i2c1-default-state {
    pins = "gpio0", "gpio1";
    function = "qup01";
   };

   qup_i2c2_default: qup-i2c2-default-state {
    pins = "gpio15", "gpio16";
    function = "qup02_i2c";
   };

   qup_i2c3_default: qup-i2c3-default-state {
    pins = "gpio38", "gpio39";
    function = "qup03";
   };

   qup_i2c4_default: qup-i2c4-default-state {
    pins = "gpio115", "gpio116";
    function = "qup04_i2c";
   };

   qup_i2c5_default: qup-i2c5-default-state {
    pins = "gpio25", "gpio26";
    function = "qup05";
   };

   qup_i2c6_default: qup-i2c6-default-state {
    pins = "gpio59", "gpio60";
    function = "qup10";
   };

   qup_i2c7_default: qup-i2c7-default-state {
    pins = "gpio6", "gpio7";
    function = "qup11_i2c";
   };

   qup_i2c8_default: qup-i2c8-default-state {
    pins = "gpio42", "gpio43";
    function = "qup12";
   };

   qup_i2c9_default: qup-i2c9-default-state {
    pins = "gpio46", "gpio47";
    function = "qup13_i2c";
   };

   qup_i2c10_default: qup-i2c10-default-state {
    pins = "gpio86", "gpio87";
    function = "qup14";
   };

   qup_i2c11_default: qup-i2c11-default-state {
    pins = "gpio53", "gpio54";
    function = "qup15";
   };

   qup_spi0_spi: qup-spi0-spi-state {
    pins = "gpio34", "gpio35", "gpio36";
    function = "qup00";
   };

   qup_spi0_cs: qup-spi0-cs-state {
    pins = "gpio37";
    function = "qup00";
   };

   qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
    pins = "gpio37";
    function = "gpio";
   };

   qup_spi1_spi: qup-spi1-spi-state {
    pins = "gpio0", "gpio1", "gpio2";
    function = "qup01";
   };

   qup_spi1_cs: qup-spi1-cs-state {
    pins = "gpio3";
    function = "qup01";
   };

   qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
    pins = "gpio3";
    function = "gpio";
   };

   qup_spi3_spi: qup-spi3-spi-state {
    pins = "gpio38", "gpio39", "gpio40";
    function = "qup03";
   };

   qup_spi3_cs: qup-spi3-cs-state {
    pins = "gpio41";
    function = "qup03";
   };

   qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
    pins = "gpio41";
    function = "gpio";
   };

   qup_spi5_spi: qup-spi5-spi-state {
    pins = "gpio25", "gpio26", "gpio27";
    function = "qup05";
   };

   qup_spi5_cs: qup-spi5-cs-state {
    pins = "gpio28";
    function = "qup05";
   };

   qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
    pins = "gpio28";
    function = "gpio";
   };

   qup_spi6_spi: qup-spi6-spi-state {
    pins = "gpio59", "gpio60", "gpio61";
    function = "qup10";
   };

   qup_spi6_cs: qup-spi6-cs-state {
    pins = "gpio62";
    function = "qup10";
   };

   qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
    pins = "gpio62";
    function = "gpio";
   };

   qup_spi8_spi: qup-spi8-spi-state {
    pins = "gpio42", "gpio43", "gpio44";
    function = "qup12";
   };

   qup_spi8_cs: qup-spi8-cs-state {
    pins = "gpio45";
    function = "qup12";
   };

   qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
    pins = "gpio45";
    function = "gpio";
   };

   qup_spi10_spi: qup-spi10-spi-state {
    pins = "gpio86", "gpio87", "gpio88";
    function = "qup14";
   };

   qup_spi10_cs: qup-spi10-cs-state {
    pins = "gpio89";
    function = "qup14";
   };

   qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
    pins = "gpio89";
    function = "gpio";
   };

   qup_spi11_spi: qup-spi11-spi-state {
    pins = "gpio53", "gpio54", "gpio55";
    function = "qup15";
   };

   qup_spi11_cs: qup-spi11-cs-state {
    pins = "gpio56";
    function = "qup15";
   };

   qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
    pins = "gpio56";
    function = "gpio";
   };

   qup_uart0_default: qup-uart0-default-state {
    qup_uart0_cts: cts-pins {
     pins = "gpio34";
     function = "qup00";
    };

    qup_uart0_rts: rts-pins {
     pins = "gpio35";
     function = "qup00";
    };

    qup_uart0_tx: tx-pins {
     pins = "gpio36";
     function = "qup00";
    };

    qup_uart0_rx: rx-pins {
     pins = "gpio37";
     function = "qup00";
    };
   };

   qup_uart1_default: qup-uart1-default-state {
    qup_uart1_cts: cts-pins {
     pins = "gpio0";
     function = "qup01";
    };

    qup_uart1_rts: rts-pins {
     pins = "gpio1";
     function = "qup01";
    };

    qup_uart1_tx: tx-pins {
     pins = "gpio2";
     function = "qup01";
    };

    qup_uart1_rx: rx-pins {
     pins = "gpio3";
     function = "qup01";
    };
   };

   qup_uart2_default: qup-uart2-default-state {
    qup_uart2_tx: tx-pins {
     pins = "gpio15";
     function = "qup02_uart";
    };

    qup_uart2_rx: rx-pins {
     pins = "gpio16";
     function = "qup02_uart";
    };
   };

   qup_uart3_default: qup-uart3-default-state {
    qup_uart3_cts: cts-pins {
     pins = "gpio38";
     function = "qup03";
    };

    qup_uart3_rts: rts-pins {
     pins = "gpio39";
     function = "qup03";
    };

    qup_uart3_tx: tx-pins {
     pins = "gpio40";
     function = "qup03";
    };

    qup_uart3_rx: rx-pins {
     pins = "gpio41";
     function = "qup03";
    };
   };

   qup_uart4_default: qup-uart4-default-state {
    qup_uart4_tx: tx-pins {
     pins = "gpio115";
     function = "qup04_uart";
    };

    qup_uart4_rx: rx-pins {
     pins = "gpio116";
     function = "qup04_uart";
    };
   };

   qup_uart5_default: qup-uart5-default-state {
    qup_uart5_cts: cts-pins {
     pins = "gpio25";
     function = "qup05";
    };

    qup_uart5_rts: rts-pins {
     pins = "gpio26";
     function = "qup05";
    };

    qup_uart5_tx: tx-pins {
     pins = "gpio27";
     function = "qup05";
    };

    qup_uart5_rx: rx-pins {
     pins = "gpio28";
     function = "qup05";
    };
   };

   qup_uart6_default: qup-uart6-default-state {
    qup_uart6_cts: cts-pins {
     pins = "gpio59";
     function = "qup10";
    };

    qup_uart6_rts: rts-pins {
     pins = "gpio60";
     function = "qup10";
    };

    qup_uart6_tx: tx-pins {
     pins = "gpio61";
     function = "qup10";
    };

    qup_uart6_rx: rx-pins {
     pins = "gpio62";
     function = "qup10";
    };
   };

   qup_uart7_default: qup-uart7-default-state {
    qup_uart7_tx: tx-pins {
     pins = "gpio6";
     function = "qup11_uart";
    };

    qup_uart7_rx: rx-pins {
     pins = "gpio7";
     function = "qup11_uart";
    };
   };

   qup_uart8_default: qup-uart8-default-state {
    qup_uart8_tx: tx-pins {
     pins = "gpio44";
     function = "qup12";
    };

    qup_uart8_rx: rx-pins {
     pins = "gpio45";
     function = "qup12";
    };
   };

   qup_uart9_default: qup-uart9-default-state {
    qup_uart9_tx: tx-pins {
     pins = "gpio46";
     function = "qup13_uart";
    };

    qup_uart9_rx: rx-pins {
     pins = "gpio47";
     function = "qup13_uart";
    };
   };

   qup_uart10_default: qup-uart10-default-state {
    qup_uart10_cts: cts-pins {
     pins = "gpio86";
     function = "qup14";
    };

    qup_uart10_rts: rts-pins {
     pins = "gpio87";
     function = "qup14";
    };

    qup_uart10_tx: tx-pins {
     pins = "gpio88";
     function = "qup14";
    };

    qup_uart10_rx: rx-pins {
     pins = "gpio89";
     function = "qup14";
    };
   };

   qup_uart11_default: qup-uart11-default-state {
    qup_uart11_cts: cts-pins {
     pins = "gpio53";
     function = "qup15";
    };

    qup_uart11_rts: rts-pins {
     pins = "gpio54";
     function = "qup15";
    };

    qup_uart11_tx: tx-pins {
     pins = "gpio55";
     function = "qup15";
    };

    qup_uart11_rx: rx-pins {
     pins = "gpio56";
     function = "qup15";
    };
   };

   sec_mi2s_active: sec-mi2s-active-state {
    pins = "gpio49", "gpio50", "gpio51";
    function = "mi2s_1";
   };

   pri_mi2s_active: pri-mi2s-active-state {
    pins = "gpio53", "gpio54", "gpio55", "gpio56";
    function = "mi2s_0";
   };

   pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
    pins = "gpio57";
    function = "lpass_ext";
   };

   ter_mi2s_active: ter-mi2s-active-state {
    pins = "gpio63", "gpio64", "gpio65", "gpio66";
    function = "mi2s_2";
   };
  };

  remoteproc_mpss: remoteproc@4080000 {
   compatible = "qcom,sc7180-mpss-pas";
   reg = <0 0x04080000 0 0x4040>;

   interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
           <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
           <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
           <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
           <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
           <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "wdog", "fatal", "ready", "handover",
       "stop-ack", "shutdown-ack";

   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "xo";

   power-domains = <&rpmhpd SC7180_CX>,
     <&rpmhpd SC7180_MX>,
     <&rpmhpd SC7180_MSS>;
   power-domain-names = "cx", "mx", "mss";

   memory-region = <&mpss_mem>;

   qcom,qmp = <&aoss_qmp>;

   qcom,smem-states = <&modem_smp2p_out 0>;
   qcom,smem-state-names = "stop";

   status = "disabled";

   glink-edge {
    interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
    label = "modem";
    qcom,remote-pid = <1>;
    mboxes = <&apss_shared 12>;
   };
  };

  gpu: gpu@5000000 {
   compatible = "qcom,adreno-618.0", "qcom,adreno";
   reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
    <0 0x05061000 0 0x800>;
   reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
   interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
   iommus = <&adreno_smmu 0>;
   operating-points-v2 = <&gpu_opp_table>;
   qcom,gmu = <&gmu>;

   #cooling-cells = <2>;

   nvmem-cells = <&gpu_speed_bin>;
   nvmem-cell-names = "speed_bin";

   interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
   interconnect-names = "gfx-mem";

   gpu_opp_table: opp-table {
    compatible = "operating-points-v2";

    opp-825000000 {
     opp-hz = /bits/ 64 <825000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
     opp-peak-kBps = <8532000>;
     opp-supported-hw = <0x04>;
    };

    opp-800000000 {
     opp-hz = /bits/ 64 <800000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
     opp-peak-kBps = <8532000>;
     opp-supported-hw = <0x07>;
    };

    opp-650000000 {
     opp-hz = /bits/ 64 <650000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
     opp-peak-kBps = <7216000>;
     opp-supported-hw = <0x07>;
    };

    opp-565000000 {
     opp-hz = /bits/ 64 <565000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
     opp-peak-kBps = <5412000>;
     opp-supported-hw = <0x07>;
    };

    opp-430000000 {
     opp-hz = /bits/ 64 <430000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
     opp-peak-kBps = <5412000>;
     opp-supported-hw = <0x07>;
    };

    opp-355000000 {
     opp-hz = /bits/ 64 <355000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
     opp-peak-kBps = <3072000>;
     opp-supported-hw = <0x07>;
    };

    opp-267000000 {
     opp-hz = /bits/ 64 <267000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
     opp-peak-kBps = <3072000>;
     opp-supported-hw = <0x07>;
    };

    opp-180000000 {
     opp-hz = /bits/ 64 <180000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
     opp-peak-kBps = <1804000>;
     opp-supported-hw = <0x07>;
    };
   };
  };

  adreno_smmu: iommu@5040000 {
   compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
   reg = <0 0x05040000 0 0x10000>;
   #iommu-cells = <1>;
   #global-interrupts = <2>;
   interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
     <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
     <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
     <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
     <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
     <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;

   clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
    <&gcc GCC_GPU_CFG_AHB_CLK>;
   clock-names = "bus", "iface";

   power-domains = <&gpucc CX_GDSC>;
  };

  gmu: gmu@506a000 {
   compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
   reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
    <0 0x0b490000 0 0x10000>;
   reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
   interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "hfi", "gmu";
   clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
          <&gpucc GPU_CC_CXO_CLK>,
          <&gcc GCC_DDRSS_GPU_AXI_CLK>,
          <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
   clock-names = "gmu", "cxo", "axi", "memnoc";
   power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
   power-domain-names = "cx", "gx";
   iommus = <&adreno_smmu 5>;
   operating-points-v2 = <&gmu_opp_table>;

   gmu_opp_table: opp-table {
    compatible = "operating-points-v2";

    opp-200000000 {
     opp-hz = /bits/ 64 <200000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
    };
   };
  };

  gpucc: clock-controller@5090000 {
   compatible = "qcom,sc7180-gpucc";
   reg = <0 0x05090000 0 0x9000>;
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
   clock-names = "bi_tcxo",
          "gcc_gpu_gpll0_clk_src",
          "gcc_gpu_gpll0_div_clk_src";
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
  };

  dma@10a2000 {
   compatible = "qcom,sc7180-dcc", "qcom,dcc";
   reg = <0x0 0x010a2000 0x0 0x1000>,
         <0x0 0x010ae000 0x0 0x2000>;
   status = "disabled";
  };

  stm@6002000 {
   compatible = "arm,coresight-stm", "arm,primecell";
   reg = <0 0x06002000 0 0x1000>,
         <0 0x16280000 0 0x180000>;
   reg-names = "stm-base", "stm-stimulus-base";

   clocks = <&aoss_qmp>;
   clock-names = "apb_pclk";

   out-ports {
    port {
     stm_out: endpoint {
      remote-endpoint = <&funnel0_in7>;
     };
    };
   };
  };

  funnel@6041000 {
   compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
   reg = <0 0x06041000 0 0x1000>;

   clocks = <&aoss_qmp>;
   clock-names = "apb_pclk";

   out-ports {
    port {
     funnel0_out: endpoint {
      remote-endpoint = <&merge_funnel_in0>;
     };
    };
   };

   in-ports {
    #address-cells = <1>;
    #size-cells = <0>;

    port@7 {
     reg = <7>;
     funnel0_in7: endpoint {
      remote-endpoint = <&stm_out>;
     };
    };
   };
  };

  funnel@6042000 {
   compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
   reg = <0 0x06042000 0 0x1000>;

   clocks = <&aoss_qmp>;
   clock-names = "apb_pclk";

   out-ports {
    port {
     funnel1_out: endpoint {
      remote-endpoint = <&merge_funnel_in1>;
     };
    };
   };

   in-ports {
    #address-cells = <1>;
    #size-cells = <0>;

    port@4 {
     reg = <4>;
     funnel1_in4: endpoint {
      remote-endpoint = <&apss_merge_funnel_out>;
     };
    };
   };
  };

  funnel@6045000 {
   compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
   reg = <0 0x06045000 0 0x1000>;

   clocks = <&aoss_qmp>;
   clock-names = "apb_pclk";

   out-ports {
    port {
     merge_funnel_out: endpoint {
      remote-endpoint = <&swao_funnel_in>;
     };
    };
   };

   in-ports {
    #address-cells = <1>;
    #size-cells = <0>;

    port@0 {
     reg = <0>;
     merge_funnel_in0: endpoint {
      remote-endpoint = <&funnel0_out>;
     };
    };

    port@1 {
     reg = <1>;
     merge_funnel_in1: endpoint {
      remote-endpoint = <&funnel1_out>;
     };
    };
   };
  };

  replicator@6046000 {
   compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
   reg = <0 0x06046000 0 0x1000>;

   clocks = <&aoss_qmp>;
   clock-names = "apb_pclk";

   out-ports {
    port {
     replicator_out: endpoint {
      remote-endpoint = <&etr_in>;
     };
    };
   };

   in-ports {
    port {
     replicator_in: endpoint {
      remote-endpoint = <&swao_replicator_out>;
     };
    };
   };
  };

  etr@6048000 {
   compatible = "arm,coresight-tmc", "arm,primecell";
   reg = <0 0x06048000 0 0x1000>;
   iommus = <&apps_smmu 0x04a0 0x20>;

   clocks = <&aoss_qmp>;
   clock-names = "apb_pclk";
   arm,scatter-gather;

   in-ports {
    port {
     etr_in: endpoint {
      remote-endpoint = <&replicator_out>;
     };
    };
   };
  };

  funnel@6b04000 {
   compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
   reg = <0 0x06b04000 0 0x1000>;

   clocks = <&aoss_qmp>;
   clock-names = "apb_pclk";

   out-ports {
    port {
     swao_funnel_out: endpoint {
      remote-endpoint = <&etf_in>;
     };
    };
   };

   in-ports {
    #address-cells = <1>;
    #size-cells = <0>;

    port@7 {
     reg = <7>;
     swao_funnel_in: endpoint {
      remote-endpoint = <&merge_funnel_out>;
     };
    };
   };
  };

  etf@6b05000 {
   compatible = "arm,coresight-tmc", "arm,primecell";
   reg = <0 0x06b05000 0 0x1000>;

   clocks = <&aoss_qmp>;
   clock-names = "apb_pclk";

   out-ports {
    port {
     etf_out: endpoint {
      remote-endpoint = <&swao_replicator_in>;
     };
    };
   };

   in-ports {
    port {
     etf_in: endpoint {
      remote-endpoint = <&swao_funnel_out>;
     };
    };
   };
  };

  replicator@6b06000 {
   compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
   reg = <0 0x06b06000 0 0x1000>;

   clocks = <&aoss_qmp>;
   clock-names = "apb_pclk";
   qcom,replicator-loses-context;

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