/* * Copyright ( C ) 2014 The Android Open Source Project * * Licensed under the Apache License , Version 2 . 0 ( the " License " ) ; * you may not use this file except in compliance with the License . * You may obtain a copy of the License at * * http : //www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing , software * distributed under the License is distributed on an " AS IS " BASIS , * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND , either express or implied . * See the License for the specific language governing permissions and * limitations under the License . #include "assembler_x86_64.h" #include <inttypes.h>#include <map>#include <random>#include "base/bit_utils.h" #include "base/macros.h" #include "base/calloc_arena_pool.h" #include "base/stl_util.h" #include "disassembler_x86.h" #include "jni_macro_assembler_x86_64.h" #include "utils/assembler_test.h" #include "utils/jni_macro_assembler_test.h" namespace art HIDDEN {0 x42);static_cast <size_t>(1 ), buffer.Size());42 );static_cast <size_t>(5 ), buffer.Size());#ifdef ART_TARGET_ANDROIDstatic constexpr size_t kRandomIterations = 1000 ; // Devices might be puny, don't stress them... #else static constexpr size_t kRandomIterations = 100000 ; // Hosts are pretty powerful. #endif // 32bit. for (int32_t i = 0 ; i < 128 ; i++) {8 >(i)) << i;for (int32_t i = 128 ; i < 255 ; i++) {8 >(i)) << i;// Do some higher ones randomly. 256 , INT32_MAX);for (size_t i = 0 ; i < kRandomIterations; i++) {8 >(value)) << value;// Negative ones. for (int32_t i = -1 ; i >= -128 ; i--) {8 >(i)) << i;for (int32_t i = -129 ; i > -256 ; i--) {8 >(i)) << i;// Do some lower ones randomly. 256 );for (size_t i = 0 ; i < 100 ; i++) {8 >(value)) << value;// 64bit. for (int64_t i = 0 ; i < 128 ; i++) {8 >(i)) << i;for (int32_t i = 128 ; i < 255 ; i++) {8 >(i)) << i;// Do some higher ones randomly. 256 , INT64_MAX);for (size_t i = 0 ; i < 100 ; i++) {8 >(value)) << value;// Negative ones. for (int64_t i = -1 ; i >= -128 ; i--) {8 >(i)) << i;for (int64_t i = -129 ; i > -256 ; i--) {8 >(i)) << i;// Do some lower ones randomly. 256 );for (size_t i = 0 ; i < kRandomIterations; i++) {8 >(value)) << value;0 x1200000010);0 x8000000000000001);struct X86_64CpuRegisterCompare {bool operator ()(const x86_64::CpuRegister& a, const x86_64::CpuRegister& b) const {return a.AsRegister() < b.AsRegister();// // Test fixture. // class AssemblerX86_64Test : public AssemblerTest<x86_64::X86_64Assembler,public :using Base = AssemblerTest<x86_64::X86_64Assembler,protected :false ; // Allow different encoding with the same size and disassembly. return InstructionSet::kX86_64;static void VerifyDisassemblerDriver(const std::vector<uint8_t>& art_code,const std::string& ref_assembly_text,const std::string& test_name) {0 U) << "Empty assembly" ;const_cast <uint8_t*>(&art_code[0 ]), art_code.size());static_cast <art::x86::DisassemblerX86*>(new DisassemblerOptions(/* absolute_addresses= */ false, /* can_read_literals = */ true, 0 ;for (const uint8_t* cur = code_mem.begin(); cur < code_mem.end(); cur += length) {// ART dumps disassembly in this format // Address: Hexbytes \t%-7s<prefix> opcode .... // Extract just the disassembly and compress spaces '\t' ) + 1 );" " ));"" );"Disassembler check failed." ;void SetUpHelpers() override {if (addresses_singleton_.size() == 0 ) {// One addressing mode to test the repeat drivers. 1 ));if (addresses_.size() == 0 ) {// Several addressing modes. 15 ));16 ));17 ));18 ));1 ));0 ));1 ));987654321 ));// Several addressing modes with the special ESP. 15 ));16 ));17 ));18 ));1 ));0 ));1 ));987654321 ));// Several addressing modes with the higher registers. 1 ));123456789 ));if (secondary_register_names_.empty()) {"eax" );"ebx" );"ecx" );"edx" );"ebp" );"esp" );"esi" );"edi" );"r8d" );"r9d" );"r10d" );"r11d" );"r12d" );"r13d" );"r14d" );"r15d" );"ax" );"bx" );"cx" );"dx" );"bp" );"sp" );"si" );"di" );"r8w" );"r9w" );"r10w" );"r11w" );"r12w" );"r13w" );"r14w" );"r15w" );"al" );"bl" );"cl" );"dl" );"bpl" );"spl" );"sil" );"dil" );"r8b" );"r9b" );"r10b" );"r11b" );"r12b" );"r13b" );"r14b" );"r15b" );void TearDown() override {return addresses_;const x86_64::CpuRegister> GetRegisters() override {static constexpr x86_64::CpuRegister kRegisters[] = {return ArrayRef<const x86_64::CpuRegister>(kRegisters);const x86_64::XmmRegister> GetFPRegisters() override {static constexpr x86_64::XmmRegister kFPRegisters[] = {return ArrayRef<const x86_64::XmmRegister>(kFPRegisters);return x86_64::Immediate(imm_value);const x86_64::CpuRegister& reg) override {return secondary_register_names_[reg];const x86_64::CpuRegister& reg) override {return tertiary_register_names_[reg];const x86_64::CpuRegister& reg) override {return quaternary_register_names_[reg];private :er_names_;r_names_;ter_names_;class AssemblerX86_64AVXTest : public AssemblerX86_64Test {public :"kabylake" , nullptr)) {}protected :return new (allocator) x86_64::X86_64Assembler(allocator, instruction_set_features_.get());const x86_64::XmmRegister> GetVectorRegisters() override {static constexpr x86_64::XmmRegister kVectorRegisters[] = {32 ),32 ),32 ),32 ),32 ),32 ),32 ),32 ),32 ),32 ),32 ),32 ),32 ),32 ),32 ),32 ),return ArrayRef<const x86_64::XmmRegister>(kVectorRegisters);private :const X86_64InstructionSetFeatures> instruction_set_features_;// // Test some repeat drivers used in the tests. // "$0\n$-1\n$18\n$4660\n$-4660\n$305419896\n$-305419896\n" ,/*f*/ nullptr, /*imm_bytes*/ 4U, "${imm}")); "$0\n$-1\n$18\n$4660\n$-4660\n$305419896\n$-305419896\n" "$20015998343868\n$-20015998343868\n$1311768467463790320\n" "$-1311768467463790320\n" ,/*f*/ nullptr, /*imm_bytes*/ 8U, "${imm}")); "%eax\n%ebx\n%ecx\n%edx\n%ebp\n%esp\n%esi\n%edi\n" "%r8d\n%r9d\n%r10d\n%r11d\n%r12d\n%r13d\n%r14d\n%r15d\n" ,/*f*/ nullptr, "%{reg}")); /*f*/ nullptr, /*imm_bytes*/ 1U, "%{reg} ${imm}"). "%eax $0\n%eax $-1\n%eax $18\n%ebx $0\n%ebx $-1\n%ebx $18\n" "%ecx $0\n%ecx $-1\n%ecx $18\n%edx $0\n%edx $-1\n%edx $18\n" ),/*f*/ nullptr, "%{reg1} %{reg2}") "%eax %eax\n%eax %ebx\n%eax %ecx\n%eax %edx\n" "%eax %ebp\n%eax %esp\n%eax %esi\n%eax %edi\n" ),/*f*/ nullptr, "%{reg1} %{reg2}"). "%eax %al\n%eax %bl\n%eax %cl\n%eax %dl\n%eax %bpl\n" "%eax %spl\n%eax %sil\n%eax %dil\n%eax %r8b\n%eax %r9b\n" ),/*f*/ nullptr, "%{reg1} %{reg2}") "%eax %xmm0\n%eax %xmm1\n%eax %xmm2\n%eax %xmm3\n" "%eax %xmm4\n%eax %xmm5\n%eax %xmm6\n%eax %xmm7\n" ),"%rax\n%rbx\n%rcx\n%rdx\n%rbp\n%rsp\n%rsi\n%rdi\n" "%r8\n%r9\n%r10\n%r11\n%r12\n%r13\n%r14\n%r15\n" ,/*f*/ nullptr, "%{reg}")); /*f*/ nullptr, /*imm_bytes*/ 1U, "%{reg} ${imm}") "%rax $0\n%rax $-1\n%rax $18\n%rbx $0\n%rbx $-1\n%rbx $18\n" "%rcx $0\n%rcx $-1\n%rcx $18\n%rdx $0\n%rdx $-1\n%rdx $18\n" ),/*f*/ nullptr, "%{reg1} %{reg2}") "%rax %eax\n%rax %ebx\n%rax %ecx\n%rax %edx\n%rax %ebp\n" "%rax %esp\n%rax %esi\n%rax %edi\n%rax %r8d\n%rax %r9d\n" ),/*f*/ nullptr, "%{reg1} %{reg2}") "%rax %rax\n%rax %rbx\n%rax %rcx\n%rax %rdx\n%rax %rbp\n" "%rax %rsp\n%rax %rsi\n%rax %rdi\n%rax %r8\n%rax %r9\n" ),/*f*/ nullptr, "%{reg1} %{reg2}") "%rax %xmm0\n%rax %xmm1\n%rax %xmm2\n%rax %xmm3\n%rax %xmm4\n" "%rax %xmm5\n%rax %xmm6\n%rax %xmm7\n%rax %xmm8\n%rax %xmm9\n" ),/*f*/ nullptr, "%{reg1} %{reg2}") "%xmm0 %xmm0\n%xmm0 %xmm1\n%xmm0 %xmm2\n%xmm0 %xmm3\n%xmm0 %xmm4\n" "%xmm0 %xmm5\n%xmm0 %xmm6\n%xmm0 %xmm7\n%xmm0 %xmm8\n%xmm0 %xmm9\n" ),/*f*/ nullptr, /*imm_bytes*/ 1U, "%{reg1} %{reg2} ${imm}") "%xmm0 %xmm0 $0\n%xmm0 %xmm0 $-1\n%xmm0 %xmm0 $18\n" "%xmm0 %xmm1 $0\n%xmm0 %xmm1 $-1\n%xmm0 %xmm1 $18\n" ),"-1(%rax,%rbx,1)\n" , RepeatA(/*f*/ nullptr, addresses_singleton_, "{mem}")); "15(%rdi,%rax,1)\n16(%rdi,%rbx,2)\n17(%rdi,%rcx,4)\n18(%rdi,%rdx,8)\n" "-1(%rax)\n(%rbx)\n1(%rsi)\n987654321(%rdi)\n15(%rsp,%rax,1)\n" "16(%rsp,%rbx,2)\n17(%rsp,%rcx,4)\n18(%rsp,%rdx,8)\n-1(%rsp)\n" "(%rsp)\n1(%rsp)\n987654321(%rsp)\n-1(%r8,%r15,2)\n123456789(%r15)\n" ,/*f*/ nullptr, "{mem}")); "-1(%rax,%rbx,1) $0\n-1(%rax,%rbx,1) $-1\n-1(%rax,%rbx,1) $18\n" ,/*f*/ nullptr, /*imm_bytes*/ 1U, addresses_singleton_, "{mem} ${imm}")); /*f*/ nullptr, addresses_singleton_, "%{reg} {mem}") "%rax -1(%rax,%rbx,1)\n%rbx -1(%rax,%rbx,1)\n%rcx -1(%rax,%rbx,1)\n" "%rdx -1(%rax,%rbx,1)\n%rbp -1(%rax,%rbx,1)\n%rsp -1(%rax,%rbx,1)\n" ),/*f*/ nullptr, addresses_singleton_, "%{reg} {mem}") "%eax -1(%rax,%rbx,1)\n%ebx -1(%rax,%rbx,1)\n%ecx -1(%rax,%rbx,1)\n" "%edx -1(%rax,%rbx,1)\n%ebp -1(%rax,%rbx,1)\n%esp -1(%rax,%rbx,1)\n" ),/*f*/ nullptr, addresses_singleton_, "{mem} %{reg}") "-1(%rax,%rbx,1) %rax\n-1(%rax,%rbx,1) %rbx\n-1(%rax,%rbx,1) %rcx\n" "-1(%rax,%rbx,1) %rdx\n-1(%rax,%rbx,1) %rbp\n-1(%rax,%rbx,1) %rsp\n" ),/*f*/ nullptr, addresses_singleton_, "{mem} %{reg}") "-1(%rax,%rbx,1) %eax\n-1(%rax,%rbx,1) %ebx\n-1(%rax,%rbx,1) %ecx\n" "-1(%rax,%rbx,1) %edx\n-1(%rax,%rbx,1) %ebp\n-1(%rax,%rbx,1) %esp\n" ),/*f*/ nullptr, addresses_singleton_, "%{reg} {mem}"). "%xmm0 -1(%rax,%rbx,1)\n%xmm1 -1(%rax,%rbx,1)\n%xmm2 -1(%rax,%rbx,1)\n" "%xmm3 -1(%rax,%rbx,1)\n%xmm4 -1(%rax,%rbx,1)\n%xmm5 -1(%rax,%rbx,1)\n" ),/*f*/ nullptr, addresses_singleton_, "{mem} %{reg}") "-1(%rax,%rbx,1) %xmm0\n-1(%rax,%rbx,1) %xmm1\n-1(%rax,%rbx,1) %xmm2\n" "-1(%rax,%rbx,1) %xmm3\n-1(%rax,%rbx,1) %xmm4\n-1(%rax,%rbx,1) %xmm5\n" ),// // Actual x86-64 instruction assembler tests. // // Make sure all addressing modes combinations are tested at least once. for (const x86_64::CpuRegister& base : GetRegisters()) {// Base only. 1 ));0 ));1 ));123456789 ));for (const x86_64::CpuRegister& index : GetRegisters()) {if (index.AsRegister() == x86_64::RSP) {// Index cannot be RSP. continue ;else if (base.AsRegister() == index.AsRegister()) {// Index only. 1 ));0 ));1 ));123456789 ));// Base and index. 1 ));0 ));1 ));123456789 ));"popq {mem}" ), "popq" );"pushq %{reg}" ), "pushq" );/*imm_bytes*/ 4U, "pushq ${imm}" ), "pushqi" );"movq %{reg2}, %{reg1}" ), "movq" );/*imm_bytes*/ 8U, "movq ${imm}, %{reg}" ), "movqi" );"mov %{reg2}, %{reg1}" ), "movl" );/*imm_bytes*/ 4U, "mov ${imm}, %{reg}" ), "movli" );"addq %{reg2}, %{reg1}" ), "addq" );/*imm_bytes*/ 4U, "addq ${imm}, %{reg}" ), "addqi" );"add %{reg2}, %{reg1}" ), "addl" );/*imm_bytes*/ 4U, "add ${imm}, %{reg}" ), "addli" );/*imm_bytes*/2U, "addw ${imm}, {mem}"), "addw"); /*imm_bytes*/2U, "addw ${imm}, %{reg}"), "addw"); "addw %{reg}, {mem}" ), "addw" );"imulq %{reg}" ), "imulq" );"imulq %{reg2}, %{reg1}" ), "imulq" );/*imm_bytes*/ 4U, "imulq ${imm}, %{reg}, %{reg}" ),"imulqi" );"imul %{reg2}, %{reg1}" ), "imull" );/*imm_bytes*/ 4U, "imull ${imm}, %{reg}, %{reg}" ),"imulli" );"mull %{reg}" ), "mull" );"subq %{reg2}, %{reg1}" ), "subq" );/*imm_bytes*/ 4U, "subq ${imm}, %{reg}" ), "subqi" );"sub %{reg2}, %{reg1}" ), "subl" );/*imm_bytes*/ 4U, "sub ${imm}, %{reg}" ), "subli" );// Shll only allows CL as the shift count. ler* assembler) {const x86_64::CpuRegister> registers = assembler_test->GetRegisters();for (auto && reg : registers) {"shll %cl, %" << assembler_test->GetSecondaryRegisterName(reg) << "\n" ;return str.str();"shll" );/*imm_bytes*/ 1U, "shll ${imm}, %{reg}" ), "shlli" );// Shlq only allows CL as the shift count. ler* assembler) {const x86_64::CpuRegister> registers = assembler_test->GetRegisters();for (auto && reg : registers) {"shlq %cl, %" << assembler_test->GetRegisterName(reg) << "\n" ;return str.str();"shlq" );/*imm_bytes*/ 1U, "shlq ${imm}, %{reg}" ), "shlqi" );// Shrl only allows CL as the shift count. ler* assembler) {const x86_64::CpuRegister> registers = assembler_test->GetRegisters();for (auto && reg : registers) {"shrl %cl, %" << assembler_test->GetSecondaryRegisterName(reg) << "\n" ;return str.str();"shrl" );/*imm_bytes*/ 1U, "shrl ${imm}, %{reg}"), "shrli"); // Shrq only allows CL as the shift count. ler* assembler) {const x86_64::CpuRegister> registers = assembler_test->GetRegisters();for (auto && reg : registers) {"shrq %cl, %" << assembler_test->GetRegisterName(reg) << "\n" ;return str.str();"shrq" );/*imm_bytes*/ 1U, "shrq ${imm}, %{reg}"), "shrqi"); // Sarl only allows CL as the shift count. ler* assembler) {const x86_64::CpuRegister> registers = assembler_test->GetRegisters();for (auto && reg : registers) {"sarl %cl, %" << assembler_test->GetSecondaryRegisterName(reg) << "\n" ;return str.str();"sarl" );/*imm_bytes*/ 1U, "sarl ${imm}, %{reg}"), "sarli"); // Sarq only allows CL as the shift count. ler* assembler) {const x86_64::CpuRegister> registers = assembler_test->GetRegisters();for (auto && reg : registers) {"sarq %cl, %" << assembler_test->GetRegisterName(reg) << "\n" ;return str.str();"sarq" );/*imm_bytes*/ 1U, "sarq ${imm}, %{reg}"), "sarqi"); // Rorl only allows CL as the shift count. ler* assembler) {const x86_64::CpuRegister> registers = assembler_test->GetRegisters();for (auto && reg : registers) {"rorl %cl, %" << assembler_test->GetSecondaryRegisterName(reg) << "\n" ;return str.str();"rorl" );/*imm_bytes*/ 1U, "rorl ${imm}, %{reg}"), "rorli"); // Roll only allows CL as the shift count. ler* assembler) {const x86_64::CpuRegister> registers = assembler_test->GetRegisters();for (auto && reg : registers) {"roll %cl, %" << assembler_test->GetSecondaryRegisterName(reg) << "\n" ;return str.str();"roll" );/*imm_bytes*/ 1U, "roll ${imm}, %{reg}"), "rolli"); // Rorq only allows CL as the shift count. ler* assembler) {const x86_64::CpuRegister> registers = assembler_test->GetRegisters();for (auto && reg : registers) {"rorq %cl, %" << assembler_test->GetRegisterName(reg) << "\n" ;return str.str();"rorq" );/*imm_bytes*/ 1U, "rorq ${imm}, %{reg}"), "rorqi"); // Rolq only allows CL as the shift count. ler* assembler) {const x86_64::CpuRegister> registers = assembler_test->GetRegisters();for (auto && reg : registers) {"rolq %cl, %" << assembler_test->GetRegisterName(reg) << "\n" ;return str.str();"rolq" );/*imm_bytes*/ 1U, "rolq ${imm}, %{reg}"), "rolqi"); "cmpq %{reg2}, %{reg1}" ), "cmpq" );/*imm_bytes*/ 4U, "cmpq ${imm}, %{reg}" ), "cmpqi" ); // only imm32 "cmp %{reg2}, %{reg1}" ), "cmpl" );/*imm_bytes*/ 4U, "cmpl ${imm}, %{reg}"), "cmpli"); // Note: uses different order for GCC than usual. This makes GCC happy, and doesn't have an // impact on functional correctness. "testl %{reg1}, %{reg2}" ), "testl" );"idivq %{reg}" ), "idivq" );"idivl %{reg}" ), "idivl" );"divq %{reg}" ), "divq" );"divl %{reg}" ), "divl" );"negq %{reg}" ), "negq" );"negl %{reg}" ), "negl" );"notq %{reg}" ), "notq" );"notl %{reg}" ), "notl" );"andq %{reg2}, %{reg1}" ), "andq" );/*imm_bytes*/ 4U, "andq ${imm}, %{reg}" ), "andqi" ); // only imm32 "andl %{reg2}, %{reg1}" ), "andl" );/*imm_bytes*/ 4U, "andl ${imm}, %{reg}" ), "andli" );/*imm_bytes*/2U, "andw ${imm}, {mem}"), "andw"); "orq %{reg2}, %{reg1}" ), "orq" );"orl %{reg2}, %{reg1}" ), "orl" );/*imm_bytes*/ 4U, "orl ${imm}, %{reg}"), "orli"); "xorq %{reg2}, %{reg1}" ), "xorq" );/*imm_bytes*/ 4U, "xorq ${imm}, %{reg}"), "xorqi"); "xor %{reg2}, %{reg1}" ), "xorl" );/*imm_bytes*/ 4U, "xor ${imm}, %{reg}"), "xorli"); "xchgq %{reg2}, %{reg1}" ), "xchgq" );"xchgq %{reg}, {mem}" ), "xchgq" );// Exclude `xcghl eax, eax` because the reference implementation generates 0x87 0xC0 (contrary to // the intel manual saying that this should be a `nop` 0x90). All other cases are the same. static const std::vector<std::pair<x86_64::CpuRegister, x86_64::CpuRegister>> except = {)"xchgl %{reg2}, %{reg1}" , &except), "xchgl" );"xchgl %{reg}, {mem}" ), "xchgl" );"xchgw %{reg2}, %{reg1}" ), "xchgw" );"xchgw %{reg}, {mem}" ), "xchgw" );"xchgb %{reg2}, %{reg1}" ), "xchgb" );"xchgb %{reg}, {mem}" ), "xchgb" );"xaddq %{reg2}, %{reg1}" ), "xaddq" );"xaddq %{reg}, {mem}" ), "xaddq" );"xaddl %{reg2}, %{reg1}" ), "xaddl" );"xaddl %{reg}, {mem}" ), "xaddl" );"xaddw %{reg2}, %{reg1}" ), "xaddw" );"xaddw %{reg}, {mem}" ), "xaddw" );"xaddb %{reg2}, %{reg1}" ), "xaddb" );"xaddb %{reg}, {mem}" ), "xaddb" );"lock xaddq %{reg}, {mem}" ), "lock_xaddq" );"lock xaddl %{reg}, {mem}" ), "lock_xaddl" );"lock xaddw %{reg}, {mem}" ), "lock_xaddw" );"lock xaddb %{reg}, {mem}" ), "lock_xaddb" );"cmpxchgb %{reg}, {mem}" ), "cmpxchgb" );"cmpxchgw %{reg}, {mem}" ), "cmpxchgw" );"cmpxchgl %{reg}, {mem}" ), "cmpxchgl" );"cmpxchg %{reg}, {mem}" ), "cmpxchg" );"lock cmpxchgb %{reg}, {mem}" ), "lock_cmpxchgb" );"lock cmpxchgw %{reg}, {mem}" ), "lock_cmpxchgw" );"lock cmpxchgl %{reg}, {mem}" ), "lock_cmpxchgl" );"lock cmpxchg %{reg}, {mem}" ), "lock_cmpxchg" );"movq %{reg}, {mem}" ), "movq_s" );"movq {mem}, %{reg}" ), "movq_l" );"movl %{reg}, {mem}" ), "movl_s" );"movl {mem}, %{reg}" ), "movl_l" );"movw %{reg}, {mem}" ), "movw_s" );"movb %{reg}, {mem}" ), "movb_s" );/*imm_bytes*/ 2U, "cmpw ${imm}, {mem}"), "cmpw"); /*imm_bytes*/ 4U, "movq ${imm}, {mem}" ), "movq" ); // only imm32 /*imm_bytes*/ 4U, "movl ${imm}, {mem}"), "movl"); /*imm_bytes*/ 2U, "movw ${imm}, {mem}"), "movw"); /*imm_bytes*/ 1U, "movb ${imm}, {mem}"), "movb"); "movntil %{reg}, {mem}" ), "movntl" );"movntiq %{reg}, {mem}" ), "movntq" );0 ),/*is64bit*/ false); 0 ),/*is64bit*/ true); const char * expected = "cvtsi2ss 0(%RAX), %xmm0\n" "cvtsi2ssq 0(%RAX), %xmm0\n" ;"cvtsi2ss" );0 ),/*is64bit*/ false); 0 ),/*is64bit*/ true); const char * expected = "cvtsi2sd 0(%RAX), %xmm0\n" "cvtsi2sdq 0(%RAX), %xmm0\n" ;"cvtsi2sd" );"cmpq {mem}, %{reg}" ), "cmpq" );"movslq {mem}, %{reg}" ), "movsxd" );"testq {mem}, %{reg}" ), "testq" );"addq {mem}, %{reg}" ), "addq" );"subq {mem}, %{reg}" ), "subq" );"cvtss2sd {mem}, %{reg}" ), "cvtss2sd" );"cvtsd2ss {mem}, %{reg}" ), "cvtsd2ss" );"comiss {mem}, %{reg}" ), "comiss" );"comisd {mem}, %{reg}" ), "comisd" );"ucomiss {mem}, %{reg}" ), "ucomiss" );"ucomisd {mem}, %{reg}" ), "ucomisd" );"andq {mem}, %{reg}" ), "andq" );"orq {mem}, %{reg}" ), "orq" );"xorq {mem}, %{reg}" ), "xorq" );const char * expected = "repne scasb\n" ;"repne_scasb" );const char * expected = "repne scasw\n" ;"repne_scasw" );const char * expected = "rep movsb\n" ;"rep_movsb" );const char * expected = "rep movsw\n" ;"rep_movsw" );const char * expected = "rep movsl\n" ;"rep_movsl" );"movslq %{reg2}, %{reg1}" ), "movsxd" );"movaps %{reg2}, %{reg1}" ), "movaps" );"vmovaps %{reg2}, %{reg1}" ), "vmovaps" );"vmovaps %{reg2}, %{reg1}" ), "avx_movaps" );"movaps %{reg}, {mem}" ), "movaps_s" );"vmovaps %{reg}, {mem}" ), "vmovaps_s" );"vmovaps %{reg}, {mem}" ), "avx_movaps_s" );"movaps {mem}, %{reg}" ), "movaps_l" );"vmovaps {mem}, %{reg}" ), "vmovaps_l" );"vmovaps {mem}, %{reg}" ), "avx_movaps_l" );"movups %{reg}, {mem}" ), "movups_s" );"vmovups %{reg}, {mem}" ), "vmovups_s" );"vmovups %{reg}, {mem}" ), "avx_movups_s" );"movups {mem}, %{reg}" ), "movups_l" );"vmovups {mem}, %{reg}" ), "vmovups_l" );"vmovups {mem}, %{reg}" ), "avx_movups_l" );"movss %{reg2}, %{reg1}" ), "movss" );"vmovss %{reg3}, %{reg2}, %{reg1}" ),"vmovss" );// Cannot verify auto forwarding as assembly supports only xmm regs inspite of passing vreg // TEST_F(AssemblerX86_64AVXTest, Movss) { // DriverStr(RepeatVV(&x86_64::X86_64Assembler::movss, "vmovss %{reg2}, %{reg1}, %{reg1}"), // "avx_movss"); // } "movss {mem}, %{reg}" ), "movss_l" );"vmovss {mem}, %{reg}" ), "vmovss_l" );// Cannot verify auto forwarding as assembly supports only xmm regs inspite of passing vreg // TEST_F(AssemblerX86_64AVXTest, MovssLoad) { // DriverStr(RepeatVA(&x86_64::X86_64Assembler::movss, "vmovss {mem}, %{reg}"), "avx_movss_l"); // } "movss %{reg}, {mem}" ), "movss_s" );"vmovss %{reg}, {mem}" ), "vmovss_s" );// Cannot verify auto forwarding as assembly supports only xmm regs inspite of passing vreg // TEST_F(AssemblerX86_64AVXTest, MovssStore) { // DriverStr(RepeatAF(&x86_64::X86_64Assembler::movss, "vmovss %{reg}, {mem}"), "avx_movss_s"); // } "movapd %{reg2}, %{reg1}" ), "movapd" );"vmovapd %{reg2}, %{reg1}" ), "vmovapd" );"vmovapd %{reg2}, %{reg1}" ), "avx_movapd" );"movapd %{reg}, {mem}" ), "movapd_s" );"vmovapd %{reg}, {mem}" ), "vmovapd_s" );"vmovapd %{reg}, {mem}" ), "avx_movapd_s" );"movapd {mem}, %{reg}" ), "movapd_l" );"vmovapd {mem}, %{reg}" ), "vmovapd_l" );"vmovapd {mem}, %{reg}" ), "avx_movapd_l" );"movupd %{reg}, {mem}" ), "movupd_s" );"vmovupd %{reg}, {mem}" ), "vmovupd_s" );"vmovupd %{reg}, {mem}" ), "avx_movupd_s" );"movupd {mem}, %{reg}" ), "movupd_l" );"vmovupd {mem}, %{reg}" ), "vmovupd_l" );"vmovupd {mem}, %{reg}" ), "avx_movupd_l" );"movsd %{reg2}, %{reg1}" ), "movsd" );"vmovsd %{reg3}, %{reg2}, %{reg1}" ),"vmovsd" );// Cannot verify auto forwarding as assembly supports only xmm regs inspite of passing vreg // TEST_F(AssemblerX86_64AVXTest, Movsd) { // DriverStr(RepeatFF(&x86_64::X86_64Assembler::movsd, "vmovsd %{reg2}, %{reg1}, %{reg1}"), // "avx_movsd"); // } "movsd {mem}, %{reg}" ), "movsd_l" );"vmovsd {mem}, %{reg}" ), "vmovsd_l" );// Cannot verify auto forwarding as assembly supports only xmm regs inspite of passing vreg // TEST_F(AssemblerX86_64AVXTest, MovsdLoad) { // DriverStr(RepeatFA(&x86_64::X86_64Assembler::movsd, "vmovsd {mem}, %{reg}"), "avx_movsd_l"); // } "movsd %{reg}, {mem}" ), "movsd_s" );"vmovsd %{reg}, {mem}" ), "vmovsd_s" );// Cannot verify auto forwarding as assembly supports only xmm regs inspite of passing vreg // TEST_F(AssemblerX86_64AVXTest, MovsdStore) { // DriverStr(RepeatAF(&x86_64::X86_64Assembler::movsd, "vmovsd %{reg2}, {mem}"), "avx_movsd_s"); // } "movdqa %{reg2}, %{reg1}" ), "movdqa" );"vmovdqa %{reg2}, %{reg1}" ), "vmovdqa" );"vmovdqa %{reg2}, %{reg1}" ), "avx_movdqa" );"movdqa %{reg}, {mem}" ), "movdqa_s" );"vmovdqa %{reg}, {mem}" ), "vmovdqa_s" );"vmovdqa %{reg}, {mem}" ), "avx_movdqa_s" );"movdqa {mem}, %{reg}" ), "movdqa_l" );"vmovdqa {mem}, %{reg}" ), "vmovdqa_l" );"vmovdqa {mem}, %{reg}" ), "avx_movdqa_l" );"movdqu %{reg}, {mem}" ), "movdqu_s" );"vmovdqu %{reg}, {mem}" ), "vmovdqu_s" );"vmovdqu %{reg}, {mem}" ), "avx_movdqu_s" );"movdqu {mem}, %{reg}" ), "movdqu_l" );"vmovdqu {mem}, %{reg}" ), "vmovdqu_l" );"vmovdqu {mem}, %{reg}" ), "avx_movdqu_l" );"movq %{reg2}, %{reg1}" ), "movq.1" );"vmovq %{reg2}, %{reg1}" ), "vmovq.1" );// Cannot verify auto forwarding as assembly supports only xmm regs inspite of passing vreg // TEST_F(AssemblerX86_64AVXTest, Movq1) { // DriverStr(RepeatVR(&x86_64::X86_64Assembler::movq, "vmovq %{reg2}, %{reg1}"), "avx_movq.1"); // } "movq %{reg2}, %{reg1}" ), "movq.2" );"vmovq %{reg2}, %{reg1}" ), "vmovq.2" );// Cannot verify auto forwarding as assembly supports only xmm regs inspite of passing vreg // TEST_F(AssemblerX86_64AVXTest, Movq2) { // DriverStr(RepeatRV(&x86_64::X86_64Assembler::movq, "vmovq %{reg2}, %{reg1}"), "avx_movq.2"); // } "movd %{reg2}, %{reg1}" ), "movd.1" );"vmovd %{reg2}, %{reg1}" ), "vmovd.1" );// Cannot verify auto forwarding as assembly supports only xmm regs inspite of passing vreg // TEST_F(AssemblerX86_64AVXTest, Movd1) { // DriverStr(RepeatVr(&x86_64::X86_64Assembler::movd, "vmovd %{reg2}, %{reg1}"), "avx_movd.1"); // } "movd %{reg2}, %{reg1}" ), "movd.2" );"vmovd %{reg2}, %{reg1}" ), "vmovd.2" );// Cannot verify auto forwarding as assembly supports only xmm regs inspite of passing vreg // TEST_F(AssemblerX86_64AVXTest, Movd2) { // DriverStr(RepeatrV(&x86_64::X86_64Assembler::movd, "vmovd %{reg2}, %{reg1}"), "avx_movd.2"); // } "addss %{reg2}, %{reg1}" ), "addss" );"addsd %{reg2}, %{reg1}" ), "addsd" );"addps %{reg2}, %{reg1}" ), "addps" );"vaddps %{reg3}, %{reg2}, %{reg1}" ),"vaddps" );"vaddps %{reg2}, %{reg1}, %{reg1}" ),"avx_addps" );"addpd %{reg2}, %{reg1}" ), "addpd" );"vaddpd %{reg3}, %{reg2}, %{reg1}" ),"vaddpd" );"vaddpd %{reg2}, %{reg1}, %{reg1}" ),"avx_addpd" );"subss %{reg2}, %{reg1}" ), "subss" );"subsd %{reg2}, %{reg1}" ), "subsd" );"subps %{reg2}, %{reg1}" ), "subps" );"vsubps %{reg3}, %{reg2}, %{reg1}" ),"vsubps" );"vsubps %{reg2}, %{reg1}, %{reg1}" ),"avx_subps" );"subpd %{reg2}, %{reg1}" ), "subpd" );"vsubpd %{reg3}, %{reg2}, %{reg1}" ),"vsubpd" );"vsubpd %{reg2}, %{reg1}, %{reg1}" ),"avx_subpd" );"mulss %{reg2}, %{reg1}" ), "mulss" );"mulsd %{reg2}, %{reg1}" ), "mulsd" );"mulps %{reg2}, %{reg1}" ), "mulps" );"vmulps %{reg3}, %{reg2}, %{reg1}" ),"vmulps" );"vmulps %{reg2}, %{reg1}, %{reg1}" ),"avx_vmulps" );"mulpd %{reg2}, %{reg1}" ), "mulpd" );"vmulpd %{reg3}, %{reg2}, %{reg1}" ),"vmulpd" );"vmulpd %{reg2}, %{reg1}, %{reg1}" ),"avx_mulpd" );"divss %{reg2}, %{reg1}" ), "divss" );"divsd %{reg2}, %{reg1}" ), "divsd" );"divps %{reg2}, %{reg1}" ), "divps" );"vdivps %{reg3}, %{reg2}, %{reg1}" ),"vdivps" );"vdivps %{reg2}, %{reg1}, %{reg1}" ),"avx_divps" );"divpd %{reg2}, %{reg1}" ), "divpd" );"vdivpd %{reg3}, %{reg2}, %{reg1}" ),"vdivpd" );"vdivpd %{reg2}, %{reg1}, %{reg1}" ),"avx_divpd" );"paddb %{reg2}, %{reg1}" ), "paddb" );"vpaddb %{reg3}, %{reg2}, %{reg1}" ),"vpaddb" );"vpaddb %{reg2}, %{reg1}, %{reg1}" ),"avx_paddb" );"psubb %{reg2}, %{reg1}" ), "psubb" );"vpsubb %{reg3},%{reg2}, %{reg1}" ),"vpsubb" );"vpsubb %{reg2},%{reg1}, %{reg1}" ),"avx_psubb" );"paddw %{reg2}, %{reg1}" ), "paddw" );"vpaddw %{reg3}, %{reg2}, %{reg1}" ),"vpaddw" );"vpaddw %{reg2}, %{reg1}, %{reg1}" ),"avx_paddw" );"psubw %{reg2}, %{reg1}" ), "psubw" );"vpsubw %{reg3}, %{reg2}, %{reg1}" ),"vpsubw" );"vpsubw %{reg2}, %{reg1}, %{reg1}" ),"avx_psubw" );"pmullw %{reg2}, %{reg1}" ), "pmullw" );"vpmullw %{reg3}, %{reg2}, %{reg1}" ),"vpmullw" );"vpmullw %{reg2}, %{reg1}, %{reg1}" ),"avx_pmullw" );"paddd %{reg2}, %{reg1}" ), "paddd" );"vpaddd %{reg3}, %{reg2}, %{reg1}" ),"vpaddd" );"vpaddd %{reg2}, %{reg1}, %{reg1}" ),"avx_paddd" );"psubd %{reg2}, %{reg1}" ), "psubd" );"vpsubd %{reg3}, %{reg2}, %{reg1}" ),"vpsubd" );"vpsubd %{reg2}, %{reg1}, %{reg1}" ),"avx_psubd" );"pmulld %{reg2}, %{reg1}" ), "pmulld" );"vpmulld %{reg3}, %{reg2}, %{reg1}" ),"vpmulld" );"vpmulld %{reg2}, %{reg1}, %{reg1}" ),"avx_pmulld" );"paddq %{reg2}, %{reg1}" ), "paddq" );"vpaddq %{reg3}, %{reg2}, %{reg1}" ),"vpaddq" );"vpaddq %{reg2}, %{reg1}, %{reg1}" ),"avx_paddq" );"psubq %{reg2}, %{reg1}" ), "psubq" );"vpsubq %{reg3}, %{reg2}, %{reg1}" ),"vpsubq" );"vpsubq %{reg2}, %{reg1}, %{reg1}" ),"avx_psubq" );"paddusb %{reg2}, %{reg1}" ), "paddusb" );"vpaddusb %{reg3}, %{reg2}, %{reg1}" ),"vpaddusb" );"vpaddusb %{reg2}, %{reg1}, %{reg1}" ),"avx_paddusb" );"paddsb %{reg2}, %{reg1}" ), "paddsb" );"vpaddsb %{reg3}, %{reg2}, %{reg1}" ),"vpaddsb" );"vpaddsb %{reg2}, %{reg1}, %{reg1}" ),"avx_paddsb" );"paddusw %{reg2}, %{reg1}" ), "paddusw" );"vpaddusw %{reg3}, %{reg2}, %{reg1}" ),"vpaddusw" );"vpaddusw %{reg2}, %{reg1}, %{reg1}" ),"avx_paddusw" );"paddsw %{reg2}, %{reg1}" ), "paddsw" );"vpaddsw %{reg3}, %{reg2}, %{reg1}" ),"vpaddsw" );"vpaddsw %{reg2}, %{reg1}, %{reg1}" ),"avx_paddsw" );"psubusb %{reg2}, %{reg1}" ), "psubusb" );"vpsubusb %{reg3}, %{reg2}, %{reg1}" ),"vpsubusb" );"vpsubusb %{reg2}, %{reg1}, %{reg1}" ),"avx_psubusb" );"psubsb %{reg2}, %{reg1}" ), "psubsb" );"vpsubsb %{reg3}, %{reg2}, %{reg1}" ),"vpsubsb" );"vpsubsb %{reg2}, %{reg1}, %{reg1}" ),"avx_psubsb" );"psubusw %{reg2}, %{reg1}" ), "psubusw" );"vpsubusw %{reg3}, %{reg2}, %{reg1}" ),"vpsubusw" );"vpsubusw %{reg2}, %{reg1}, %{reg1}" ),"avx_psubusw" );"psubsw %{reg2}, %{reg1}" ), "psubsw" );"vpsubsw %{reg3}, %{reg2}, %{reg1}" ),"vpsubsw" );"vpsubsw %{reg2}, %{reg1}, %{reg1}" ),"avx_psubsw" );"cvtsi2ss %{reg2}, %{reg1}" ), "cvtsi2ss" );"cvtsi2sd %{reg2}, %{reg1}" ), "cvtsi2sd" );"cvtss2si %{reg2}, %{reg1}" ), "cvtss2si" );"cvtss2sd %{reg2}, %{reg1}" ), "cvtss2sd" );"cvtsd2si %{reg2}, %{reg1}" ), "cvtsd2si" );"cvttss2si %{reg2}, %{reg1}" ),"cvttss2si" );"cvttsd2si %{reg2}, %{reg1}" ),"cvttsd2si" );"cvtsd2ss %{reg2}, %{reg1}" ), "cvtsd2ss" );"cvtdq2ps %{reg2}, %{reg1}" ), "cvtdq2ps" );"vcvtdq2ps %{reg2}, %{reg1}" ),"vcvtdq2ps" );"vcvtdq2ps %{reg2}, %{reg1}" ),"avx_cvtdq2ps" );"cvtdq2pd %{reg2}, %{reg1}" ), "cvtdq2pd" );"comiss %{reg2}, %{reg1}" ), "comiss" );"comisd %{reg2}, %{reg1}" ), "comisd" );"ucomiss %{reg2}, %{reg1}" ), "ucomiss" );"ucomisd %{reg2}, %{reg1}" ), "ucomisd" );"sqrtss %{reg2}, %{reg1}" ), "sqrtss" );"sqrtsd %{reg2}, %{reg1}" ), "sqrtsd" );/*imm_bytes*/ 1U, "roundss ${imm}, %{reg2}, %{reg1}" ), "roundss" );/*imm_bytes*/ 1U, "roundsd ${imm}, %{reg2}, %{reg1}" ), "roundsd" );"xorps %{reg2}, %{reg1}" ), "xorps" );"vxorps %{reg3}, %{reg2}, %{reg1}" ),"vxorps" );"vxorps %{reg2}, %{reg1}, %{reg1}" ),"avx_xorps" );"xorpd %{reg2}, %{reg1}" ), "xorpd" );"vxorpd %{reg3}, %{reg2}, %{reg1}" ),"vxorpd" );"vxorpd %{reg2}, %{reg1}, %{reg1}" ),"avx_xorpd" );"pxor %{reg2}, %{reg1}" ), "pxor" );"vpxor %{reg3}, %{reg2}, %{reg1}" ), "vpxor" );"vpxor %{reg2}, %{reg1}, %{reg1}" ),"avx_pxor" );"andps %{reg2}, %{reg1}" ), "andps" );"vandps %{reg3}, %{reg2}, %{reg1}" ),"vandps" );"vandps %{reg2}, %{reg1}, %{reg1}" ),"avx_andps" );"andpd %{reg2}, %{reg1}" ), "andpd" );"vandpd %{reg3}, %{reg2}, %{reg1}" ),"vandpd" );"vandpd %{reg2}, %{reg1}, %{reg1}" ),"avx_andpd" );"pand %{reg2}, %{reg1}" ), "pand" );"vpand %{reg3}, %{reg2}, %{reg1}" ), "vpand" );"vpand %{reg2}, %{reg1}, %{reg1}" ),"avx_pand" );"andn %{reg3}, %{reg2}, %{reg1}" ), "andn" );"andnpd %{reg2}, %{reg1}" ), "andnpd" );"vandnpd %{reg3}, %{reg2}, %{reg1}" ),"vandnpd" );"vandnpd %{reg2}, %{reg1}, %{reg1}" ),"avx_andnpd" );"andnps %{reg2}, %{reg1}" ), "andnps" );"vandnps %{reg3}, %{reg2}, %{reg1}" ),"vandnps" );"vandnps %{reg2}, %{reg1}, %{reg1}" ),"avx_andnps" );"pandn %{reg2}, %{reg1}" ), "pandn" );"vpandn %{reg3}, %{reg2}, %{reg1}" ),"vpandn" );"vpandn %{reg2}, %{reg1}, %{reg1}" ),"avx_pandn" );"orps %{reg2}, %{reg1}" ), "orps" );"vorps %{reg3}, %{reg2}, %{reg1}" ), "vorps" );"vorps %{reg2}, %{reg1}, %{reg1}" ),"avx_orps" );"orpd %{reg2}, %{reg1}" ), "orpd" );"vorpd %{reg3}, %{reg2}, %{reg1}" ), "vorpd" );"vorpd %{reg2}, %{reg1}, %{reg1}" ),"avx_orpd" );"por %{reg2}, %{reg1}" ), "por" );"vpor %{reg3}, %{reg2}, %{reg1}" ), "vpor" );"vpor %{reg2}, %{reg1}, %{reg1}" ), "avx_por" );"pavgb %{reg2}, %{reg1}" ), "pavgb" );"vpavgb %{reg3}, %{reg2}, %{reg1}" ),"vpavgb" );"vpavgb %{reg2}, %{reg1}, %{reg1}" ),"avx_pavgb" );"pavgw %{reg2}, %{reg1}" ), "pavgw" );"vpavgw %{reg3}, %{reg2}, %{reg1}" ),"vpavgw" );"vpavgw %{reg2}, %{reg1}, %{reg1}" ),"avx_pavgw" );"psadbw %{reg2}, %{reg1}" ), "psadbw" );"pmaddwd %{reg2}, %{reg1}" ), "pmadwd" );"vpmaddwd %{reg3}, %{reg2}, %{reg1}" ),"vpmaddwd" );"vpmaddwd %{reg2}, %{reg1}, %{reg1}" ),"avx_pmaddwd" );"vfmadd213ss %{reg3}, %{reg2}, %{reg1}" ), "vfmadd213ss" );"vfmadd213sd %{reg3}, %{reg2}, %{reg1}" ), "vfmadd213sd" );"phaddw %{reg2}, %{reg1}" ), "phaddw" );"phaddd %{reg2}, %{reg1}" ), "phaddd" );"vphaddd %{reg3}, %{reg2}, %{reg1}" ),"vphaddd" );"vphaddd %{reg2}, %{reg1}, %{reg1}" ),"avx_phaddd" );"haddps %{reg2}, %{reg1}" ), "haddps" );"haddpd %{reg2}, %{reg1}" ), "haddpd" );"phsubw %{reg2}, %{reg1}" ), "phsubw" );"phsubd %{reg2}, %{reg1}" ), "phsubd" );"hsubps %{reg2}, %{reg1}" ), "hsubps" );"hsubpd %{reg2}, %{reg1}" ), "hsubpd" );"pminsb %{reg2}, %{reg1}" ), "pminsb" );"vpminsb %{reg3}, %{reg2}, %{reg1}" ),"vpminsb" );"vpminsb %{reg2}, %{reg1}, %{reg1}" ),"avx_pminsb" );"pmaxsb %{reg2}, %{reg1}" ), "pmaxsb" );"vpmaxsb %{reg3}, %{reg2}, %{reg1}" ),"vpmaxsb" );"vpmaxsb %{reg2}, %{reg1}, %{reg1}" ),"avx_pmaxsb" );"pminsw %{reg2}, %{reg1}" ), "pminsw" );"vpminsw %{reg3}, %{reg2}, %{reg1}" ),"vpminsw" );"vpminsw %{reg2}, %{reg1}, %{reg1}" ),"avx_pminsw" );"pmaxsw %{reg2}, %{reg1}" ), "pmaxsw" );"vpmaxsw %{reg3}, %{reg2}, %{reg1}" ),"vpmaxsw" );"vpmaxsw %{reg2}, %{reg1}, %{reg1}" ),"avx_pmaxsw" );"pminsd %{reg2}, %{reg1}" ), "pminsd" );"vpminsd %{reg3}, %{reg2}, %{reg1}" ),"vpminsd" );"vpminsd %{reg2}, %{reg1}, %{reg1}" ),"avx_pminsd" );"pmaxsd %{reg2}, %{reg1}" ), "pmaxsd" );"vpmaxsd %{reg3}, %{reg2}, %{reg1}" ),"vpmaxsd" );"vpmaxsd %{reg2}, %{reg1}, %{reg1}" ),"avx_pmaxsd" );"pminub %{reg2}, %{reg1}" ), "pminub" );"vpminub %{reg3}, %{reg2}, %{reg1}" ),"vpminub" );"vpminub %{reg2}, %{reg1}, %{reg1}" ),"avx_pminub" );"pmaxub %{reg2}, %{reg1}" ), "pmaxub" );"vpmaxub %{reg3}, %{reg2}, %{reg1}" ),"vpmaxub" );"vpmaxub %{reg2}, %{reg1}, %{reg1}" ),"avx_pmaxub" );"pminuw %{reg2}, %{reg1}" ), "pminuw" );"vpminuw %{reg3}, %{reg2}, %{reg1}" ),"vpminuw" );"vpminuw %{reg2}, %{reg1}, %{reg1}" ),"avx_pminuw" );"pmaxuw %{reg2}, %{reg1}" ), "pmaxuw" );"vpmaxuw %{reg3}, %{reg2}, %{reg1}" ),"vpmaxuw" );"vpmaxuw %{reg2}, %{reg1}, %{reg1}" ),"avx_pmaxuw" );"pminud %{reg2}, %{reg1}" ), "pminud" );"vpminud %{reg3}, %{reg2}, %{reg1}" ),"vpminud" );"vpminud %{reg2}, %{reg1}, %{reg1}" ),"avx_pminud" );"pmaxud %{reg2}, %{reg1}" ), "pmaxud" );"vpmaxud %{reg3}, %{reg2}, %{reg1}" ),"vpmaxud" );"vpmaxud %{reg2}, %{reg1}, %{reg1}" ),"avx_pmaxud" );"minps %{reg2}, %{reg1}" ), "minps" );"vminps %{reg3}, %{reg2}, %{reg1}" ),"vminps" );"vminps %{reg2}, %{reg1}, %{reg1}" ),"avx_minps" );"maxps %{reg2}, %{reg1}" ), "maxps" );"vmaxps %{reg3}, %{reg2}, %{reg1}" ),"vmaxps" );"vmaxps %{reg2}, %{reg1}, %{reg1}" ),"avx_maxps" );"minpd %{reg2}, %{reg1}" ), "minpd" );"vminpd %{reg3}, %{reg2}, %{reg1}" ),"vminpd" );"vminpd %{reg2}, %{reg1}, %{reg1}" ),"avx_minpd" );"maxpd %{reg2}, %{reg1}" ), "maxpd" );"vmaxpd %{reg3}, %{reg2}, %{reg1}" ),"vmaxpd" );"vmaxpd %{reg2}, %{reg1}, %{reg1}" ),"avx_maxpd" );"pcmpeqb %{reg2}, %{reg1}" ), "pcmpeqb" );"vpcmpeqb %{reg3}, %{reg2}, %{reg1}" ),"vpcmpeqb" );"vpcmpeqb %{reg2}, %{reg1}, %{reg1}" ),"avx_pcmpeqb" );"pcmpeqw %{reg2}, %{reg1}" ), "pcmpeqw" );"pcmpeqd %{reg2}, %{reg1}" ), "pcmpeqd" );"pcmpeqq %{reg2}, %{reg1}" ), "pcmpeqq" );"pcmpgtb %{reg2}, %{reg1}" ), "pcmpgtb" );"pcmpgtw %{reg2}, %{reg1}" ), "pcmpgtw" );"pcmpgtd %{reg2}, %{reg1}" ), "pcmpgtd" );"pcmpgtq %{reg2}, %{reg1}" ), "pcmpgtq" );"vpcmpgtq %{reg3}, %{reg2}, %{reg1}" ),"vpcmpgtq" );"vpcmpgtq %{reg2}, %{reg1}, %{reg1}" ),"avx_pcmpgtq" );/*imm_bytes*/ 1U, "shufps ${imm}, %{reg2}, %{reg1}" ), "shufps" );/*imm_bytes*/ 1U, "shufpd ${imm}, %{reg2}, %{reg1}" ), "shufpd" );/*imm_bytes*/ 1U, "pshufd ${imm}, %{reg2}, %{reg1}" ), "pshufd" );"punpcklbw %{reg2}, %{reg1}" ), "punpcklbw" );"vpunpcklbw %{reg3}, %{reg2}, %{reg1}" ), "vpunpcklbw" );"vpunpcklbw %{reg2}, %{reg1}, %{reg1}" ), "avx_punpcklbw" );"punpcklwd %{reg2}, %{reg1}" ), "punpcklwd" );"punpckldq %{reg2}, %{reg1}" ), "punpckldq" );"punpcklqdq %{reg2}, %{reg1}" ), "punpcklqdq" );"punpckhbw %{reg2}, %{reg1}" ), "punpckhbw" );"punpckhwd %{reg2}, %{reg1}" ), "punpckhwd" );"punpckhdq %{reg2}, %{reg1}" ), "punpckhdq" );"punpckhqdq %{reg2}, %{reg1}" ), "punpckhqdq" );4 u, "psllw ${imm}, %{reg}" ), "psllwi" );4 U, "vpsllw ${imm}, %{reg2}, %{reg1}" ),"vpsllw" );4 U, "vpsllw ${imm}, %{reg}, %{reg}" ),"avx_psllw" );5 u, "pslld ${imm}, %{reg}" ), "pslldi" );5 U, "vpslld ${imm}, %{reg2}, %{reg1}" ),"vpslld" );5 U, "vpslld ${imm}, %{reg}, %{reg}" ),"avx_pslld" );6 u, "psllq ${imm}, %{reg}" ), "psllqi" );6 U, "vpsllq ${imm}, %{reg2}, %{reg1}" ),"vpsllq" );6 U, "vpsllq ${imm}, %{reg}, %{reg}" ),"avx_psllq" );4 u, "psraw ${imm}, %{reg}" ), "psrawi" );4 U, "vpsraw ${imm}, %{reg2}, %{reg1}" ),"vpsraw" );4 U, "vpsraw ${imm}, %{reg}, %{reg}" ),"avx_psraw" );5 u, "psrad ${imm}, %{reg}" ), "psradi" );5 U, "vpsrad ${imm}, %{reg2}, %{reg1}" ),"vpsrad" );5 U, "vpsrad ${imm}, %{reg}, %{reg}" ),"avx_psrad" );4 u, "psrlw ${imm}, %{reg}" ), "psrlwi" );4 U, "vpsrlw ${imm}, %{reg2}, %{reg1}" ),"vpsrlw" );4 U, "vpsrlw ${imm}, %{reg}, %{reg}" ),"avx_psrlw" );5 u, "psrld ${imm}, %{reg}" ), "psrldi" );5 U, "vpsrld ${imm}, %{reg2}, %{reg1}" ),"vpsrld" );5 U, "vpsrld ${imm}, %{reg}, %{reg}" ),"avx_psrld" );6 u, "psrlq ${imm}, %{reg}" ), "psrlqi" );6 U, "vpsrlq ${imm}, %{reg2}, %{reg1}" ),"vpsrlq" );6 U, "vpsrlq ${imm}, %{reg}, %{reg}" ),"avx_psrlq" );1 ));2 ));"psrldq $1, %xmm0\n" "psrldq $2, %xmm15\n" , "psrldqi" );5 U, "vpermpd ${imm}, %{reg2}, %{reg1}" ),"vpermpd" );"vbroadcastss %{reg2}, %{reg1}" ),"vbroadcastss" );"vbroadcastsd %{reg2}, %{reg1}" ),"vbroadcastsd" );"vpbroadcastb %{reg2}, %{reg1}" ),"vpbroadcastb" );"vpbroadcastw %{reg2}, %{reg1}" ),"vpbroadcastw" );"vpbroadcastd %{reg2}, %{reg1}" ),"vpbroadcastd" );"vpbroadcastq %{reg2}, %{reg1}" ),"vpbroadcastq" );"pabsb %{reg2}, %{reg1}" ), "pabsb" );"vpabsb %{reg2}, %{reg1}" ), "vpabsb" );"vpabsb %{reg2}, %{reg1}" ), "avx_pabsb" );"pabsw %{reg2}, %{reg1}" ), "pabsw" );"vpabsw %{reg2}, %{reg1}" ), "vpabsw" );"vpabsw %{reg2}, %{reg1}" ), "avx_pabsw" );"pabsd %{reg2}, %{reg1}" ), "pabsd" );"vpabsd %{reg2}, %{reg1}" ), "vpabsd" );"vpabsd %{reg2}, %{reg1}" ), "avx_pabsd" );const char * expected = "vzeroupper\n" ;"vzeroupper" );// Disassembler tests "movaps {reg1}, {reg2}" ),"disass-movaps" );"vmovaps {reg1}, {reg2}" ),"disass-vmovaps" );"vmovaps {reg1}, {reg2}" ),"disass-avx_movaps" );// TODO: Disassembler tests cannot handle memory right now because of difference in // the format between ART disassembly and the combination generator // TEST_F(AssemblerX86_64AVXTest, DisassVMovapsStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAV(&x86_64::X86_64Assembler::vmovaps, // "vmovaps {mem}, {reg}"), "disass-vmovaps_s"); // } // TEST_F(AssemblerX86_64AVXTest, DisassMovapsStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAV(&x86_64::X86_64Assembler::movaps, // "vmovaps {mem}, {reg}"), "disass-avx_movaps_s"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovapsLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatVA(&x86_64::X86_64Assembler::vmovaps, // "vmovaps {reg}, {mem}"), "disass-vmovaps_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassMovapsLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatVA(&x86_64::X86_64Assembler::movaps, // "vmovaps {reg}, {mem}"), "disass-avx_movaps_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovupsStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAV(&x86_64::X86_64Assembler::vmovups, // "vmovups {mem}, {reg}"), "disass-vmovups_s"); // } // TEST_F(AssemblerX86_64AVXTest, DisassMovupsStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAV(&x86_64::X86_64Assembler::movups, // "vmovups {mem}, {reg}"), "disass-avx_movups_s"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovupsLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatVA(&x86_64::X86_64Assembler::vmovups, // "vmovups {reg}, {mem}"), "disass-vmovups_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassMovupsLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatVA(&x86_64::X86_64Assembler::movups, // "vmovups {reg}, {mem}"), "disass-avx_movups_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovssLoad){ // CustomDriverStr(VerifyDisassemblerDriver, RepeatFA(&x86_64::X86_64Assembler::vmovss, // "vmovss {reg}, {mem}"), "disass-vmovss_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovssStore){ // CustomDriverStr(VerifyDisassemblerDriver, RepeatAF(&x86_64::X86_64Assembler::vmovss, // "vmovss {mem}, {reg}"), "disass-vmovss_s"); // } "movss {reg1}, {reg2}" ),"disass-movss" );"vmovss {reg1}, {reg2}, {reg3}" ),"disass-vmovss" );"movapd {reg1}, {reg2}" ),"disass-movapd" );"vmovapd {reg1}, {reg2}" ),"disass-vmovapd" );// TEST_F(AssemblerX86_64AVXTest, DisassVMovapdStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAV(&x86_64::X86_64Assembler::vmovapd, // "vmovapd {mem}, {reg}"), "disass-vmovapd_s"); // } // TEST_F(AssemblerX86_64AVXTest, DisassMovapdStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAV(&x86_64::X86_64Assembler::movapd, // "vmovapd {mem}, {reg}"), "disass-avx_movapd_s"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovapdLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatVA(&x86_64::X86_64Assembler::vmovapd, // "vmovapd {reg}, {mem}"), "disass-vmovapd_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassMovapdLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatVA(&x86_64::X86_64Assembler::movapd, // "vmovapd {reg}, {mem}"), "disass-avx_movapd_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovupdStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAV(&x86_64::X86_64Assembler::vmovupd, // "vmovupd {mem}, {reg}"), "disass-vmovupd_s"); // } // TEST_F(AssemblerX86_64AVXTest, DisassMovupdStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAV(&x86_64::X86_64Assembler::movupd, // "vmovupd {mem}, {reg}"), "disass-avx_movupd_s"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovupdLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatVA(&x86_64::X86_64Assembler::vmovupd, // "vmovupd {reg}, {mem}"), "disass-vmovupd_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassMovupdLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatVA(&x86_64::X86_64Assembler::movupd, // "vmovupd {reg}, {mem}"), "disass-avx_movupd_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovsdLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatFA(&x86_64::X86_64Assembler::vmovsd, // "vmovsd {reg}, {mem}"), "disass-vmovsd_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovsdStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAF(&x86_64::X86_64Assembler::vmovsd, // "vmovsd {mem}, {reg}"), "disass-vmovsd_s"); // } "movsd {reg1}, {reg2}" ),"disass-movsd" );"vmovsd {reg1}, {reg2}, {reg3}" ),"disass-vmovsd" );"movdqa {reg1}, {reg2}" ),"disass-movdqa" );"vmovdqa {reg1}, {reg2}" ),"disass-vmovdqa" );// TEST_F(AssemblerX86_64AVXTest, DisassVMovdqaStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAV(&x86_64::X86_64Assembler::vmovdqa, // "vmovdqa {mem}, {reg}"), "disass-vmovdqa_s"); // } // TEST_F(AssemblerX86_64AVXTest, DisassMovdqaStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAV(&x86_64::X86_64Assembler::movdqa, // "vmovdqa {mem}, {reg}"), "disass-avx_movdqa_s"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovdqaLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatVA(&x86_64::X86_64Assembler::vmovdqa, // "vmovdqa {reg}, {mem}"), "disass-vmovdqa_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassMovdqaLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatVA(&x86_64::X86_64Assembler::movdqa, // "vmovdqa {reg}, {mem}"), "disass-avx_movdqa_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovdquStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAV(&x86_64::X86_64Assembler::vmovdqu, // "vmovdqu {mem}, {reg}"), "disass-vmovdqu_s"); // } // TEST_F(AssemblerX86_64AVXTest, DisassMovdquStore) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatAV(&x86_64::X86_64Assembler::movdqu, // "vmovdqu {mem}, {reg}"), "disass-avx_movdqu_s"); // } // TEST_F(AssemblerX86_64AVXTest, DisassVMovdquLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatVA(&x86_64::X86_64Assembler::vmovdqu, // "vmovdqu {reg}, {mem}"), "disass-vmovdqu_l"); // } // TEST_F(AssemblerX86_64AVXTest, DisassMovdquLoad) { // CustomDriverStr(VerifyDisassemblerDriver, RepeatVA(&x86_64::X86_64Assembler::movdqu, // "vmovdqu {reg}, {mem}"), "disass-avx_movdqu_l"); // } "movq {reg1}, {reg2}" ),"disass-movq.1" );"vmovq {reg1}, {reg2}" ),"disass-vmovq.1" );"movq {reg1}, {reg2}" ),"disass-movq.2" );"vmovq {reg1}, {reg2}" ),"disass-vmovq.2" );"movd {reg1}, {reg2}" ),"disass-movd.1" );"vmovd {reg1}, {reg2}" ),"disass-vmovd.1" );"movd {reg1}, {reg2}" ),"disass-movd.2" );"vmovd {reg1}, {reg2}" ),"disass-vmovd.2" );// TODO: Disassembler tests cannot handle commutative instructions like vaddps // Hence no disassembler tests for add, mul, avg, xor, or, and etc. // Also, some integral min/max operations are not treated as commutative because // it does not affect the encoding length and therefore they can be tested here. #define DISASSEMBLER_TEST_INSTR_WITH_3_VEC_REGS(inst) \## inst) { \#inst " {reg1}, {reg2}" ), \"disass-" #inst ); \## inst) { \## inst, "v" #inst " {reg1}, {reg2}, {reg3}" ), \"disass-v" #inst ); \// Cannot test commutative operations // DISASSEMBLER_TEST_INSTR_WITH_3_VEC_REGS(pminsw); // DISASSEMBLER_TEST_INSTR_WITH_3_VEC_REGS(pmaxsw); // Cannot test commutative operations // DISASSEMBLER_TEST_INSTR_WITH_3_VEC_REGS(pminub); // DISASSEMBLER_TEST_INSTR_WITH_3_VEC_REGS(pmaxub); "cvtdq2ps {reg1}, {reg2}" ),"disass-cvtdq2ps" );"vcvtdq2ps {reg1}, {reg2}" ),"disass-vcvtdq2ps" );"vfmadd213ss {reg1}, {reg2}, {reg3}" ),"disass-vfmadd213ss" );"vfmadd213sd {reg1}, {reg2}, {reg3}" ),"disass-vfmadd213sd" );#define DISASSEMBLER_TEST_SHIFT_INSTR(inst, bits) \## inst) { \#inst " {reg}, {imm}" ), \"disass-" #inst ); \## inst) { \## inst, bits, "v" #inst " {reg1}, {reg2}, {imm}" ), \"disass-v" #inst ); \4 U);5 U);6 U);4 U);5 U);4 U);5 U);6 U);"vbroadcastss {reg1}, {reg2}" ),"disass-vbroadcastss" );"vbroadcastsd {reg1}, {reg2}" ),"disass-vbroadcastsd" );"vpbroadcastb {reg1}, {reg2}" ),"disass-vpbroadcastb" );"vpbroadcastw {reg1}, {reg2}" ),"disass-vpbroadcastw" );"vpbroadcastd {reg1}, {reg2}" ),"disass-vpbroadcastd" );"vpbroadcastq {reg1}, {reg2}" ),"disass-vpbroadcastq" );"pabsb {reg1}, {reg2}" ),"disass-pabsb" );"vpabsb {reg1}, {reg2}" ),"disass-vpabsb" );"pabsw {reg1}, {reg2}" ),"disass-pabsw" );"vpabsw {reg1}, {reg2}" ),"disass-vpabsw" );"pabsd {reg1}, {reg2}" ),"disass-pabsd" );"vpabsd {reg1}, {reg2}" ),"disass-vpabsd" );const char * expected = "vzeroupper\n" ;"disass-vzeroupper" );"fincstp\n" ;"fsin\n" ;"fcos\n" ;"fptan\n" ;return str.str();"x87" );// no ext addressing "fildl {mem}" ), "filds" );// no ext addressing "fildll {mem}" ), "fildl" );// no ext addressing "fistpl {mem}" ), "fistps" );// no ext addressing "fistpll {mem}" ), "fistpl" );"call *%{reg}" ), "call" );"jmp *%{reg}" ), "jmp" );/*imm_bytes*/ 2U, "enter ${imm}, $0" , /*non-negative*/ true), "enter"); /*imm_bytes*/ 2U, "ret ${imm}" , /*non-negative*/ true), "ret"); test,"ret\n" ;"leave\n" ;return str.str();"retleave" );"blsmsk %{reg2}, %{reg1}" ), "blsmsk" );"blsi %{reg2}, %{reg1}" ), "blsi" );"blsr %{reg2}, %{reg1}" ), "blsr" );"bswap %{reg}" ), "bswapl" );"bswap %{reg}" ), "bswapq" );"bsfl %{reg2}, %{reg1}" ), "bsfl" );"bsfl {mem}, %{reg}" ), "bsfl_address" );"bsfq %{reg2}, %{reg1}" ), "bsfq" );"bsfq {mem}, %{reg}" ), "bsfq_address" );"bsrl %{reg2}, %{reg1}" ), "bsrl" );"bsrl {mem}, %{reg}" ), "bsrl_address" );"bsrq %{reg2}, %{reg1}" ), "bsrq" );"bsrq {mem}, %{reg}" ), "bsrq_address" );"popcntl %{reg2}, %{reg1}" ), "popcntl" );"popcntl {mem}, %{reg}" ), "popcntl_address" );"popcntq %{reg2}, %{reg1}" ), "popcntq" );"popcntq {mem}, %{reg}" ), "popcntq_address" );ess(12 ), false );ddress(12 ), false );ess(12 ), false );const char * expected ="cmovzl 0xc(%RDI,%RBX,4), %R10d\n" "cmovnzl 0xc(%R10,%RBX,4), %edi\n" "cmovzl 0xc(%RDI,%R9,4), %edi\n" ;"cmovl_address" );ess(12 ), true );ddress(12 ), true );ess(12 ), true );const char * expected ="cmovzq 0xc(%RDI,%RBX,4), %R10\n" "cmovnzq 0xc(%R10,%RBX,4), %rdi\n" "cmovzq 0xc(%RDI,%R9,4), %rdi\n" ;"cmovq_address" );4 ));const char * expected ="jrcxz 1f\n" "addl 4(%RSP),%EDI\n" "1:\n" ;"jrcxz" );// Test both forward and backward branches. 4 ));const char * expected ="1: je 2f\n" "jmp 2f\n" "jrcxz 2f\n" "addl 4(%RSP),%EDI\n" "2: jne 1b\n" "jmp 1b\n" ;"near_label" );// From Condition /* kOverflow = 0 , kNoOverflow = 1 , kBelow = 2 , kAboveEqual = 3 , kEqual = 4 , kNotEqual = 5 , kBelowEqual = 6 , kAbove = 7 , kSign = 8 , kNotSign = 9 , kParityEven = 10 , kParityOdd = 11 , kLess = 12 , kGreaterEqual = 13 , kLessEqual = 14 , 15 ] = { "o" , "no" , "b" , "ae" , "e" , "ne" , "be" , "a" , "s" , "ns" , "pe" , "po" ,"l" , "ge" , "le" };const x86_64::CpuRegister> registers = assembler_test->GetRegisters();for (auto && reg : registers) {for (size_t i = 0 ; i < 15 ; ++i) {static_cast <x86_64::Condition>(i), reg);"set" << suffixes[i] << " %" << assembler_test->GetQuaternaryRegisterName(reg) << "\n" ;return str.str();"setcc" );"movzbl %{reg2}, %{reg1}" ), "movzxb" );"movsbl %{reg2}, %{reg1}" ), "movsxb" );const char * expected = "repne scasw\n" ;"Repnescasw" );const char * expected = "repe cmpsw\n" ;"Repecmpsw" );const char * expected = "repe cmpsl\n" ;"Repecmpsl" );const char * expected = "repe cmpsq\n" ;"Repecmpsq" );const char * expected = "ud2\n" ;"Ud2" );/*imm_bytes*/ 1U, "cmpb ${imm}, {mem}" ), "cmpb" );/*imm_bytes*/ 1U, "testb ${imm}, {mem}" ), "testbi" );/*imm_bytes*/ 4U, "testl ${imm}, {mem}" ), "testli" );// Test that displacing an existing address is the same as constructing a new one with the same // initial displacement. // Test different displacements, including some 8-bit and 32-bit ones, so that changing // displacement may require a different addressing mode. static const std::vector<int32_t> displacements = {0 , 42 , -42 , 140 , -140 };// Test with all scale factors. static const std::vector<ScaleFactor> scales = {TIMES_1, TIMES_2, TIMES_4, TIMES_8};for (int32_t disp0 : displacements) { // initial displacement for (int32_t disp : displacements) { // extra displacement for (const x86_64::CpuRegister reg : GetRegisters()) {// Test non-SIB addressing. // Test SIB addressing with RBP base. if (reg.AsRegister() != x86_64::RSP) {for (ScaleFactor scale : scales) {// Test SIB addressing with different base. for (const x86_64::CpuRegister& index : GetRegisters()) {if (index.AsRegister() == x86_64::RSP) {continue ; // Skip RSP as it cannot be used with this address constructor. for (ScaleFactor scale : scales) {,// Test absolute and RIP-relative addressing. false ), disp),false ));true ), disp),true ));class JNIMacroAssemblerX86_64Test : public JNIMacroAssemblerTest<x86_64::X86_64JNIMacroAssembler> {public :using Base = JNIMacroAssemblerTest<x86_64::X86_64JNIMacroAssembler>;protected :return InstructionSet::kX86_64;private :static x86_64::X86_64ManagedRegister ManagedFromCpu(x86_64::Register r) {return x86_64::X86_64ManagedRegister::FromCpuRegister(r);static x86_64::X86_64ManagedRegister ManagedFromFpu(x86_64::FloatRegister r) {return x86_64::X86_64ManagedRegister::FromXmmRegister(r);assembler_test,// TODO: more interesting spill registers / entry spills. // Two random spill regs. const ManagedRegister raw_spill_regs[] = {const ManagedRegister> spill_regs(raw_spill_regs);10 * kStackAlignment;// Three random entry spills. 0 u), ManagedFromCpu(x86_64::RAX), /* size= */ 8u); 8 u), ManagedFromCpu(x86_64::RBX), /* size= */ 8u); 16 u), ManagedFromFpu(x86_64::XMM1), /* size= */ 8u); // Construct assembly text counterpart. // (1) Push the spill_regs. "pushq %rsi\n" ;"pushq %r10\n" ;// (2) Move down the stack pointer. static_cast <ssize_t>(frame_size) - (spill_regs.size() * 8 + 8 );"subq $" << displacement << ", %rsp\n" ;// (3) Store method reference. "movq %rdi, (%rsp)\n" ;// (4) Entry spills. "movq %rax, " << frame_size + 0 << "(%rsp)\n" ;"movq %rbx, " << frame_size + 8 << "(%rsp)\n" ;"movsd %xmm1, " << frame_size + 16 << "(%rsp)\n" ;return str.str();"BuildFrame" );* assembler_test,// TODO: more interesting spill registers / entry spills. // Two random spill regs. const ManagedRegister raw_spill_regs[] = {const ManagedRegister> spill_regs(raw_spill_regs);10 * kStackAlignment;/* may_suspend= */ true); // Construct assembly text counterpart. // (1) Move up the stack pointer. static_cast <ssize_t>(frame_size) - spill_regs.size() * 8 - 8 ;"addq $" << displacement << ", %rsp\n" ;// (2) Pop spill regs. "popq %r10\n" ;"popq %rsi\n" ;"ret\n" ;return str.str();"RemoveFrame" );0 U);10 * kStackAlignment);// Construct assembly text counterpart. // Increase by 0 is a NO-OP and ignored by the assembler. "addq $-" << kStackAlignment << ", %rsp\n" ;"addq $-" << 10 * kStackAlignment << ", %rsp\n" ;return str.str();"IncreaseFrame" );0 U);10 * kStackAlignment);// Construct assembly text counterpart. // Decrease by 0 is a NO-OP and ignored by the assembler. "addq $" << kStackAlignment << ", %rsp\n" ;"addq $" << 10 * kStackAlignment << ", %rsp\n" ;return str.str();"DecreaseFrame" );// namespace art
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