/* * Copyright © 2009 Nokia Corporation * * Permission is hereby granted , free of charge , to any person obtaining a * copy of this software and associated documentation files ( the " Software " ) , * to deal in the Software without restriction , including without limitation * the rights to use , copy , modify , merge , publish , distribute , sublicense , * and / or sell copies of the Software , and to permit persons to whom the * Software is furnished to do so , subject to the following conditions : * * The above copyright notice and this permission notice ( including the next * paragraph ) shall be included in all copies or substantial portions of the * Software . * * THE SOFTWARE IS PROVIDED " AS IS " , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR * IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY , * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM , DAMAGES OR OTHER * LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE , ARISING * FROM , OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE . * * Author : Siarhei Siamashka ( siarhei . siamashka @ nokia . com ) /* * This file contains a macro ( ' generate_composite_function ' ) which can * construct 2 D image processing functions , based on a common template . * Any combinations of source , destination and mask images with 8 bpp , * 16 bpp , 24 bpp , 32 bpp color formats are supported . * * This macro takes care of : * - handling of leading and trailing unaligned pixels * - doing most of the work related to L2 cache preload * - encourages the use of software pipelining for better instructions * scheduling * * The user of this macro has to provide some configuration parameters * ( bit depths for the images , prefetch distance , etc . ) and a set of * macros , which should implement basic code chunks responsible for * pixels processing . See ' pixman - arm - neon - asm . S ' file for the usage * examples . * * TODO : * - try overlapped pixel method ( from Ian Rickards ) when processing * exactly two blocks of pixels * - maybe add an option to do reverse scanline processing /* * Bit flags for ' generate_composite_function ' macro which are used * to tune generated functions behavior . 0 1 2 /* * Offset in stack where mask and source pointer / stride can be accessed * from ' init ' macro . This is useful for doing special handling for solid mask . 40 /* * Constants for selecting preferable prefetch type . 0 /* No prefetch at all */ 1 /* A simple, fixed-distance-ahead prefetch */ 2 /* Advanced fine-grained prefetch */ /* * Definitions of supplementary pixld / pixst macros ( for partial load / store of * pixel data ) . if \abits > 0 else if \abits > 0 else if \abits > 0 ), :\()\abits\()]!else )]!perand\()]!if \numbytes == 32 4 ), %(\basereg+5 ), \6 ), %(\basereg+7 ), \mem_operand, \abits16 2 ), %(\basereg+3 ), \mem_operand, \abits8 1 ), \mem_operand, \abits4 if !RESPECT_STRICT_ALIGNMENT || (\elem_size == 32 )32 , %(\basereg+0 ), 1 , \mem_operand, \abits16 16 , %(\basereg+0 ), 2 , \mem_operand, \abits16 , %(\basereg+0 ), 3 , \mem_operand, \abitselse 8 , %(\basereg+0 ), 4 , \mem_operand, \abits8 , %(\basereg+0 ), 5 , \mem_operand, \abits8 , %(\basereg+0 ), 6 , \mem_operand, \abits8 , %(\basereg+0 ), 7 , \mem_operand, \abits2 if !RESPECT_STRICT_ALIGNMENT || (\elem_size == 16 )16 , %(\basereg+0 ), 1 , \mem_operand, \abitselse 8 , %(\basereg+0 ), 2 , \mem_operand, \abits8 , %(\basereg+0 ), 3 , \mem_operand, \abits1 8 , %(\basereg+0 ), 1 , \mem_operand, \abitselse "unsupported size: \numbytes" 0 if \bpp > 0 if (\bpp == 32 ) && (\numpix == 8 ) && (DEINTERLEAVE_32BPP_ENABLED != 0 )8 , %(\basereg+4 ), %(\basereg+5 ), \6 ), %(\basereg+7 ), \mem_operand, \abits24 ) && (\numpix == 8 )8 , %(\basereg+3 ), %(\basereg+4 ), %(\basereg+5 ), \mem_operand24 ) && (\numpix == 4 )8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 4 , \mem_operand8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 5 , \mem_operand8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 6 , \mem_operand8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 7 , \mem_operand24 ) && (\numpix == 2 )8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 2 , \mem_operand8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 3 , \mem_operand24 ) && (\numpix == 1 )8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 1 , \mem_operandelse 8 ), vld1, %(\bpp), \basereg, \mem_operand, \abits0 if \bpp > 0 if (\bpp == 32 ) && (\numpix == 8 ) && (DEINTERLEAVE_32BPP_ENABLED != 0 )8 , %(\basereg+4 ), %(\basereg+5 ), \6 ), %(\basereg+7 ), \mem_operand, \abits24 ) && (\numpix == 8 )8 , %(\basereg+3 ), %(\basereg+4 ), %(\basereg+5 ), \mem_operand24 ) && (\numpix == 4 )8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 4 , \mem_operand8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 5 , \mem_operand8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 6 , \mem_operand8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 7 , \mem_operand24 ) && (\numpix == 2 )8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 2 , \mem_operand8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 3 , \mem_operand24 ) && (\numpix == 1 )8 , %(\basereg+0 ), %(\basereg+1 ), %(\basereg+2 ), 1 , \mem_operandelse 8 ), vst1, %(\bpp), \basereg, \mem_operand, \abitsif (\bpp * \numpix) <= 128 else 128 if (\bpp * \numpix) <= 128 else 128 /* * Pixel fetcher for nearest scaling ( needs TMP1 , TMP2 , VX , UNIT_X register * aliases to be defined ) if \elem_size == 16 #16 5 : subspl VX, VX, SRC_WIDTH_FIXED5 b#1 #16 5 : subspl VX, VX, SRC_WIDTH_FIXED5 b#1 16 {d\()\reg1\()[0 ]}, [TMP1, :16 ]#16 5 : subspl VX, VX, SRC_WIDTH_FIXED5 b#1 16 {d\()\reg1\()[1 ]}, [TMP2, :16 ]#16 5 : subspl VX, VX, SRC_WIDTH_FIXED5 b#1 16 {d\()\reg1\()[2 ]}, [TMP1, :16 ]16 {d\()\reg1\()[3 ]}, [TMP2, :16 ]32 #16 5 : subspl VX, VX, SRC_WIDTH_FIXED5 b#2 #16 5 : subspl VX, VX, SRC_WIDTH_FIXED5 b#2 32 {d\()\reg1\()[0 ]}, [TMP1, :32 ]32 {d\()\reg1\()[1 ]}, [TMP2, :32 ]else "unsupported" if 0 /* elem_size == 32 */ #16 #1 #2 #16 #2 32 {d\()\reg1\()[0 ]}, [TMP1, :32 ]#16 #1 #2 32 {d\()\reg2\()[0 ]}, [TMP2, :32 ]#16 #2 32 {d\()\reg1\()[1 ]}, [TMP1, :32 ]32 {d\()\reg2\()[1 ]}, [TMP2, :32 ]else if \elem_size == 16 #16 5 : subspl VX, VX, SRC_WIDTH_FIXED5 b#1 16 {d\()\reg1\()[\idx]}, [TMP1, :16 ]32 #16 5 : subspl VX, VX, SRC_WIDTH_FIXED5 b#2 32 {d\()\reg1\()[\idx]}, [TMP1, :32 ]if \numbytes == 32 4 ), %(\basereg+5 ), \mem_operand6 ), %(\basereg+7 ), \mem_operand4 )16 2 ), %(\basereg+3 ), \mem_operand8 1 ), \mem_operand4 if \elem_size == 32 0 ), 1 , \mem_operand16 0 ), 2 , \mem_operand0 ), 3 , \mem_operandelse 0 ), 4 , \mem_operand0 ), 5 , \mem_operand0 ), 6 , \mem_operand0 ), 7 , \mem_operand2 if \elem_size == 16 0 ), 1 , \mem_operandelse 0 ), 2 , \mem_operand0 ), 3 , \mem_operand1 0 ), 1 , \mem_operandelse "unsupported size: \numbytes" if \bpp > 0 8 ), %(\bpp), \basereg, \mem_operand8 d\()\reg1, d\()\reg28 d\()\reg1, d\()\reg2/* deinterleave B, G, R, A channels for eight 32bpp pixels in 4 registers */ if (\bpp == 32 ) && (DEINTERLEAVE_32BPP_ENABLED != 0 )0 ), %(\basereg+1 )2 ), %(\basereg+3 )1 ), %(\basereg+3 )0 ), %(\basereg+2 )/* interleave B, G, R, A channels for eight 32bpp pixels in 4 registers */ if (\bpp == 32 ) && (DEINTERLEAVE_32BPP_ENABLED != 0 )0 ), %(\basereg+2 )1 ), %(\basereg+3 )2 ), %(\basereg+3 )0 ), %(\basereg+1 )/* * This is a macro for implementing cache preload . The main idea is that * cache preload logic is mostly independent from the rest of pixels * processing code . It starts at the top left pixel and moves forward * across pixels and can jump across scanlines . Prefetch distance is * handled in an ' incremental ' way : it starts from 0 and advances to the * optimal distance over time . After reaching optimal prefetch distance , * it is kept constant . There are some checks which prevent prefetching * unneeded pixel lines below the image ( but it still can prefetch a bit * more data on the right side of the image - not a big issue and may * be actually helpful when rendering text glyphs ) . Additional trick is * the use of LDR instruction for prefetch instead of PLD when moving to * the next line , the point is that we have a high chance of getting TLB * miss in this case , and PLD would be useless . * * This sounds like it may introduce a noticeable overhead ( when working with * fully cached data ) . But in reality , due to having a separate pipeline and * instruction queue for NEON unit in ARM Cortex - A8 , normal ARM code can * execute simultaneously with NEON and be completely shadowed by it . Thus * we get no performance overhead at all ( * ) . This looks like a very nice * feature of Cortex - A8 , if used wisely . We don ' t have a hardware prefetcher , * but still can implement some rather advanced prefetch logic in software * for almost zero cost ! * * ( * ) The overhead of the prefetcher is visible when running some trivial * pixels processing like simple copy . Anyway , having prefetch is a must * when working with the graphics data . if (PREFETCH_TYPE_CURRENT == PREFETCH_TYPE_ADVANCED)if (src_bpp_shift >= 0 ) || (dst_r_bpp != 0 ) || (mask_bpp_shift >= 0 )if regs_shortage/* If we are short on regs, ORIG_W is kept on stack */ if \std_increment != 0 #\ std_increment#0 xF#\ boost_increment#1 if src_bpp_shift >= 0 #src_bpp_shift ]if dst_r_bpp != 0 #dst_bpp_shift ]if mask_bpp_shift >= 0 #mask_bpp_shift ]#0 x10if src_bpp_shift >= 0 #src_bpp_shift ]!if dst_r_bpp != 0 #dst_bpp_shift ]!if mask_bpp_shift >= 0 #mask_bpp_shift ]!if (PREFETCH_TYPE_CURRENT == PREFETCH_TYPE_SIMPLE)if src_bpp > 0 #( PREFETCH_DISTANCE_SIMPLE * src_bpp / 8 )]if dst_r_bpp > 0 #( PREFETCH_DISTANCE_SIMPLE * dst_r_bpp / 8 )]if mask_bpp > 0 #( PREFETCH_DISTANCE_SIMPLE * mask_bpp / 8 )]64 ), MASK/* * Macro which is used to process leading pixels until destination * pointer is properly aligned ( at 16 bytes boundary ) . When destination * buffer uses 16 bpp format , this is unnecessary , or even pointless . if dst_w_bpp != 24 #0 xF2 f1 , 2 , 4 , 8 , 16 if (dst_w_bpp <= (\lowbit * 8 )) && ((\lowbit * 8 ) < (pixblock_size * dst_w_bpp))if \lowbit < 16 /* we don't need more than 16-byte alignment */ #\ lowbit1 f8 / dst_w_bpp), src_bpp, src_basereg, SRC8 / dst_w_bpp), mask_bpp, mask_basereg, MASKif dst_r_bpp > 0 8 / dst_r_bpp), dst_r_bpp, dst_r_basereg, DST_Relse #\ lowbit#( \lowbit * 8 / dst_w_bpp)#( \lowbit * 8 / dst_w_bpp)1 :0 , pixblock_size1 , 2 , 4 , 8 , 16 if (dst_w_bpp <= (\lowbit * 8 )) && ((\lowbit * 8 ) < (pixblock_size * dst_w_bpp))if \lowbit < 16 /* we don't need more than 16-byte alignment */ #\ lowbit1 f8 / dst_w_bpp), dst_w_bpp, dst_w_basereg, DST_W1 :2 :/* * Special code for processing up to ( pixblock_size - 1 ) remaining * trailing pixels . As SIMD processing performs operation on * pixblock_size pixels , anything smaller than this has to be loaded * and stored in a special way . Loading and storing of pixel data is * performed in such a way that we fill some ' slots ' in the NEON * registers ( some slots naturally are unused ) , then perform compositing * operation as usual . In the end , the data is taken from these ' slots ' * and saved to memory . * * cache_preload_flag - allows to suppress prefetch if * set to 0 * dst_aligned_flag - selects whether destination buffer * is aligned #( pixblock_size - 1 )2 f16 , 8 , 4 , 2 , 1 if pixblock_size > \chunk_size#\ chunk_size1 fif \dst_aligned_flag != 0 else if \cache_preload_flag != 0 #\ chunk_size1 :if \cache_preload_flag != 0 0 , pixblock_size16 , 8 , 4 , 2 , 1 if pixblock_size > \chunk_size#\ chunk_size1 fif \dst_aligned_flag != 0 else 1 :2 :/* * Macro , which performs all the needed operations to switch to the next * scanline and start the next loop iteration unless all the scanlines * are already processed . if regs_shortage/* load W and H (width and height) from stack */ else #dst_bpp_shift if src_bpp != 0 #src_bpp_shift if mask_bpp != 0 #mask_bpp_shift if (dst_w_bpp != 24 )#dst_bpp_shift if (src_bpp != 24 ) && (src_bpp != 0 )#src_bpp_shift if (mask_bpp != 24 ) && (mask_bpp != 0 )#mask_bpp_shift #1 if regs_shortage#4 ] /* save updated height to stack */ /* * Registers are allocated in the following way by default : * d0 , d1 , d2 , d3 - reserved for loading source pixel data * d4 , d5 , d6 , d7 - reserved for loading destination pixel data * d24 , d25 , d26 , d27 - reserved for loading mask pixel data * d28 , d29 , d30 , d31 - final destination pixel data for writeback to memory 28 , \4 , \0 , \24 /* save all registers */ /* * Select prefetch type for this function . If prefetch distance is * set to 0 or one of the color formats is 24 bpp , SIMPLE prefetch * has to be used instead of ADVANCED . if \prefetch_distance == 0 24 ) || (\mask_bpp_ == 24 ) || (\dst_w_bpp_ == 24 ))/* * Make some macro arguments globally visible and accessible * from other macros 64 ), SRC/* * Assign symbolic names to registers /* width (is updated during processing) */ /* height (is updated during processing) */ /* destination buffer pointer for writes */ /* destination image stride */ /* source buffer pointer */ /* source image stride */ /* destination buffer pointer for reads */ /* mask pointer */ /* mask stride */ /* combined lines counter and prefetch */ /* distance increment counter */ /* pixel index in a scanline for current */ /* pretetch position */ /* pointer to source scanline start */ /* for prefetch purposes */ /* pointer to destination scanline start */ /* for prefetch purposes */ /* pointer to mask scanline start */ /* for prefetch purposes */ /* * Check whether we have enough registers for all the local variables . * If we don ' t have enough registers , original width and height are * kept on top of stack ( and ' regs_shortage ' variable is set to indicate * this for the rest of code ) . Even if there are enough registers , the * allocation scheme may be a bit different depending on whether source * or mask is not used . if (PREFETCH_TYPE_CURRENT < PREFETCH_TYPE_ADVANCED)/* saved original width */ /* temporary register */ 0 0 /* saved original width */ /* temporary register */ 0 0 /* saved original width */ /* temporary register */ 0 else /* saved original width */ /* temporary register */ 1 1 if src_bpp == 32 2 24 0 16 1 8 0 0 1 else "requested src bpp (src_bpp) is not supported" if mask_bpp == 32 2 24 0 8 0 0 1 else "requested mask bpp (mask_bpp) is not supported" if dst_w_bpp == 32 2 24 0 16 1 8 0 else "requested dst bpp (dst_w_bpp) is not supported" if (((\flags) & FLAG_DST_READWRITE) != 0 )else 0 if (((\flags) & FLAG_DEINTERLEAVE_32BPP) != 0 )1 else 0 if \prefetch_distance < 0 || \prefetch_distance > 15 "invalid prefetch distance (\prefetch_distance)" if src_bpp > 0 #40 ]if mask_bpp > 0 #48 ]#0 if src_bpp > 0 #44 ]if mask_bpp > 0 #52 ]if src_bpp == 24 #1 if mask_bpp == 24 #1 if dst_w_bpp == 24 #1 /* * Setup advanced prefetcher initial state /* PF_CTL = prefetch_distance | ((h - 1) << 4) */ #4 #( \prefetch_distance - 0 x10)if regs_shortage#1 if regs_shortage#4 ] /* save updated height to stack */ else 9 f#( pixblock_size * 2 )8 f/* * This is the start of the pipelined loop , which if optimized for * long scanlines 0 :/* Implement "head (tail_head) ... (tail_head) tail" loop pattern */ 64 ), DST_R64 ), MASK#pixblock_size 0 , pixblock_size#( pixblock_size * 2 )2 f1 :#pixblock_size 1 b2 :64 ), DST_W/* Process the remaining trailing pixels in the scanline */ 1 , 1 , \0 bif regs_shortage/* exit */ /* * This is the start of the loop , designed to process images with small width * ( less than pixblock_size * 2 pixels ) . In this case neither pipelining * nor prefetch are used . 8 :/* Process exactly pixblock_size pixels if needed */ #pixblock_size 1 f64 ), DST_R64 ), MASK64 ), DST_W1 :/* Process the remaining trailing pixels in the scanline */ 0 , 0 , \8 b9 :if regs_shortage/* exit */ /* * A simplified variant of function generation template for a single * scanline processing ( for implementing pixman combine functions ) 28 , \4 , \0 , \24 /* * Make some macro arguments globally visible and accessible * from other macros if \use_nearest_scaling != 0 /* * Assign symbolic names to registers for nearest scaling #( 24 + 4 )]if mask_bpp != 0 #( 24 + 8 )]else /* * Assign symbolic names to registers /* width (is updated during processing) */ /* destination buffer pointer for writes */ /* source buffer pointer */ /* destination buffer pointer for reads */ /* mask pointer */ if (((\flags) & FLAG_DST_READWRITE) != 0 )else 0 if (((\flags) & FLAG_DEINTERLEAVE_32BPP) != 0 )1 else 0 64 ), SRC#pixblock_size 8 f#pixblock_size 7 f/* Implement "head (tail_head) ... (tail_head) tail" loop pattern */ 64 ), DST_R64 ), MASK#pixblock_size 2 f1 :#pixblock_size 1 b2 :64 ), DST_W7 :/* Process the remaining trailing pixels in the scanline (dst aligned) */ 0 , 1 , \if \use_nearest_scaling != 0 /* exit */ else /* exit */ 8 :/* Process the remaining trailing pixels in the scanline (dst unaligned) */ 0 , 0 , \if \use_nearest_scaling != 0 /* exit */ else /* exit */ 0 , \x1 , \x/* Default prologue/epilogue, nothing special needs to be done */ /* * Prologue / epilogue variant which additionally saves / restores d8 - d15 * registers ( they need to be saved / restored by callee according to ABI ) . * This is required if the code needs to use all the NEON registers . /******************************************************************************/ /* * Conversion of 8 r5g6b6 pixels packed in 128 - bit register ( in ) * into a planar a8r8g8b8 format ( with a , r , g , b color components * stored into 64 - bit registers out_a , out_r , out_g , out_b respectively ) . * * Warning : the conversion is destructive and the original * value ( in ) is lost . #8 #3 #5 #255 #5 #6 #2 #8 #3 #5 #5 #6 #2 /* * Conversion from planar a8r8g8b8 format ( with a , r , g , b color components * in 64 - bit registers in_a , in_r , in_g , in_b respectively ) into 8 r5g6b6 * pixels packed in 128 - bit register ( out ) . Requires two temporary 128 - bit * registers ( tmp1 , tmp2 ) #8 #8 #8 #5 #11 /* * Conversion of four r5g6b5 pixels ( in ) to four x8r8g8b8 pixels * returned in ( out0 , out1 ) registers pair . Requires one temporary * 64 - bit register ( tmp ) . ' out1 ' and ' in ' may overlap , the original * value from ' in ' is lost #5 /* G top 6 bits */ #11 /* B top 5 bits */ #5 /* R is ready in top bits */ #6 /* G is ready in top bits */ #5 /* B is ready in top bits */ #8 /* R is in place */ #8 /* G & B is in place */ /* everything is in place */
Messung V0.5 in Prozent C=93 H=100 G=96
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