#ifdefined(__loongarch__) || defined (__loongarch64) #define SK_CPU_LOONGARCH 1 #endif
#ifdefined(__powerpc__) || defined (__powerpc64__) #define SK_CPU_PPC 1 #endif
/** * SK_CPU_SSE_LEVEL * * If defined, SK_CPU_SSE_LEVEL should be set to the highest supported level. * On non-intel CPU this should be undefined.
*/ #define SK_CPU_SSE_LEVEL_SSE1 10 #define SK_CPU_SSE_LEVEL_SSE2 20 #define SK_CPU_SSE_LEVEL_SSE3 30 #define SK_CPU_SSE_LEVEL_SSSE3 31 #define SK_CPU_SSE_LEVEL_SSE41 41 #define SK_CPU_SSE_LEVEL_SSE42 42 #define SK_CPU_SSE_LEVEL_AVX 51 #define SK_CPU_SSE_LEVEL_AVX2 52 #define SK_CPU_SSE_LEVEL_SKX 60
/** * SK_CPU_LSX_LEVEL * * If defined, SK_CPU_LSX_LEVEL should be set to the highest supported level. * On non-loongarch CPU this should be undefined.
*/ #define SK_CPU_LSX_LEVEL_LSX 70 #define SK_CPU_LSX_LEVEL_LASX 80
// TODO(kjlubick) clean up these checks
// Are we in GCC/Clang? #ifndef SK_CPU_SSE_LEVEL // These checks must be done in descending order to ensure we set the highest // available SSE level. #ifdefined(__AVX512F__) && defined(__AVX512DQ__) && defined(__AVX512CD__) && \ defined(__AVX512BW__) && defined(__AVX512VL__) #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SKX #elifdefined(__AVX2__) #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_AVX2 #elifdefined(__AVX__) #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_AVX #elifdefined(__SSE4_2__) #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE42 #elifdefined(__SSE4_1__) #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE41 #elifdefined(__SSSE3__) #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSSE3 #elifdefined(__SSE3__) #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE3 #elifdefined(__SSE2__) #define SK_CPU_SSE_LEVEL SK_CPU_SSE_LEVEL_SSE2 #endif #endif
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