// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // // * Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution. // * Neither the name of ARM Limited nor the names of its contributors may be // used to endorse or promote products derived from this software without // specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef VIXL_A64_CONSTANTS_A64_H_#define VIXL_A64_CONSTANTS_A64_H_#include <stdint.h>#include "jit/arm64/vixl/Globals-vixl.h" namespace vixl {// Supervisor Call (svc) specific support. // // The SVC instruction encodes an optional 16-bit immediate value. // The simulator understands the codes below. enum SVCSimulatorCodes {0 x10, // Transition to x86_64 C code. 0 x11, // Push the current SP on a special Simulator stack. 0 x12 // Pop from the special Simulator stack and compare to SP. const unsigned kNumberOfRegisters = 32 ;const unsigned kNumberOfVRegisters = 32 ;const unsigned kNumberOfFPRegisters = kNumberOfVRegisters;const unsigned kNumberOfZRegisters = kNumberOfVRegisters;const unsigned kNumberOfPRegisters = 16 ;// Callee saved registers are x21-x30(lr). const int kNumberOfCalleeSavedRegisters = 10 ;const int kFirstCalleeSavedRegisterIndex = 21 ;// Callee saved FP registers are d8-d15. Note that the high parts of v8-v15 are // still caller-saved. const int kNumberOfCalleeSavedFPRegisters = 8 ;const int kFirstCalleeSavedFPRegisterIndex = 8 ;// All predicated instructions accept at least p0-p7 as the governing predicate. const unsigned kNumberOfGoverningPRegisters = 8 ;// clang-format off #define AARCH64_P_REGISTER_CODE_LIST(R) \0 ) R(1 ) R(2 ) R(3 ) R(4 ) R(5 ) R(6 ) R(7 ) \8 ) R(9 ) R(10 ) R(11 ) R(12 ) R(13 ) R(14 ) R(15 )#define AARCH64_REGISTER_CODE_LIST(R) \0 ) R(1 ) R(2 ) R(3 ) R(4 ) R(5 ) R(6 ) R(7 ) \8 ) R(9 ) R(10 ) R(11 ) R(12 ) R(13 ) R(14 ) R(15 ) \16 ) R(17 ) R(18 ) R(19 ) R(20 ) R(21 ) R(22 ) R(23 ) \24 ) R(25 ) R(26 ) R(27 ) R(28 ) R(29 ) R(30 ) R(31 )#define REGISTER_CODE_LIST(R) \0 ) R(1 ) R(2 ) R(3 ) R(4 ) R(5 ) R(6 ) R(7 ) \8 ) R(9 ) R(10 ) R(11 ) R(12 ) R(13 ) R(14 ) R(15 ) \16 ) R(17 ) R(18 ) R(19 ) R(20 ) R(21 ) R(22 ) R(23 ) \24 ) R(25 ) R(26 ) R(27 ) R(28 ) R(29 ) R(30 ) R(31 )// SVE loads and stores use "w" instead of "s" for word-sized accesses, so the // mapping from the load/store variant to constants like k*RegSize is irregular. #define VIXL_SVE_LOAD_STORE_VARIANT_LIST(V) \// Sign-extending loads don't have double-word variants. #define VIXL_SVE_LOAD_STORE_SIGNED_VARIANT_LIST(V) \#define INSTRUCTION_FIELDS_LIST(V_) \/* Register fields */ \ 4 , 0 , ExtractBits) /* Destination register. */ \ 9 , 5 , ExtractBits) /* First source register. */ \ 20 , 16 , ExtractBits) /* Second source register. */ \ 19 , 16 , ExtractBits) /* Second source register (code 0-15). */ \ 14 , 10 , ExtractBits) /* Third source register. */ \ 4 , 0 , ExtractBits) /* Load/store register. */ \ 14 , 10 , ExtractBits) /* Load/store second register. */ \ 20 , 16 , ExtractBits) /* Exclusive access status. */ \ 3 , 0 , ExtractBits) /* Load/store register (p0-p7). */ \ 3 , 0 , ExtractBits) /* SVE destination predicate register. */ \ 8 , 5 , ExtractBits) /* SVE first source predicate register. */ \ 19 , 16 , ExtractBits) /* SVE second source predicate register.*/ \ 12 , 10 , ExtractBits) /* Governing predicate (p0-p7). */ \ /* Common bits */ \ 31 , 31 , ExtractBits) \29 , 29 , ExtractBits) \/* PC relative addressing */ \ 23 , 5 , ExtractSignedBits) \30 , 29 , ExtractBits) \/* Add/subtract/logical shift register */ \ 23 , 22 , ExtractBits) \15 , 10 , ExtractBits) \/* Add/subtract immediate */ \ 21 , 10 , ExtractBits) \22 , 22 , ExtractBits) \/* Add/substract extend */ \ 12 , 10 , ExtractBits) \15 , 13 , ExtractBits) \/* Move wide */ \ 20 , 5 , ExtractBits) \22 , 21 , ExtractBits) \/* Logical immediate, bitfield and extract */ \ 22 , 22 , ExtractBits) \21 , 16 , ExtractBits) \15 , 10 , ExtractBits) \21 , 16 , ExtractBits) \15 , 10 , ExtractBits) \/* Test and branch immediate */ \ 18 , 5 , ExtractSignedBits) \23 , 19 , ExtractBits) \31 , 31 , ExtractBits) \/* Conditionals */ \ 15 , 12 , ExtractBits) \3 , 0 , ExtractBits) \3 , 0 , ExtractBits) \20 , 16 , ExtractBits) \23 , 5 , ExtractSignedBits) \/* Floating point */ \ 23 , 22 , ExtractBits) \20 , 13 , ExtractBits) \15 , 10 , ExtractBits) \/* Load Store */ \ 20 , 12 , ExtractSignedBits) \21 , 10 , ExtractBits) \21 , 15 , ExtractSignedBits) \12 , 12 , ExtractBits) \23 , 22 , ExtractBits) \26 , 26 , ExtractBits) \31 , 30 , ExtractBits) \4 , 0 , ExtractBits) \4 , 3 , ExtractBits) \2 , 1 , ExtractBits) \0 , 0 , ExtractBits) \22 , 22 , ExtractSignedBits) \20 , 12 , ExtractBits) \/* Other immediates */ \ 25 , 0 , ExtractSignedBits) \23 , 5 , ExtractSignedBits) \23 , 5 , ExtractSignedBits) \20 , 5 , ExtractBits) \11 , 5 , ExtractBits) \11 , 10 , ExtractBits) \9 , 8 , ExtractBits) \15 , 0 , ExtractBits) \/* System (MRS, MSR, SYS) */ \ 20 , 5 , ExtractBits) \19 , 19 , ExtractBits) \18 , 5 , ExtractBits) \20 , 19 , ExtractBits) \18 , 16 , ExtractBits) \7 , 5 , ExtractBits) \15 , 12 , ExtractBits) \11 , 8 , ExtractBits) \20 , 15 , ExtractBits) \/* Load-/store-exclusive */ \ 22 , 22 , ExtractBits) \23 , 23 , ExtractBits) \15 , 15 , ExtractBits) \31 , 30 , ExtractBits) \21 , 21 , ExtractBits) \/* NEON generic fields */ \ 30 , 30 , ExtractBits) \23 , 22 , ExtractBits) \11 , 10 , ExtractBits) \12 , 12 , ExtractBits) \21 , 21 , ExtractBits) \20 , 20 , ExtractBits) \11 , 11 , ExtractBits) \14 , 11 , ExtractBits) \20 , 16 , ExtractBits) \14 , 11 , ExtractBits) \/* NEON extra fields */ \ 12 , 12 , ExtractBits) \12 , 11 , ExtractBits) \14 , 13 , ExtractBits) \/* NEON Modified Immediate fields */ \ 18 , 16 , ExtractBits) \9 , 5 , ExtractBits) \29 , 29 , ExtractBits) \15 , 12 , ExtractBits) \/* NEON Shift Immediate fields */ \ 22 , 16 , ExtractBits) \22 , 19 , ExtractBits) \18 , 16 , ExtractBits) \/* SVE generic fields */ \ 23 , 22 , ExtractBits) \10 , 5 , ExtractSignedBits) \12 , 5 , ExtractSignedBits) \12 , 5 , ExtractBits) \9 , 5 , ExtractBits) \/* SVE Bitwise Immediate bitfield */ \ 17 , 17 , ExtractBits) \16 , 11 , ExtractBits) \10 , 5 , ExtractBits) \3 , 0 , ExtractBits) \3 , 3 , ExtractBits)// clang-format on #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \/* NZCV */ \ 31 , 28 , ExtractBits) \31 , 31 , ExtractBits) \30 , 30 , ExtractBits) \29 , 29 , ExtractBits) \28 , 28 , ExtractBits) \/* FPCR */ \ 26 , 26 , ExtractBits) \25 , 25 , ExtractBits) \24 , 24 , ExtractBits) \// Fields offsets. #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \const int Name## _offset = LowBit; \const int Name## _width = HighBit - LowBit + 1 ; \const uint32_t Name## _mask = ((1 << Name## _width) - 1 ) << LowBit;#define NOTHING(A, B)#undef NOTHING#undef DECLARE_FIELDS_BITS// ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed // from ImmPCRelLo and ImmPCRelHi. const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask;// Disable `clang-format` for the `enum`s below. We care about the manual // formatting that `clang-format` would destroy. // clang-format off // Condition codes. enum Condition {0 , // Z set Equal. 1 , // Z clear Not equal. 2 , // C set Carry set. 3 , // C clear Carry clear. 4 , // N set Negative. 5 , // N clear Positive or zero. 6 , // V set Overflow. 7 , // V clear No overflow. 8 , // C set, Z clear Unsigned higher. 9 , // C clear or Z set Unsigned lower or same. 10 , // N == V Greater or equal. 11 , // N != V Less than. 12 , // Z clear, N == V Greater than. 13 , // Z set or N != V Less then or equal 14 , // Always. 15 , // Behaves as always/al. // Aliases. // C set Unsigned higher or same. // C clear Unsigned lower. // Floating-point additional condition code. // Unordered comparison. // SVE predicate condition aliases. // No active elements were true. // An active element was true. // The last element was not true. // The last element was true. struct ice_hw *hw, enum ice_block blk,// The first element was not true. // An active element was true but not the last element. // The last active element was true or no active elements were true. // CTERM termination condition not deleted. // CTERM termination condition deleted. // Mozilla expanded aliases. 0 , Zero = 0 ,1 , NonZero = 1 ,2 , CarrySet = 2 ,3 , CarryClear = 3 ,Signed = 4 ,5 ,6 ,7 ,8 ,9 ,10 ,11 ,12 ,13 ,14 ,15 inline Condition InvertCondition(Condition cond) {// Conditions al and nv behave identically, as "always true". They can't be // inverted, because there is no "always false" condition. return static_cast <Condition>(cond ^ 1 );enum FPTrapFlags {1 ,0 enum FlagsUpdate {1 ,0 enum StatusFlags {0 ,// Derive the flag combinations from the system register bit descriptions. // Floating-point comparison results. // SVE condition flags. // Mozilla change: Use sized enum to allow better packing for Shift uses. enum Shift : int8_t {1 ,0 x0,0 x1,0 x2,0 x3,0 x4// Mozilla change: Use sized enum to allow better packing for Extend uses. enum Extend : int8_t {1 ,0 ,1 ,2 ,3 ,4 ,5 ,6 ,7 enum SVEOffsetModifier {// Multiply (each element of) the offset by either the vector or predicate // length, according to the context. // Shift or extend modifiers (as in `Shift` or `Extend`). enum SystemHint {0 ,1 ,2 ,3 ,4 ,5 ,16 ,20 ,32 ,34 ,36 ,38 ,40 enum BranchTargetIdentifier {// These correspond to the values of the CRm:op2 fields in the equivalent HINT // instruction. 25 ,27 enum BarrierDomain {0 ,1 ,2 ,3 enum BarrierType {0 ,1 ,2 ,3 enum PrefetchOperation {0 x00,0 x01,0 x02,0 x03,0 x04,0 x05,0 x06,0 x07,0 x08,0 x09,0 x0a,0 x0b,0 x0c,0 x0d,0 x0e,0 x0f,0 x10,0 x11,0 x12,0 x13,0 x14,0 x15,0 x16,0 x17,0 x18,0 x19,0 x1a,0 x1b,0 x1c,0 x1d,0 x1e,0 x1f,bool IsNamedPrefetchOperation(int op) {return ((op >= PLDL1KEEP) && (op <= PLDL3STRM)) ||enum BType {// Set when executing any instruction on a guarded page, except those cases // listed below. 0 ,// Set when an indirect branch is taken from an unguarded page to a guarded // page, or from a guarded page to ip0 or ip1 (x16 or x17), eg "br ip0". 1 ,// Set when an indirect branch and link (call) is taken, eg. "blr x0". 2 ,// Set when an indirect branch is taken from a guarded page to a register // that is not ip0 or ip1 (x16 or x17), eg, "br x0". 3 template <int op0, int op1, int crn, int crm, int op2>class SystemRegisterEncoder {public :static const uint32_t value =// System/special register names. // This information is not encoded as one field but as the concatenation of // multiple fields (Op0, Op1, Crn, Crm, Op2). enum SystemRegister {3 , 3 , 4 , 2 , 0 >::value,3 , 3 , 4 , 4 , 0 >::value,3 , 3 , 2 , 4 , 0 >::value, // Random number. 3 , 3 , 2 , 4 , 1 >::value, // Reseeded random number. 3 , 3 , 0 , 0 , 7 >::valuetemplate <int op1, int crn, int crm, int op2>class CacheOpEncoder {public :static const uint32_t value =enum InstructionCacheOp : uint32_t {3 , 7 , 5 , 1 >::valueenum DataCacheOp : uint32_t {3 , 7 , 10 , 1 >::value,3 , 7 , 11 , 1 >::value,3 , 7 , 12 , 1 >::value,3 , 7 , 13 , 1 >::value,3 , 7 , 14 , 1 >::value,3 , 7 , 4 , 1 >::value,3 , 7 , 4 , 3 >::value,3 , 7 , 4 , 4 >::value,3 , 7 , 10 , 3 >::value,3 , 7 , 10 , 5 >::value,3 , 7 , 12 , 3 >::value,3 , 7 , 12 , 5 >::value,3 , 7 , 14 , 3 >::value,3 , 7 , 14 , 5 >::valueenum GCSOp {3 , 7 , 7 , 0 >::value,3 , 7 , 7 , 1 >::value,3 , 7 , 7 , 2 >::value,3 , 7 , 7 , 3 >::value// Some SVE instructions support a predicate constraint pattern. This is // interpreted as a VL-dependent value, and is typically used to initialise // predicates, or to otherwise limit the number of processed elements. enum SVEPredicateConstraint {// Select 2^N elements, for the largest possible N. 0 x0,// Each VL<N> selects exactly N elements if possible, or zero if N is greater // than the number of elements. Note that the encoding values for VL<N> are // not linearly related to N. 0 x1,0 x2,0 x3,0 x4,0 x5,0 x6,0 x7,0 x8,0 x9,0 xa,0 xb,0 xc,0 xd,// Each MUL<N> selects the largest multiple of N elements that the vector // length supports. Note that for D-sized lanes, this can be zero. 0 x1d,0 x1e,// Select all elements. 0 x1f// Instruction enumerations. // // These are the masks that define a class of instructions, and the list of // instructions within each class. Each enumeration has a Fixed, FMask and // Mask value. // // Fixed: The fixed bits in this instruction class. // FMask: The mask used to extract the fixed bits in the class. // Mask: The mask used to identify the instructions within a class. // // The enumerations can be used like this: // // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed); // switch(instr->Mask(PCRelAddressingMask)) { // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break; // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break; // default: printf("Unknown instruction\n"); // } // Generic fields. using GenericInstrField = uint32_t;0 x80000000,0 x00000000,0 x00C00000,0 x00C00000,0 x00000000,0 x00400000using NEONFormatField = uint32_t;0 x40C00000,0 x40000000,0 x00000000,0 x00400000,0 x00800000,0 x00C00000,0 x00C00000 | NEON_Qenum NEONFPFormatField : uint32_t {0 x40400000,enum NEONLSFormatField : uint32_t {0 x40000C00,0 x00000000,0 x00000400,0 x00000800,0 x00000C00,enum NEONScalarFormatField : uint32_t {0 x00C00000,0 x10000000,0 x00000000,0 x00400000,0 x00800000,0 x00C00000enum SVESizeField {0 x00C00000,0 x00000000,0 x00400000,0 x00800000,0 x00C00000// PC relative addressing. enum PCRelAddressingOp : uint32_t {0 x10000000,0 x1F000000,0 x9F000000,0 x00000000,0 x80000000// Add/sub (immediate, shifted and extended.) const int kSFOffset = 31 ;enum AddSubOp : uint32_t {0 x60000000,0 x20000000,0 x00000000,0 x40000000,#define ADD_SUB_OP_LIST(V) \enum AddSubImmediateOp : uint32_t {0 x11000000,0 x1F800000,0 xFF800000,#define ADD_SUB_IMMEDIATE(A) \## _w_imm = AddSubImmediateFixed | A, \## _x_imm = AddSubImmediateFixed | A | SixtyFourBits#undef ADD_SUB_IMMEDIATEenum AddSubShiftedOp : uint32_t {0 x0B000000,0 x1F200000,0 xFF200000,#define ADD_SUB_SHIFTED(A) \## _w_shift = AddSubShiftedFixed | A, \## _x_shift = AddSubShiftedFixed | A | SixtyFourBits#undef ADD_SUB_SHIFTEDenum AddSubExtendedOp : uint32_t {0 x0B200000,0 x1F200000,0 xFFE00000,#define ADD_SUB_EXTENDED(A) \## _w_ext = AddSubExtendedFixed | A, \## _x_ext = AddSubExtendedFixed | A | SixtyFourBits#undef ADD_SUB_EXTENDED// Add/sub with carry. enum AddSubWithCarryOp : uint32_t {0 x1A000000,0 x1FE00000,0 xFFE0FC00,// Rotate right into flags. enum RotateRightIntoFlagsOp : uint32_t {0 x1A000400,0 x1FE07C00,0 xFFE07C10,0 xA0000000// Evaluate into flags. enum EvaluateIntoFlagsOp : uint32_t {0 x1A000800,0 x1FE03C00,0 xFFE07C1F,0 x2000000D,0 x2000400D// Logical (immediate and shifted register). enum LogicalOp : uint32_t {0 x60200000,NOT = 0 x00200000,AND = 0 x00000000,AND | NOT ,0 x20000000,NOT ,0 x40000000,NOT ,0 x60000000,NOT // Logical immediate. enum LogicalImmediateOp : uint32_t {0 x12000000,0 x1F800000,0 xFF800000,AND ,AND | SixtyFourBits,// Logical shifted register. enum LogicalShiftedOp : uint32_t {0 x0A000000,0 x1F000000,0 xFF200000,AND ,AND | SixtyFourBits,// Move wide immediate. enum MoveWideImmediateOp : uint32_t {0 x12800000,0 x1F800000,0 xFF800000,0 x00000000,0 x40000000,0 x60000000,// Bitfield. const int kBitfieldNOffset = 22 ;enum BitfieldOp : uint32_t {0 x13000000,0 x1F800000,0 xFF800000,0 x00000000,0 x80000000,0 x20000000,0 xA0000000,0 x40000000,0 xC0000000,// Bitfield N field. // Extract. enum ExtractOp : uint32_t {0 x13800000,0 x1F800000,0 xFFA00000,0 x00000000,0 x80000000,// Unconditional branch. enum UnconditionalBranchOp : uint32_t {0 x14000000,0 x7C000000,0 xFC000000,0 x00000000,0 x80000000// Unconditional branch to register. enum UnconditionalBranchToRegisterOp : uint32_t {0 xD6000000,0 xFE000000,0 xFFFFFC00,0 x001F0000,0 x003F0000,0 x005F0000,0 x001F0800,0 x001F0C00,0 x003F0800,0 x003F0C00,0 x005F0800,0 x005F0C00,0 x011F0800,0 x011F0C00,0 x013F0800,0 x013F0C00// Compare and branch. enum CompareBranchOp : uint32_t {0 x34000000,0 x7E000000,0 xFF000000,0 x00000000,0 x80000000,0 x01000000,0 x81000000,// Test and branch. enum TestBranchOp : uint32_t {0 x36000000,0 x7E000000,0 x7F000000,0 x00000000,0 x01000000// Conditional branch. enum ConditionalBranchOp : uint32_t {0 x54000000,0 xFE000000,0 xFF000010,0 x00000000// System. // System instruction encoding is complicated because some instructions use op // and CR fields to encode parameters. To handle this cleanly, the system // instructions are split into more than one enum. enum SystemOp : uint32_t {0 xD5000000,0 xFFC00000enum SystemSysRegOp : uint32_t {0 xD5100000,0 xFFD00000,0 xFFF00000,0 x00200000,0 x00000000enum SystemPStateOp : uint32_t {0 xD5004000,0 xFFF8F000,0 xFFFFF0FF,0 x0000001F,0 x0000003F,0 x0000005Fenum SystemHintOp : uint32_t {0 xD503201F,0 xFFFFF01F,0 xFFFFF01F,0 x00000000enum SystemSysOp : uint32_t {0 xD5080000,0 xFFF80000,0 xFFF80000,0 x00000000,0 x00200000// Exception. enum ExceptionOp : uint32_t {0 xD4000000,0 xFF000000,0 xFFE0001F,0 x00400000,0 x00200000,0 x00000001,0 x00000002,0 x00000003,0 x00A00001,0 x00A00002,0 x00A00003,// Mozilla change: // Add pseudo-instruction for Wasm traps. 0 x00A00000,enum MemBarrierOp : uint32_t {0 xD503309F,0 xFFFFF09F,0 xFFFFF0FF,0 x00000000,0 x00000020,0 x00000040enum SystemExclusiveMonitorOp : uint32_t {0 xD503305F,0 xFFFFF0FF,0 xFFFFF0FF,enum SystemPAuthOp : uint32_t {0 xD503211F,0 xFFFFFD1F,0 xFFFFFFFF,0 x00000100,0 x00000140,0 x00000180,0 x000001C0,0 x00000300,0 x00000320,0 x00000340,0 x00000360,0 x00000380,0 x000003A0,0 x000003C0,0 x000003E0,// XPACLRI has the same fixed mask as System Hints and needs to be handled // differently. 0 xD50320FF// Any load or store. enum LoadStoreAnyOp : uint32_t {0 x0a000000,0 x08000000// Any load pair or store pair. enum LoadStorePairAnyOp : uint32_t {0 x3a000000,0 x28000000#define LOAD_STORE_PAIR_OP_LIST(V) \0 x00000000), \0 x00400000), \0 x40400000), \0 x80000000), \0 x80400000), \0 x04000000), \0 x04400000), \0 x44000000), \0 x44400000), \0 x84000000), \0 x84400000)// Load/store pair (post, pre and offset.) enum LoadStorePairOp : uint32_t {0 xC4400000,1 << 22 ,#define LOAD_STORE_PAIR(A, B, C) \## _## B = C#undef LOAD_STORE_PAIRenum LoadStorePairPostIndexOp : uint32_t {0 x28800000,0 x3B800000,0 xFFC00000,#define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \## _## B## _post = LoadStorePairPostIndexFixed | A## _## B#undef LOAD_STORE_PAIR_POST_INDEXenum LoadStorePairPreIndexOp : uint32_t {0 x29800000,0 x3B800000,0 xFFC00000,#define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \## _## B## _pre = LoadStorePairPreIndexFixed | A## _## B#undef LOAD_STORE_PAIR_PRE_INDEXenum LoadStorePairOffsetOp : uint32_t {0 x29000000,0 x3B800000,0 xFFC00000,#define LOAD_STORE_PAIR_OFFSET(A, B, C) \## _## B## _off = LoadStorePairOffsetFixed | A## _## B#undef LOAD_STORE_PAIR_OFFSETenum LoadStorePairNonTemporalOp : uint32_t {0 x28000000,0 x3B800000,0 xFFC00000,1 << 22 ,// Load with pointer authentication. enum LoadStorePACOp : uint32_t {0 xF8200400,0 xFF200400,0 xFFA00C00,0 x00000800,0 x00000000,0 x00800000,// Load literal. enum LoadLiteralOp : uint32_t {0 x18000000,0 x3B000000,0 xFF000000,0 x00000000,0 x40000000,0 x80000000,0 xC0000000,0 x04000000,0 x44000000,0 x84000000#define LOAD_STORE_OP_LIST(V) \0 x00000000), \0 x40000000), \0 x80000000), \0 xC0000000), \0 x00400000), \0 x40400000), \0 x80400000), \0 xC0400000), \0 x00800000), \0 x40800000), \0 x80800000), \0 x00C00000), \0 x40C00000), \0 x04000000), \0 x44000000), \0 x84000000), \0 xC4000000), \0 x04800000), \0 x04400000), \0 x44400000), \0 x84400000), \0 xC4400000), \0 x04C00000)// Load/store (post, pre, offset and unsigned.) enum LoadStoreOp : uint32_t {0 xC4C00000,0 x04000000,#define LOAD_STORE(A, B, C, D) \## B## _## C = D#undef LOAD_STORE0 xC0800000// Load/store unscaled offset. enum LoadStoreUnscaledOffsetOp : uint32_t {0 x38000000,0 x3B200C00,0 xFFE00C00,#define LOAD_STORE_UNSCALED(A, B, C, D) \## U## B## _## C = LoadStoreUnscaledOffsetFixed | D#undef LOAD_STORE_UNSCALED// Load/store post index. enum LoadStorePostIndex : uint32_t {0 x38000400,0 x3B200C00,0 xFFE00C00,#define LOAD_STORE_POST_INDEX(A, B, C, D) \## B## _## C## _post = LoadStorePostIndexFixed | D#undef LOAD_STORE_POST_INDEX// Load/store pre index. enum LoadStorePreIndex : uint32_t {0 x38000C00,0 x3B200C00,0 xFFE00C00,#define LOAD_STORE_PRE_INDEX(A, B, C, D) \## B## _## C## _pre = LoadStorePreIndexFixed | D#undef LOAD_STORE_PRE_INDEX// Load/store unsigned offset. enum LoadStoreUnsignedOffset : uint32_t {0 x39000000,0 x3B000000,0 xFFC00000,#define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \## B## _## C## _unsigned = LoadStoreUnsignedOffsetFixed | D#undef LOAD_STORE_UNSIGNED_OFFSET// Load/store register offset. enum LoadStoreRegisterOffset : uint32_t {0 x38200800,0 x3B200C00,0 xFFE00C00,#define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \## B## _## C## _reg = LoadStoreRegisterOffsetFixed | D#undef LOAD_STORE_REGISTER_OFFSETenum LoadStoreExclusive : uint32_t {0 x08000000,0 x3F000000,0 xFFE08000,0 x00000000,0 x40000000,0 x80000000,0 xC0000000,0 x00400000,0 x40400000,0 x80400000,0 xC0400000,0 x80200000,0 xC0200000,0 x80600000,0 xC0600000,0 x00008000,0 x40008000,0 x80008000,0 xC0008000,0 x00408000,0 x40408000,0 x80408000,0 xC0408000,0 x80208000,0 xC0208000,0 x80608000,0 xC0608000,0 x00808000,0 x40808000,0 x80808000,0 xC0808000,0 x00C08000,0 x40C08000,0 x80C08000,0 xC0C08000,// v8.1 Load/store LORegion ops 0 x00800000,0 x00C00000,0 x40800000,0 x40C00000,0 x80800000,0 x80C00000,0 xC0800000,0 xC0C00000,// v8.1 Load/store exclusive ops 0 x00400000,0 x00008000,0 x40000000,0 x80A00000,0 x00A00000,0 x40A00000,0 x00200000,// Load/store RCpc unscaled offset. enum LoadStoreRCpcUnscaledOffsetOp : uint32_t {0 x19000000,0 x3F200C00,0 xFFE00C00,0 x00000000,0 x00400000,0 x00800000,0 x00C00000,0 x40000000,0 x40400000,0 x40800000,0 x40C00000,0 x80000000,0 x80400000,0 x80800000,0 xC0000000,0 xC0400000#define ATOMIC_MEMORY_SIMPLE_OPC_LIST(V) \0 x00000000), \0 x00001000), \0 x00002000), \0 x00003000), \0 x00004000), \0 x00005000), \0 x00006000), \0 x00007000)// Atomic memory. enum AtomicMemoryOp : uint32_t {0 x38200000,0 x3B200C00,0 xFFE0FC00,0 x00008000,0 x00808000,0 x00408000,0 x00C08000,0 x40008000,0 x40808000,0 x40408000,0 x40C08000,0 x80008000,0 x80808000,0 x80408000,0 x80C08000,0 xC0008000,0 xC0808000,0 xC0408000,0 xC0C08000,0 x0080C000,0 x4080C000,0 x8080C000,0 xC080C000,0 x3B208C00,0 x00007000,#define ATOMIC_MEMORY_SIMPLE(N, OP) \## Op = OP, \## B = AtomicMemoryFixed | OP, \## AB = AtomicMemoryFixed | OP | 0 x00800000, \## LB = AtomicMemoryFixed | OP | 0 x00400000, \## ALB = AtomicMemoryFixed | OP | 0 x00C00000, \## H = AtomicMemoryFixed | OP | 0 x40000000, \## AH = AtomicMemoryFixed | OP | 0 x40800000, \## LH = AtomicMemoryFixed | OP | 0 x40400000, \## ALH = AtomicMemoryFixed | OP | 0 x40C00000, \## _w = AtomicMemoryFixed | OP | 0 x80000000, \## A_w = AtomicMemoryFixed | OP | 0 x80800000, \## L_w = AtomicMemoryFixed | OP | 0 x80400000, \## AL_w = AtomicMemoryFixed | OP | 0 x80C00000, \## _x = AtomicMemoryFixed | OP | 0 xC0000000, \## A_x = AtomicMemoryFixed | OP | 0 xC0800000, \## L_x = AtomicMemoryFixed | OP | 0 xC0400000, \## AL_x = AtomicMemoryFixed | OP | 0 xC0C00000#undef ATOMIC_MEMORY_SIMPLE// Conditional compare. enum ConditionalCompareOp : uint32_t {0 x60000000,0 x20000000,0 x60000000// Conditional compare register. enum ConditionalCompareRegisterOp : uint32_t {0 x1A400000,0 x1FE00800,0 xFFE00C10,// Conditional compare immediate. enum ConditionalCompareImmediateOp : uint32_t {0 x1A400800,0 x1FE00800,0 xFFE00C10,// Conditional select. enum ConditionalSelectOp : uint32_t {0 x1A800000,0 x1FE00000,0 xFFE00C00,0 x00000000,0 x80000000,0 x00000400,0 x80000400,0 x40000000,0 xC0000000,0 x40000400,0 xC0000400,// Data processing 1 source. enum DataProcessing1SourceOp : uint32_t {0 x5AC00000,0 x5FE00000,0 xFFFFFC00,0 x00000000,0 x00000400,0 x00000800,0 x00000C00,0 x00001000,0 x00001400,// Pointer authentication instructions in Armv8.3. 0 x80010000,0 x80010400,0 x80010800,0 x80010C00,0 x80011000,0 x80011400,0 x80011800,0 x80011C00,0 x80012000,0 x80012400,0 x80012800,0 x80012C00,0 x80013000,0 x80013400,0 x80013800,0 x80013C00,0 x80014000,0 x80014400,// Mozilla change: Add constants for CSSC instructions. 0 x0000'2000, 0 x0000'1C00, 0 x0000'1800, // Data processing 2 source. enum DataProcessing2SourceOp : uint32_t {0 x1AC00000,0 x5FE00000,0 xFFE0FC00,0 x00000800,0 x80000800,0 x00000C00,0 x80000C00,0 x00002000,0 x80002000,0 x00002400,0 x80002400,0 x00002800,0 x80002800,0 x00002C00,0 x80002C00,0 x00003000,0 x00004000,0 x00004400,0 x00004800,0 x00004C00,0 x00005000,0 x00005400,0 x00005800,0 x00005C00,// Mozilla change: Add constants for CSSC instructions. 0 x0000'6000, 0 x0000'6800, 0 x0000'6400, 0 x0000'6C00, // Data processing 3 source. enum DataProcessing3SourceOp : uint32_t {0 x1B000000,0 x1F000000,0 xFFE08000,0 x00000000,0 x80000000,0 x00008000,0 x80008000,0 x80200000,0 x80208000,0 x80400000,0 x80A00000,0 x80A08000,0 x80C00000// Floating point compare. enum FPCompareOp : uint32_t {0 x1E202000,0 x5F203C00,0 xFFE0FC1F,0 x00000000,0 x00000000,0 x00000000,0 x00000008,0 x00000008,0 x00000008,0 x00000010,0 x00000010,0 x00000010,0 x00000018,0 x00000018,0 x00000018,// Floating point conditional compare. enum FPConditionalCompareOp : uint32_t {0 x1E200400,0 x5F200C00,0 xFFE00C10,0 x00000000,0 x00000000,0 x00000000,0 x00000010,0 x00000010,0 x00000010,// Floating point conditional select. enum FPConditionalSelectOp : uint32_t {0 x1E200C00,0 x5F200C00,0 xFFE00C00,0 x00000000,0 x00000000,0 x00000000,// Floating point immediate. enum FPImmediateOp : uint32_t {0 x1E201000,0 x5F201C00,0 xFFE01C00,0 x00000000,0 x00000000,0 x00000000// Floating point data processing 1 source. enum FPDataProcessing1SourceOp : uint32_t {0 x1E204000,0 x5F207C00,0 xFFFFFC00,0 x00000000,0 x00000000,0 x00000000,Exception: Index 12 out of bounds for length 120 x00008000,0 x00008000,0 x00010000,0 x00010000,0 x00010000,0 x00018000,0 x00018000,0 x00018000,0 x00028000,0 x00020000,0 x00038000,0 x00038000,0 x00C20000,0 x00C28000,0 x00088000,0 x00088000,0 x00080000,0 x00080000,0 x00098000,0 x00098000,0 x00090000,0 x00090000,0 x00040000,0 x00040000,0 x00040000,0 x00048000,0 x00048000,0 x00048000,0 x00050000,0 x00050000,0 x00050000,0 x00058000,0 x00058000,0 x00058000,0 x00060000,0 x00070000,0 x00070000,0 x00070000,0 x00078000,0 x00078000,0 x00078000,// Floating point data processing 2 source. enum FPDataProcessing2SourceOp : uint32_t {0 x1E200800,0 x5F200C00,0 xFFE0FC00,0 x00000000,0 x00001000,0 x00002000,0 x00003000,0 x00004000,0 x00005000,0 00006000 java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 550 x00007000,0 x00008000,// Floating point data processing 3 source. enum FPDataProcessing3SourceOp : uint32_t {0 x1F000000,0 x5F000000,0 xFFE08000,0 x00C00000,0 x00C08000,0 x00E00000,0 x00E08000,0 x00000000,0 x00008000,0 x00200000,0 x00208000,0 x00400000,0 x00408000,0 x00600000,0 x00608000// Conversion between floating point and integer. enum FPIntegerConvertOp : uint32_t {0 x1E200000,0 x5F20FC00,0 xFFFFFC00,0 x00000000,0 x00010000,0 x00080000,for length 320 x00100000,0 x00110000,0 x00180000,0 x00190000,0 x00020000,0 x00030000,0 x00040000,0 x00050000,[0, 43) out of bounds for length 280 x00060000 | FP16,0 x00070000 | FP16,0 x00060000,0 x00070000,0 x008F0000,0 x008E0000,0 x001E0000// Conversion between fixed point and floating point. enum FPFixedPointConvertOp : uint32_t {0 x1E000000,0 x5F200000,0 xFFFF0000,0 x00180000,0 x00190000,0 x00020000,0 x00030000,// Crypto - two register SHA. enum Crypto2RegSHAOp : uint32_t {0 x5E280800,0 xFF3E0C00// Crypto - three register SHA. enum Crypto3RegSHAOp : uint32_t {0 x5E000000,0 xFF208C00// Crypto - AES. enum CryptoAESOp : uint32_t {0 x4E280800,0 xFF3E0C00// NEON instructions with two register operands. enum NEON2RegMiscOp : uint32_t {0 x0E200800,0 x9F3E0C00,0 xBF3FFC00,0 x20000000,0 x00000000,0 x20000000,0 x00001000,0 x00002000,0 x00003000,0 x00004000,0 x20004000,0 x00005000,0 x20005000,0 x00006000,0 x00007000,0 x20007000,0 x00008000,0 x20008000,0 x00009000,0 x20009000,0 x0000A000,0 x0000B000,0 x2000B000,0 x00012000,0 x20012000,0 x20013000,0 x00014000,0 x0001F000,// These instructions use only one bit of the size field. The other bit is // used to distinguish between instructions. 0 x00800000,0 x0080F000,0 x2080F000,0 x00016000,0 x20016000,0 x00017000,0 x2001E000,0 x0001E000,0 x2001F000,r length 290 x20018000,0 x00818000,0 x00019000,0 x20019000,0 x00819000,0 x20819000,0 x0001A000,0 x0081A000,0 x0001B000,0 x0081B000,0 x0001C000,0 x2081F000,0 x2081C000,0 x0081C000,0 x2081D000,0 x0081D000,0 x0080C000,0 x2080C000,0 x0080D000,0 x2080D000,0 x0080E000,// NEON instructions with two register operands (FP16). enum NEON2RegMiscFP16Op : uint32_t {0 x0E780800,0 x9F7E0C00,0 xBFFFFC00,0 x00018000,0 x00019000,0 x0001A000,0 x0001B000,0 x0001C000,0 x0001D000,0 x0080C000,0 x0080D000,0 x0080E000,0 x0080F000,0 x00818000,0 x00819000,0 x0081A000,0 x0081B000,0 x0081D000,0 x20018000,0 x20019000,0 x2001A000,0 x2001B000,0 x2001C000,0 x2001D000,0 x2080C000,0 x2080D000,0 x2080F000,0 x20819000,0 x2081A000,0 x2081B000,0 x2081D000,0 x2081F000// NEON instructions with three same-type operands. enum NEON3SameOp : uint32_t {0 x0E200400,0 x9F200400,0 xBF20FC00,0 x20000000,0 x00008000,0 x0000B800,0 x00000000,0 x00002000,0 x00001000,0 x00008800,0 x00003800,0 x00003000,0 x00008800,0 x00009000,0 x20009000,0 x00009800,0 x20009800,0 x00005000,0 x00004800,0 x00005800,0 x00004000,0 x00006000,0 x0000A000,0 x00006800,0 x0000A800,0 x00007000,0 x00007800,0 x00000800,0 x00002800,0 x00008000,0 x0000B000,0 x2000B000,// NEON floating point instructions with three same-type operands. 0 x0000C000,0 x0000C000,0 x00800000,0 x0000D000,0 x0080D000,0 x2000D800,0 x2000F800,0 x0000F000,0 x0000C000,0 x2000F000,0 x2000C000,0 x0080F000,0 x0080C000,0 x2080F000,0 x2080C000,0 x0000C800,0 x0080C800,0 x0000D800,0 x0000F800,0 x0080F800,0 x2080D000,0 x2000D000,0 x0000E000,0 x2000E000,0 x2080E000,0 x2000E800,0 x2080E800,// NEON logical instructions with three same-type operands. 0 x00001800,0 x0000F800,0 xBFE0FC00,0 x00000000,0 x00A00000,0 x00C00000,0 x20000000,0 x00400000,0 x20C00000,0 x20800000,0 x20400000,// FHM (FMLAL-like) instructions have an oddball encoding scheme under 3Same. 0 xBFE0FC00, // U size opcode 0 x0000E800, // 0 00 11101 0 x2000C800, // 1 00 11001 0 x0080E800, // 0 10 11101 0 x2080C800 // 1 10 11001 enum NEON3SameFP16 : uint32_t {0 x0E400400,0 x9F60C400,0 xBFE0FC00,0 x00000000,0 x00000800,0 x00001000,0 x00001800,0 x00002000,0 x00003000,0 x00003800,0 x00800000,0 x00800800,0 x00801000,0 x00803000,0 x00803800,0 x20000000,0 x20001000,0 x20001800,0 x20002000,0 x20002800,0 x20003000,0 x20003800,0 x20800000,0 x20801000,0 x20802000,0 x20802800,0 x20803000// 'Extra' NEON instructions with three same-type operands. enum NEON3SameExtraOp : uint32_t {0 x20000000,0 x9E208400,0 xBE20FC00,0 x00000800,0 x00001000,0 x00001000,/* v8.3 Complex Numbers */ 0 x2E00C400,// FCMLA fixes opcode<3:2>, and uses opcode<1:0> to encode <rotate>. 0 x00006000,// FCADD fixes opcode<3:2, 0>, and uses opcode<1> to encode <rotate>. 0 x00006800,0 x00002000// Other encodings under NEON3SameExtraFCFMask are UNALLOCATED. // NEON instructions with three different-type operands. enum NEON3DifferentOp : uint32_t {0 x0E200000,/* If the VSIG has at least 1 VSI then iterate through the list NEON3DifferentMask = 0 xFF20FC00 , NEON_ADDHN = NEON3DifferentFixed | 0 x00004000 , NEON_ADDHN2 = NEON_ADDHN | NEON_Q , NEON_PMULL = NEON3DifferentFixed | 0 x0000E000 , NEON_PMULL2 = NEON_PMULL | NEON_Q , = | 0 20004000 , NEON_RADDHN2 = NEON_RADDHN | NEON_Q , NEON_RSUBHN = NEON3DifferentFixed | 0 x20006000 , NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q , NEON_SABAL = java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 13 NEON_SABAL2 = NEON_SABAL | NEON_Q , NEON_SABDL = NEON3DifferentFixed | 0 x00007000 , NEON_SABDL2 = NEON_SABDL | NEON_Q , NEON_SADDL = NEON3DifferentFixed | 0 x00000000 , NEON_SADDL2 = NEON_SADDL | NEON_Q , NEON_SADDW = NEON3DifferentFixed | 0 x00001000 , NEON_SADDW2 = NEON_SADDW | NEON_Q , NEON_SMLAL = NEON3DifferentFixed | 0 x00008000 , NEON_SMLAL2 = NEON_SMLAL | NEON_Q , NEON_SMLSL = NEON3DifferentFixed | 0 x0000A000 , NEON_SMLSL2 = NEON_SMLSL | NEON_Q , NEON_SMULL = NEON3DifferentFixed | 0 x0000C000 , NEON_SMULL2 = NEON_SMULL | NEON_Q , NEON_SSUBL = NEON3DifferentFixed | 0 x00002000 , NEON_SSUBL2 = NEON_SSUBL | NEON_Q , NEON_SSUBW = NEON3DifferentFixed | 0 x00003000 , NEON_SSUBW2 = NEON_SSUBW | NEON_Q , NEON_SQDMLAL = NEON3DifferentFixed | 0 x00009000 , NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q , NEON_SQDMLSL = NEON3DifferentFixed | 0 x0000B000 , NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q , NEON_SQDMULL = NEON3DifferentFixed | 0 x0000D000 , NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q , NEON_SUBHN = NEON3DifferentFixed | 0 x00006000 , NEON_SUBHN2 = NEON_SUBHN | NEON_Q , NEON_UABAL = NEON_SABAL | NEON3SameUBit , NEON_UABAL2 = NEON_UABAL | NEON_Q , NEON_UABDL = java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 6 NEON_UABDL2 = NEON_UABDL | NEON_Q , NEON_UADDL = NEON_SADDL | NEON3SameUBit , NEON_UADDL2 = NEON_UADDL | NEON_Q , NEON_UADDW = NEON_SADDW | NEON3SameUBit , NEON_UADDW2 = NEON_UADDW | NEON_Q , NEON_UMLAL = NEON_SMLAL | NEON3SameUBit , NEON_UMLAL2 = NEON_UMLAL | NEON_Q , NEON_UMLSL = NEON_SMLSL | NEON3SameUBit , NEON_UMLSL2 = NEON_UMLSL | NEON_Q , NEON_UMULL = NEON_SMULL | NEON3SameUBit , NEON_UMULL2 = NEON_UMULL | NEON_Q , NEON_USUBL = NEON_SSUBL | NEON3SameUBit , NEON_USUBL2 = NEON_USUBL | NEON_Q , NEON_USUBW = NEON_SSUBW | NEON3SameUBit , NEON_USUBW2 = NEON_USUBW | NEON_Q } ; // NEON instructions operating across vectors. enum NEONAcrossLanesOp : uint32_t { NEONAcrossLanesFixed = 0 x0E300800 , NEONAcrossLanesFMask = 0 x9F3E0C00 , NEONAcrossLanesMask = 0 xBF3FFC00 , NEON_ADDV = NEONAcrossLanesFixed | 0 x0001B000 , NEON_SADDLV = NEONAcrossLanesFixed | 0 x00003000 , NEON_UADDLV = NEONAcrossLanesFixed | 0 x20003000 , NEON_SMAXV = NEONAcrossLanesFixed | 0 x0000A000 , NEON_SMINV = NEONAcrossLanesFixed | 0 x0001A000 , NEON_UMAXV = NEONAcrossLanesFixed | 0 x2000A000 , NEON_UMINV = NEONAcrossLanesFixed | 0 x2001A000 , NEONAcrossLanesFP16Fixed = NEONAcrossLanesFixed | 0 x0000C000 , NEONAcrossLanesFP16FMask = NEONAcrossLanesFMask | java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 NEONAcrossLanesFP16Mask = NEONAcrossLanesMask | 0 x20800000 , NEON_FMAXNMV_H = NEONAcrossLanesFP16Fixed | 0 x00000000 , NEON_FMAXV_H = NEONAcrossLanesFP16Fixed | 0 x00003000 , NEON_FMINNMV_H = NEONAcrossLanesFP16Fixed | 0 x00800000 , NEON_FMINV_H = NEONAcrossLanesFP16Fixed | 0 x00803000 , // NEON floating point across instructions. NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0 x2000C000 , NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0 x2000C000 , NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0 x20800000 , NEON_FMAXV = NEONAcrossLanesFPFixed | 0 x2000F000 , NEON_FMINV = NEONAcrossLanesFPFixed | 0 x2080F000 , NEON_FMAXNMV = NEON_FMAXNMV = NEONAcrossLanesFPFixed NEON_FMINNMV = NEONAcrossLanesFPFixed | 0 x2080C000 } ; // NEON instructions with indexed element operand. NEONByIndexedElementFixed = 0 x0F000000 , NEONByIndexedElementFMask = 0 x9F000400 , NEONByIndexedElementMask = 0 xBF00F400 , NEON_MUL_byelement = NEONByIndexedElementFixed | 0 x00008000 , NEON_MLA_byelement = NEONByIndexedElementFixed | 0 x20000000 , NEON_MLS_byelement = NEONByIndexedElementFixed | 0 x20004000 , NEON_SMULL_byelement = NEONByIndexedElementFixed | 0 x0000A000 , NEON_SMLAL_byelement = java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 0 java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 1 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0 x2000A000 , NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0 x20002000 , NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0 x20006000 , NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0 x0000B000 , NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0 x00003000 , NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0 x00007000 , NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0 x0000C000 , NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0 x0000D000 hdl profile handle indicating which profile to remove = NEONByIndexedElementFixed | 0 x0000E000 , NEON_SQRDMLAH_byelement = NEONByIndexedElementFixed | 0 x2000D000 , NEON_UDOT_byelement = NEONByIndexedElementFixed | 0 x2000E000 , NEON_SQRDMLSH_byelement = NEONByIndexedElementFixed | 0 x2000F000 , NEON_FMLA_H_byelement = NEONByIndexedElementFixed | 0 x00001000 , NEON_FMLS_H_byelement = NEONByIndexedElementFixed | 0 x00005000 , NEON_FMUL_H_byelement = NEONByIndexedElementFixed | 0 x00009000 , NEON_FMULX_H_byelement = NEONByIndexedElementFixed | 0 x20009000 , // Floating point instructions. NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0 x00800000 , NEONByIndexedElementFPMask = NEONByIndexedElementMask if ( ice_vsig_prof_id_count ( , blk , vsig ) = 1 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0 x00001000 , NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0 x00005000 , NEON_FMUL_byelement = NEONByIndexedElementFPFixed NEON_FMULX_byelement = NEONByIndexedElementFPFixed | status = ice_rem_prof_id ( hw , blk , p ) ; // FMLAL-like instructions. = x , opcode xx00 NEONByIndexedElementFPLongFixed = NEONByIndexedElementFixed | 0 x00800000 , NEONByIndexedElementFPLongFMask = NEONByIndexedElementFMask | java.lang.StringIndexOutOfBoundsException: Index 64 out of bounds for length 3 NEONByIndexedElementFPLongMask = 0 xBFC0F400 , NEON_FMLAL_H_byelement = NEONByIndexedElementFixed | 0 x00800000 , NEON_FMLAL2_H_byelement = NEONByIndexedElementFixed | 0 x20808000 , NEON_FMLSL_H_byelement = NEONByIndexedElementFixed | 0 x00804000 , NEON_FMLSL2_H_byelement = NEONByIndexedElementFixed | 0 x2080C000 , // Complex instruction(s). // This is necessary because the 'rot' encoding moves into the // NEONByIndex..Mask space. NEONByIndexedElementFPComplexMask = 0 xBF009400 , NEON_FCMLA_byelement = NEONByIndexedElementFixed | 0 x20001000 } ; // NEON register copy. enum NEONCopyOp : uint32_t { NEONCopyFixed = 0 java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 7 NEONCopyFMask = 0 x9FE08400 , NEONCopyMask = 0 x3FE08400 , NEONCopyInsElementMask = NEONCopyMask | 0 x40000000 , = | 0 53 NEONCopyDupElementMask = NEONCopyMask | 0 x20007800 , NEONCopyDupGeneralMask = NEONCopyDupElementMask , NEONCopyUmovMask = NEONCopyMask | 0 status , i , NEONCopySmovMask = NEONCopyMask | 0 NEON_INS_ELEMENT = NEONCopyFixed | 0 x60000000 , NEON_INS_GENERAL = NEONCopyFixed | 0 x40001800 , NEON_DUP_ELEMENT = NEONCopyFixed | 0 x00000000 , NEON_DUP_GENERAL = NEONCopyFixed | 0 x00000800 , NEON_SMOV = NEONCopyFixed | 0 x00002800 , NEON_UMOV = NEONCopyFixed | 0 x00003800 } ; // NEON extract. enum NEONExtractOp : uint32_t { NEONExtractFixed = 0 x2E000000 , NEONExtractFMask = 0 xBF208400 , java.lang.StringIndexOutOfBoundsException: Range [18, 17) out of bounds for length 32 NEON_EXT = NEONExtractFixed | 0 x00000000 } ; enum NEONLoadStoreMultiOp : uint32_t { NEONLoadStoreMultiL = 0 x00400000 , NEONLoadStoreMulti1_1v = 0 x00007000 , NEONLoadStoreMulti1_2v = 0 x0000A000 , NEONLoadStoreMulti1_3v = 0 x00006000 , NEONLoadStoreMulti1_4v = 0 x00002000 , NEONLoadStoreMulti2 = 0 x00008000 , NEONLoadStoreMulti3 = 0 x00004000 , NEONLoadStoreMulti4 = 0 x00000000 } ; // NEON load/store multiple structures. enum ice_rem_prof ( truct * ice_block blk , u64 id ) NEONLoadStoreMultiStructFixed = 0 x0C000000 , NEONLoadStoreMultiStructFMask = 0 xBFBF0000 , NEONLoadStoreMultiStructMask = 0 xBFFFF000 , NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed , NEONLoadStoreMultiStructLoad NEONLoadStoreMultiStructFixed | NEONLoadStoreMultiL , NEON_LD1_1v | , NEON_LD1_2v = | or length 70 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v } NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v , NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2 , NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3 , NEON_LD4 = NEONLoadStoreMultiStructLoad goto NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v , NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v , NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v , NEON_ST1_4v = | NEONLoadStoreMulti1_4v , NEON_ST2 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3 , NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4 } ; // NEON load/store multiple structures with post-index addressing. enum PostIndexOp : uint32_t { NEONLoadStoreMultiStructPostIndexFixed = 0 x0C800000 , = 0 java.lang.StringIndexOutOfBoundsException: Range [54, 53) out of bounds for length 54 NEONLoadStoreMultiStructPostIndexMask = 0 xBFE0F000 , NEONLoadStoreMultiStructPostIndex = h java.lang.StringIndexOutOfBoundsException: Range [17, 16) out of bounds for length 23 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex , NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex , NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex , NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex struct * chg NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex , NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex , NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex , NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex , NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex , NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex , NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex , NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex , NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex , if ( ! w - b [ . . map - prof_id ] ) { } ; enum NEONLoadStoreSingleOp : uint32_t { NEONLoadStoreSingle1 = 0 x00000000 , NEONLoadStoreSingle2 = 0 x00200000 , NEONLoadStoreSingle3 = 0 x00002000 , NEONLoadStoreSingle4 = 0 x00202000 , NEONLoadStoreSingleL = 0 x00400000 , NEONLoadStoreSingle_b = 0 x00000000 , NEONLoadStoreSingle_h = 0 x00004000 , NEONLoadStoreSingle_s = 0 x00008000 , NEONLoadStoreSingle_d = 0 x00008400 , NEONLoadStoreSingleAllLanes = 0 java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 0 NEONLoadStoreSingleLenMask = 0 x00202000 } ; // NEON load/store single structure. enum NEONLoadStoreSingleStructOp : uint32_t { NEONLoadStoreSingleStructFixed = 0 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 NEONLoadStoreSingleStructFMask = 0 xBF9F0000 , NEONLoadStoreSingleStructMask = 0 xBFFFE000 , NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed , NEONLoadStoreSingleStructLoad = NEONLoadStoreSingleStructFixed | NEONLoadStoreSingleL , NEONLoadStoreSingleStructLoad1 = NEONLoadStoreSingle1 | NEONLoadStoreSingleStructLoad , NEONLoadStoreSingleStructLoad2 = NEONLoadStoreSingle2 | NEONLoadStoreSingleStructLoad , NEONLoadStoreSingleStructLoad3 = NEONLoadStoreSingle3 | NEONLoadStoreSingleStructLoad , NEONLoadStoreSingleStructLoad4 = NEONLoadStoreSingle4 | NEONLoadStoreSingleStructLoad , NEONLoadStoreSingleStructStore1 = NEONLoadStoreSingle1 | NEONLoadStoreSingleStructFixed , NEONLoadStoreSingleStructStore2 = NEONLoadStoreSingle2 | java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 2 NEONLoadStoreSingleStructStore3 = NEONLoadStoreSingle3 | NEONLoadStoreSingleStructFixed , NEONLoadStoreSingleStructStore4 = NEONLoadStoreSingle4 | NEONLoadStoreSingleStructFixed , NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b , java.lang.StringIndexOutOfBoundsException: Range [14, 12) out of bounds for length 70 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s , NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d , java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 1 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b , NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h , NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s , NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d , NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b , NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h , NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s , NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d , java.lang.StringIndexOutOfBoundsException: Range [14, 13) out of bounds for length 38 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b , NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s , NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b , NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h , NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s , NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d , NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes , NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b , NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h , NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s , NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d , NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b , NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h , NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s , NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d , NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes , NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b , NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h , NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s , NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d } ; / / NEON load / store single structure with post - index addressing . enum NEONLoadStoreSingleStructPostIndexOp : uint32_t { NEONLoadStoreSingleStructPostIndexFixed = 0 x0D800000 , NEONLoadStoreSingleStructPostIndexFMask = 0 xBF800000 , NEONLoadStoreSingleStructPostIndexMask = 0 xBFE0E000 , NEONLoadStoreSingleStructPostIndex = 0 x00800000 NEON_LD1_b_post = NEON_LD1_b | the bottom of the TCAM table; otherwise NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex , NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex , NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex , NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex , NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex , NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex , NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex NEON_ST1_d_post = ADD ; NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex , NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex , NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex , NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex , NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex , NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex , NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex , NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex , NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex , NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex , NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex , NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex , NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex , NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex , NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex , NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex , NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex , NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex , NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex , NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex , NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex , NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex , NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex , NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex , NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex , NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex , NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex } ; / / NEON modified immediate . enum NEONModifiedImmediateOp : uint32_t { NEONModifiedImmediateFixed = 0 x0F000400 , NEONModifiedImmediateFMask = 0 x9FF80400 , NEONModifiedImmediateOpBit = 0 x20000000 , NEONModifiedImmediate_FMOV = NEONModifiedImmediateFixed | 0 x00000800 , NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0 x00000000 , NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0 x20000000 , NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0 x00001000 , NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0 x20001000 } ; / / NEON shift immediate . enum NEONShiftImmediateOp : uint32_t { NEONShiftImmediateFixed = 0 x0F000400 , NEONShiftImmediateFMask = 0 x9F800400 , NEONShiftImmediateMask = 0 xBF80FC00 , NEONShiftImmediateUBit = 0 x20000000 , NEON_SHL = NEONShiftImmediateFixed | 0 x00005000 , NEON_SSHLL = NEONShiftImmediateFixed | 0 x0000A000 , NEON_USHLL = NEONShiftImmediateFixed | 0 x2000A000 , NEON_SLI = NEONShiftImmediateFixed | 0 x20005000 , NEON_SRI = NEONShiftImmediateFixed | 0 x20004000 , NEON_SHRN = NEONShiftImmediateFixed | 0 x00008000 , NEON_RSHRN = NEONShiftImmediateFixed | 0 x00008800 , NEON_UQSHRN = NEONShiftImmediateFixed | 0 x20009000 , NEON_UQRSHRN = NEONShiftImmediateFixed | 0 x20009800 , NEON_SQSHRN = NEONShiftImmediateFixed | 0 x00009000 , NEON_SQRSHRN = NEONShiftImmediateFixed | 0 x00009800 , NEON_SQSHRUN = NEONShiftImmediateFixed | 0 x20008000 , NEON_SQRSHRUN = NEONShiftImmediateFixed | 0 x20008800 , NEON_SSHR = NEONShiftImmediateFixed | 0 x00000000 , NEON_SRSHR = NEONShiftImmediateFixed | 0 x00002000 , NEON_USHR = NEONShiftImmediateFixed | 0 x20000000 , NEON_URSHR = NEONShiftImmediateFixed | 0 x20002000 , NEON_SSRA = NEONShiftImmediateFixed | 0 x00001000 , NEON_SRSRA = NEONShiftImmediateFixed | 0 x00003000 , NEON_USRA = NEONShiftImmediateFixed | 0 x20001000 , NEON_URSRA = NEONShiftImmediateFixed | 0 x20003000 , NEON_SQSHLU = NEONShiftImmediateFixed | 0 x20006000 , NEON_SCVTF_imm = NEONShiftImmediateFixed | 0 x0000E000 , NEON_UCVTF_imm = NEONShiftImmediateFixed | 0 x2000E000 , NEON_FCVTZS_imm = _ set_bit ( t - > cam [ java.lang.StringIndexOutOfBoundsException: Range [40, 38) out of bounds for length 400 x2000F800,0 x00007000,0 x200070000 x0E000000,0 xBF208C00,0 x00001000,0 xBF20FC00,0 x00000000,0 x00002000,0 x00004000,0 x00006000,0 x0E000800,0 xBF208C00,0 x3F20FC00,0 x00001000,0 x00002000,0 x00003000,0 x00005000,0 x00006000,0 x000070000 x5E200800,0 xDF3E0C00,gth 57th 59ndex 51 out of bounds for length 3tion: Index 52 out of bounds for length 300 x00800000,0 x0081F000,0 x5E780800,0 xDF7E0C00,0 xFFFFFC00,0 x0081F000,0 x5E200400,0 xDF200400,of bounds for length 00 x0000C000,0 x0000C000,0 x00800000,0 x5E400400,0 xDF60C400,0 xFFE0FC00,0 x5E008400,0 xDF208400,0 xFF20FC00,0 x5E200000,0 xDF200C00,0 x5F000000,0 xDF000400,0 xFF00F400,xception: Range [36, 31) out of bounds for length 610 x00800000,0 x00800000,0 x5E000400,0 xDFE08400,0 xFFE0FC00,0 x5E300800,0 xFFB1F800,0 x0081B000,0 x0000C000,0 x0000D000,0 x0000F000,0 x0080C000,0 x0080F000,0 x2000C000,0 x2080C000,0 x2000D000,0 x2000F000,0 x2080F0000 x5F000400,0 xDF800400,0 xFF80FC00,Index 56 out of bounds for length 420 x84A00000,0 xFFA08000,0 xFFA0E000,setsFixed | 0 x00002000,sFixed | 0 x00004000,0 x85200000,0 xFFA08000,0 xFFA0E000,ed | 0 x00004000,ixed | 0 x000060000 x84000000,0 xFE208000,0 xFFA0E000,ed,0 x00002000,d | 0 x00004000,xed | 0 x00006000,[35, 34) out of bounds for length 35ixed | 0 x00802000,d | 0 x00804000,xed | 0 x00806000,d | 0 x01004000,xed | 0 x010060000 x84208000,0 xFE608000,0 xFFE0E000,0 x00002000,0 x00004000,0 x00006000,0 x00800000,0 x00802000,0 x00804000,0 x00806000,0 x01004000,0 x010060000 x84200000,0 xFFA08010,0 xFFA0E010,d,d | 0 x00002000,d | 0 x00004000,d | 0 x000060000 x8400E000,0 xFE60E010,0 xFFE0E010,0 x00800000,0 x01000000,0 x018000000 xE4608000,0 xFE60A000,0 xFFE0A000,0 0 0 xE4408000,0 xFE60A000,0 xFFE0A000,xed,xed | 0 x00800000,xed | 0 x010000000 xE460A000,0 xFE60E000,0 xFFE0E000,0 x00800000,0 x010000000 xC4200000,0 xFE208000,0 xFFA0E000,sFixed | 0 x00800000,etsFixed | 0 x00802000,Fixed | 0 x00804000,tsFixed | 0 x00806000,sFixed | 0 x01000000,etsFixed | 0 x01002000,Fixed | 0 x01004000,tsFixed | 0 x01006000,Fixed | 0 x01804000,tsFixed | 0 x018060000 xC4608000,0 xFE608000,0 xFFE0E000,0 x00800000,0 0 x00804000,0 x00806000,0 x01000000,0 0 x01004000,0 x01006000,) out of bounds for length 940 x018060000 xC4408000,0 xFE608000,0 xFFE0E000,xed | 0 x00002000,| 0 x00004000,ed | 0 x00006000,d | 0 x00800000,xed | 0 x00802000,| 0 x00804000,ed | 0 x00806000,d | 0 x01000000,xed | 0 x01002000,| 0 x01004000,ed | 0 x01006000,| 0 x01804000,ed | 0 x018060000 xC4000000,0 xFE208000,0 xFFA0E000,fsetsFixed,OffsetsFixed | 0 x00002000,setsFixed | 0 x00004000,ffsetsFixed | 0 x00006000,fsetsFixed | 0 x00800000,OffsetsFixed | 0 x00802000,setsFixed | 0 x00804000,ffsetsFixed | 0 x00806000,fsetsFixed | 0 x01000000,OffsetsFixed | 0 x01002000,setsFixed | 0 x01004000,ffsetsFixed | 0 x01006000,setsFixed | 0 x01804000,ffsetsFixed | 0 x018060000 xC4208000,0 xFE608000,0 xFFE0E000,0 x00002000,0 x00004000,0 x00006000,0 x00802000,0 x00804000,0 x00806000,0 x01000000,0 x01002000,0 x01004000,th 710 x01804000,0 x018060000 xC4608000,0 xFFE080100 xFFE0E010,,| 0 x00002000,| 0 x00004000,| 0 x000060000 xC4200000,0 xFFA08010,0 xFFA0E010,setsFixed,setsFixed | 0 x00002000,setsFixed | 0 x00004000,setsFixed | 0 x000060000 xC400E000,0 xFE60E010,0 xFFE0E010,0 x00800000,0 x01000000,0 x018000000 xE420A000,0 xFE60E000,0 xFFE0E000,0 x00800000,0 x01000000,0 x018000000 xE400A000,0 xFE60E000,0 xFFE0E000,ed,ed | 0 x00800000,ed | 0 x01000000,ed | 0 x018000000 xE4208000,0 xFE60A000,0 xFFE0A000,tsFixed | 0 x00800000,tsFixed | 0 x01000000,tsFixed | 0 x018000000 xE4008000,0 xFE60A000,0 xFFE0A000,ffsetsFixed,ffsetsFixed | 0 x00800000,ffsetsFixed | 0 x01000000,ffsetsFixed | 0 x018000000 xE440A000,0 xFE60E000,0 xFFE0E000,0 x00800000,0 x01000000,0 x018000000 x0420A000,0 xFF20F000,0 xFFE0F000,0 x00400000,0 x00800000,0 x00C000000 x04202000,0 xFF20E000,0 xFFE0FC00,0 x00001000,0 x00401000,0 x00801000,0 x00C010000 x05000000,0 xFF3C0000,0 xFFFC0000,0 x00400000,0 x008000000 x04180000,0 xFF38E000,0 xFF3FE000,0 x00010000,0 x00020000,0 x000300000 x04008000,0 xFF30E000,0 xFF3FE000,0 x00010000,0 x00030000,0 x000400000 x04108000,0 xFF38E000,0 xFF3FE000,0 x00010000,0 x00030000,0 x00040000,0 x00050000,0 x000700000 x04188000,0 xFF38E000,0 xFF3FE000,0 x00010000,0 x000300000 x04208000,0 xFF20E000,0 xFF20FC00,0 x00000400,0 x00000C00,0 x00001000,0 x00001400,0 x00001C000 x05C00000,0 xFFFC0000,0 xFFFC0000,0 x2539C000,0 xFF39C000,0 xFF3FE000,0 xFF3FFC00,0 xFF3FFC00,0 x05202000,0 xFF20FC00,0 xFF20FC00,0 x2538C000,0 xFF39C000,0 xFF3FC000,0 x05A18000,0 xFFBFE000,0 xFFBFE000,0 x05288000,0 xFF3EE000,0 xFF3FE000,0 x000100000 x0530A000,0 xFF3EE000,0 xFF3FE000,0 x000100000 x052A8000,0 xFF3EE000,0 xFF3FE000,0 x000100000 x25202000,0 xFF20FC0F,0 xFFA0FC1F,0 x00800000,0 x008000100 x0420BC00,0 xFF20FC00,0 xFFFFFC00,0 xA4006000,0 xFE00E000,0 xFFE0E000,0 x00200000,0 x00400000,0 x00600000,0 x00800000,0 x00A00000,0 x00C00000,0 x00E00000,0 x01000000,0 x01200000,0 x01400000,0 x01600000,0 x01800000,0 x01A00000,0 x01C00000,0 x01E000000 xA400A000,0 xFE10E000,0 xFFF0E000,0 x00200000,0 x00400000,0 x00600000,0 x00800000,0 x00A00000,0 x00C00000,0 x00E00000,0 x01000000,0 x01200000,0 x01400000,0 x01600000,0 x01800000,0 x01A00000,0 x01C00000,0 x01E000000 xA4004000,0 xFE00E000,0 xFFE0E000,0 x00200000,0 x00400000,0 x00600000,0 x00800000,0 x00A00000,0 x00C00000,0 x00E00000,0 x01000000,0 x01200000,0 x01400000,0 x01600000,0 x01800000,0 x01A00000,0 x01C00000,0 x01E000000 xA410A000,0 xFE10E000,0 xFFF0E000,0 x00200000,0 x00400000,0 x00600000,0 x00800000,0 x00A00000,0 x00C00000,0 x00E00000,0 x01000000,0 x01200000,0 x01400000,0 x01600000,0 x01800000,0 x01A00000,0 x01C00000,0 x01E000000 xA400E000,0 xFE70E000,0 xFFF0E000,0 x00800000,0 x01000000,0 x018000000 xA400C000,0 xFE60E000,0 xFFE0E000,0 x00800000,0 x01000000,0 x018000000 xE410E000,0 xFE70E000,0 xFFF0E000,0 x00800000,0 x01000000,0 x018000000 xE4006000,0 xFE60E000,0 xFFE0E000,0 x00800000,0 x01000000,0 x018000000 java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 00 x00002000,0 x00004000,th 71 470 x8400C000,0 xFE60E010,0 xFFE0E010,0 x00800000,0 x01000000,0 x018000000 xE400E000,0 xFE10E000,0 xFF90E000,0 x00800000,0 x01000000,0 x018000000 xE4004000,0 xFE00E000,0 xFF80E000,0 x00800000,0 x01000000,0 x018000000 x0510C000,0 xFF30E000,0 xFF30E000,0 x0528A000,0 xFF3FE000,0 xFF3FE000,0 x05100000,0 xFF308000,0 xFF308000,0 x05208000,0 java.lang.StringIndexOutOfBoundsException: Range [1, 66) out of bounds for length 590 xFF3FE000,0 x0420E000,0 xFF30F800,0 xFFF0FC00,0 x00400000,0 x00800000,0 x00C000000 x0520A000,0 xFF3EE000,0 xFF3FE000,0 x000100000 x05228000,0 xFF3EE000,0 xFF3FE000,0 x000100000 x252C9000,0 xFF3FFFFF,0 xFFFFFFFF,0 x25289000,0 xFF3FFE1F,0 xFFFFFE1F,0 x65182000,0 xFF38E000,0 xFF3FE000, 24: Range [26, 21) out of bounds for length 570 xFF20E000,0 xFF20FC00,0 x00000400,0 x00000800,0 x00000C00,0 x00001800,0 x00001C000 x65188000,0 xFF38E3C0,0 xFF3FE3C0,0 x00010000,0 x00020000,0 x00030000,0 x00040000,0 x00050000,0 x00060000,0 x000700000 x65008000,0 xFF30E000,0 xFF3FE000, status =ice_add_prof_id_vsighw ,hdl,false,0 x00010000,0 x00020000,0 x00030000,0 x00040000,0 x00050000,0 x00060000,0 x00070000,0 x00080000,0 x00090000,0 x000A0000,0 x000C0000,0 x000D00000 x65004000,0 xFF204000,0 xFF20E010,0 x00000010,0 x00002000,0 x00002010,0 x00008000,0 x00008010,0 x0000A0100 x65102000,0 xFF38E000,0 xFF3FE010,0 x00000010,0 x00010000,0 x00010010,0 x00020000,0 x000300000 x64008000,0 xFF3EE000,0 xFF3EE000,0 x64000000,0 xFF208000,0 xFF208000,0 x64201000,0 xFF20F000,0 xFFE0F000,0 x00800000,0 x00C000000 x6508A000,0 xFFFFE000,0 x00800000,0 x00810000,0 x00C00000,0 x00C10000,0 x00C20000,0 x00C300000 x6518A000,0 xFF38E000,0 ,0 x00420000,0 x00430000,0 ,0 x00450000,0 x00460000,0 x00470000,0 x00840000,0 x00850000,0 x00C00000,0 x00C10000,0 x00C40000,0 x00C50000,0 x00C60000,0 x00C700000 x0420B800,0 xFF20FC00,0 xFF3FFC00,0 x65002000,0 xFF38E000,0 xFF3FE000,0 x00040000,0 x00050000,0 x00060000,0 x000700000 x65200000,0 xFF200000,0 xFF20E000,0 x00002000,0 x00004000,0 x00006000,0 java.lang.StringIndexOutOfBoundsException: Range [47, 46) out of bounds for length 470 x0000A000,0 x0000C000,0 x0000E0000 x64200000,0 xFF20F800,0 xFFE0FC00,0 x00400000,0 x00000400,0 x00400000,0 x00800000,0 x00800400,0 x00C00000,0 x00C004000 x64202000,0 xFF20FC00,0 xFFE0FC00,0 x00400000,0 x00800000,0 x00C000000 x6500A000,0 xFF38E000,0 xFF3FE000,0 x00010000,0 x00020000,0 x00030000,0 x00040000,0 x00060000,0 x000700000 x65108000,0 xFF38FC00,0 xFF38FC00,0 x0420B000,0 xFF20F800,0 xFF20FC00,0 x650CA000,0 xFF3CE000,0 xFF3FE000,0 x000100000 x65083000,0 xFF38F000,0 xFF3FFC00,0 x00060000,0 x000700000 x25288000,0 xFF38F000,0 xFF3FFE00,0 x00000800,0 x00000C00,0 x00010000,s for length 140 x00020000,0 x00020800,0 x00020C00,0 x00030000,0 x00030800,0 x00030C00,0 x00040000,0 x00040800,0 x00050000,0 x000508000 x0430E000,0 xFF30F800,0 xFFF0FC00,0 x00000400,0 x00400000,0 x00400400,0 x00800000,0 x00800400,0 x00C00000,0 x00C004000 x0430C000,0 xFF30F800,0 xFFF0FC00,0 x00400000,0 x00400400,0 x00800000,th 620 x00C00000,0 java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 530 x04204000,0 xFF20F000,bounds for length 00 x00000400,0 x00000800,0 x00000C000 x05243800,0 xFF3FFC00,0 xFF3FFC00,0 x05343800,0 xFF3FFC00,0 xFF3FFC00,0 x2520C000,0 xFF38C000,0 xFF3FC000,0 x00010000,0 x00030000,0 x00040000,0 x00050000,0 x00060000,0 x000700000 x04000000,0 xFF38E000,0 xFF3FE000,0 x00010000,0 x000300000 x04200000,0 xFF20E000,0 xFF20FC00,0 x00000400,0 x00001000,0 x00001400,0 x00001800,0 x00001C000 x25200000,0 xFF20E000,0 xFF20EC10,0 x00000400,0 x00000410,0 x00000C00,0 x00000C100 x25000000,0 xFF204000,0 xFF20E010,0 x00000010,0 x00002000,0 x00002010,0 x00008000,0 x000080100 x24200000,0 xFF200000,0 x00000010,0 x00002000,0 x000020100 x24000000,0 xFF200000,0 xFF20E010,0 x00000010,0 x00002000,0 x00002010,0 ,0 x00004010,0 x00006000,0 x00006010,0 x00008000,or length 70 x0000A010,0 x0000C000,0 x0000C010,0 x0000E000,0 x0000E0100 x6510A000,0 xFF38E000,0 xFFFFE000,0 x00420000,0 x00430000,0 x00440000,0 x00450000,0 x00460000,0 x00470000,0 x00840000,0 x00850000,0 x00C00000,0 x00C10000,0 x00C40000,0 x00C50000,0 x00C60000,0 x00C700000 x04140000,0 xFF3CE000,0 xFF3FE000,0 x00010000,0 x00020000,0 x00030000enum SVEIntMinMaxDifference_PredicatedOp {0 xFF38E000,0 xFF3FE000,0 x00010000,0 x00020000,0 x00030000,0 x00040000,0 x00050000enum SVEIntMinMaxImm_UnpredicatedOp {0 x2528C000,0 xFF38C000,0 xFF3FE000,0 x00010000,0 x00020000,0 x00030000enum SVEIntMulAddPredicatedOp {0 x04004000,0 xFF204000,0 xFF20E000,0 x00002000,0 x00008000,0 x0000A000enum SVEIntMulAddUnpredicatedOp {0 x44000000,0 xFF208000,0 xFF20FC00,0 x00000400enum SVEIntMulImm_UnpredicatedOp {0 x2530C000,0 xFF38C000,0 xFF3FE000,enum SVEIntMulVectors_PredicatedOp {0 x04100000,0 xFF3CE000,0 xFF3FE000,0 x00020000,0 x00030000enum SVEMovprfxOp {0 x04002000,0 xFF20E000,0 xFF3EE000,0 x00100000enum SVEIntReductionOp {0 x04002000,0 xFF20E000,0 xFF3FE000,0 x00010000,0 x00080000,0 x00090000,0 x000A0000,0 x000B0000enum SVEIntReductionLogicalOp {0 x04182000,0 xFF38E000,0 xFF3FE000,0 x00180000,0 x00190000,0 x001A0000enum SVEIntUnaryArithmeticPredicatedOp {0 x0400A000,0 xFF20E000,0 xFF3FE000,0 x00100000,0 x00110000,0 x00120000,0 x00130000,0 x00140000,0 x00150000,0 x00160000,0 x00170000,0 x00180000,0 x00190000,0 x001A0000,0 x001B0000,0 x001C0000,0 x001D0000,0 x001E0000enum SVELoadAndBroadcastElementOp {0 x84408000,0 xFE408000,0 xFFC0E000,0 x00002000,0 x00004000,0 x00006000,0 x00800000,0 x00802000,0 x00804000,0 x00806000,0 x01000000,0 x01002000,0 x01004000,0 x01006000,0 x01800000,0 x01802000,0 x01804000,0 x01806000enum SVELoadAndBroadcastQuadword_ScalarPlusImmOp {0 xA4002000,0 xFE10E000,0 xFFF0E000,0 x00800000,0 x01000000,0 x01800000enum SVELoadAndBroadcastQuadword_ScalarPlusScalarOp {0 xA4000000,0 xFE00E000,0 xFFE0E000,0 x00800000,0 x01000000,0 x01800000enum SVELoadMultipleStructures_ScalarPlusImmOp {0 xA400E000,0 xFE10E000,0 xFFF0E000,0 x00200000,0 x00400000,0 x00600000,0 x00A00000,0 x00C00000,0 x00E00000,0 x01200000,0 x01400000,0 x01600000,0 x01A00000,0 x01C00000,0 x01E00000enum SVELoadMultipleStructures_ScalarPlusScalarOp {0 xA400C000,0 xFE00E000,0 xFFE0E000,0 x00200000,0 x00400000,0 x00600000,0 x00A00000,0 x00C00000,0 x00E00000,0 x01200000,0 x01400000,0 x01600000,0 x01A00000,0 x01C00000,0 x01E00000enum SVELoadPredicateRegisterOp {0 x85800000,0 xFFC0E010,0 xFFC0E010,enum SVELoadVectorRegisterOp {0 x85804000,0 xFFC0E000,0 xFFC0E000,enum SVEMulIndexOp {0 x44200000,0 xFF200000,0 xFFE0FC00,0 x00800000,0 x00800400,0 x00C00000,0 x00C00400enum SVEPartitionBreakConditionOp {0 x25104000,0 xFF3FC200,0 xFFFFC200,0 x00400000,0 x00800000,0 x00C00000enum SVEPermutePredicateElementsOp {0 x05204000,0 xFF30E210,0 xFF30FE10,0 x00000400,0 x00000800,0 x00000C00,0 x00001000,0 x00001400enum SVEPermuteVectorExtractOp {0 x05200000,0 xFF20E000,0 xFFE0E000,enum SVEPermuteVectorInterleavingOp {0 x05206000,0 xFF20E000,0 xFF20FC00,0 x00000400,0 x00000800,0 x00000C00,0 x00001000,0 x00001400enum SVEPredicateCountOp {0 x25208000,0 xFF38C000,0 xFF3FC200,enum SVEPredicateFirstActiveOp {0 x2518C000,0 xFF3FFE10,0 xFFFFFE10,0 x00400000enum SVEPredicateInitializeOp {0 x2518E000,0 xFF3EFC10,0 xFF3FFC10,0 x00010000,0 x00000000,enum SVEPredicateLogicalOp {0 x25004000,0 xFF30C000,0 xFFF0C210,0 x00400000,0 x00000010,0 x00000200,0 x00800000,0 x00800010,0 x00800210,0 x00800200,0 x00000210enum SVEPredicateNextActiveOp {0 x2519C400,0 xFF3FFE10,0 xFF3FFE10,enum SVEPredicateReadFromFFR_PredicatedOp {0 x2518F000,0 xFF3FFE10,0 xFFFFFE10,0 x00400000enum SVEPredicateReadFromFFR_UnpredicatedOp {0 x2519F000,0 xFF3FFFF0,0 xFFFFFFF0,enum SVEPredicateTestOp {0 x2510C000,0 xFF3FC210,0 xFFFFC21F,0 x00400000enum SVEPredicateZeroOp {0 x2518E400,0 xFF3FFFF0,0 xFFFFFFF0,enum SVEPropagateBreakOp {0 x2500C000,0 xFF30C000,0 xFFF0C210,0 x00000010,0 x00400000,0 x00400010enum SVEPropagateBreakToNextPartitionOp {0 x25184000,0 xFFBFC210,0 xFFFFC210,0 x00400000enum SVEReversePredicateElementsOp {0 x05344000,0 xFF3FFE10,0 xFF3FFE10,enum SVEReverseVectorElementsOp {0 x05383800,0 xFF3FFC00,0 xFF3FFC00,enum SVEReverseWithinElementsOp {0 x05248000,0 xFF3CE000,0 xFF3FE000,0 x00010000,0 x00020000,0 x00030000enum SVESaturatingIncDecRegisterByElementCountOp {0 x0420F000,0 xFF20F000,0 xFFF0FC00,0 x00000400,0 x00000800,0 x00000C00,0 x00100000,0 x00100400,0 x00100800,0 x00100C00,0 x00400000,0 x00400400,0 x00400800,0 x00400C00,0 x00500000,0 x00500400,0 x00500800,0 x00500C00,0 x00800000,0 x00800400,0 x00800800,0 x00800C00,0 x00900000,0 x00900400,0 x00900800,0 x00900C00,0 x00C00000,0 x00C00400,0 x00C00800,0 x00C00C00,0 x00D00000,0 x00D00400,0 x00D00800,0 x00D00C00enum SVESaturatingIncDecVectorByElementCountOp {0 x0420C000,0 xFF30F000,0 xFFF0FC00,0 x00400000,0 x00400400,0 x00400800,0 x00400C00,0 x00800000,0 x00800400,0 x00800800,0 x00800C00,0 x00C00000,0 x00C00400,0 x00C00800,0 x00C00C00enum SVEStackFrameAdjustmentOp {0 x04205000,0 xFFA0F800,0 xFFE0F800,0 x00400000enum SVEStackFrameSizeOp {0 x04BF5000,0 xFFFFF800,0 xFFFFF800,enum SVEStoreMultipleStructures_ScalarPlusImmOp {0 xE410E000,0 xFE10E000,0 xFFF0E000,0 x00200000,0 x00400000,0 x00600000,0 x00A00000,0 x00C00000,0 x00E00000,0 x01200000,0 x01400000,0 x01600000,0 x01A00000,0 x01C00000,0 x01E00000enum SVEStoreMultipleStructures_ScalarPlusScalarOp {0 xE4006000,0 xFE00E000,0 xFFE0E000,0 x00200000,0 x00400000,0 x00600000,0 x00A00000,0 x00C00000,0 x00E00000,0 x01200000,0 x01400000,0 x01600000,0 x01A00000,0 x01C00000,0 x01E00000enum SVEStorePredicateRegisterOp {0 xE5800000,0 xFFC0E010,0 xFFC0E010,enum SVEStoreVectorRegisterOp {0 xE5804000,0 xFFC0E000,0 xFFC0E000,enum SVETableLookupOp {0 x05203000,0 xFF20FC00,0 xFF20FC00,enum SVEUnpackPredicateElementsOp {0 x05304000,0 xFFFEFE10,0 xFFFFFE10,0 x00010000enum SVEUnpackVectorElementsOp {0 x05303800,0 xFF3CFC00,0 xFF3FFC00,0 x00010000,0 x00020000,0 x00030000enum SVEVectorSelectOp {0 x0520C000,0 xFF20C000,0 xFF20C000,enum SVEVectorSpliceOp {0 x052C8000,0 xFF3FE000,0 xFF3FE000,enum ReservedOp : uint32_t {0 x00000000,0 x1E000000,0 xFFFF0000,0 x00000000// Unimplemented and unallocated instructions. These are defined to make fixed // bit assertion easier. enum UnimplementedOp : uint32_t {0 x00000000,0 x00000000enum UnallocatedOp : uint32_t {0 x00000000,0 x00000000// Mozilla change: Add enum for CSSC max-min immediate instructions enum MaxMinImmediateOp : uint32_t {0 x11C00000,0 x1FC00000,0 xFFFC0000,0 x0000'0000, 0 x0008'0000, 0 x0004'0000, 0 x000c'0000, // Re-enable `clang-format` after the `enum`s. // clang-format on // Mozilla change: // // Instruction bit pattern for an undefined instruction, that will trigger a // SIGILL at runtime. // // A couple of strategies we can use here. There are no unencoded // instructions in the instruction set that are guaranteed to remain that // way. However there are some currently (as of 2018) unencoded // instructions that are good candidates. // // Ideally, unencoded instructions should be non-destructive to the register // state, and should be unencoded at all exception levels. // // At the trap the pc will hold the address of the offending instruction. // // Some candidates for unencoded instructions: // // 0xd4a00000 (essentially dcps0, a good one since it is nonsensical and may // remain unencoded in the future for that reason) // 0x33000000 (bfm variant) // 0xd67f0000 (br variant) // 0x5ac00c00 (rbit variant) // // This instruction is "dcps0", also has 16-bit payload if needed. static constexpr uint32_t UNDEFINED_INST_PATTERN = DCPS0;// namespace vixl #endif // VIXL_A64_CONSTANTS_A64_H_
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