ret = ath10k_sdio_func0_cmd52_wr_byte(func->card,
CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS,
byte);
/* give us some time to enable, in ms */
func->enable_timeout = 100;
ret = sdio_set_block_size(func, ar_sdio->mbox_info.block_size); if (ret) {
ath10k_warn(ar, "failed to set sdio block size to %d: %d\n",
ar_sdio->mbox_info.block_size, ret); goto out;
}
/* For some reason toio() doesn't have const for the buffer, need * an ugly hack to workaround that.
*/
ret = sdio_memcpy_toio(func, addr, (void *)buf, len); if (ret) {
ath10k_warn(ar, "failed to write to address 0x%x: %d\n",
addr, ret); goto out;
}
for (i = 0; i < ar_sdio->n_rx_pkts; i++) {
lookaheads_local = lookaheads;
n_lookahead_local = n_lookahead;
id = ((struct ath10k_htc_hdr *)
&lookaheads[lookahead_idx++])->eid;
if (id >= ATH10K_HTC_EP_COUNT) {
ath10k_warn(ar, "invalid endpoint in look-ahead: %d\n",
id);
ret = -ENOMEM; goto out;
}
ep = &htc->endpoint[id];
if (ep->service_id == 0) {
ath10k_warn(ar, "ep %d is not connected\n", id);
ret = -ENOMEM; goto out;
}
pkt = &ar_sdio->rx_pkts[i];
if (pkt->part_of_bundle && !pkt->last_in_bundle) { /* Only read lookahead's from RX trailers * for the last packet in a bundle.
*/
lookahead_idx--;
lookaheads_local = NULL;
n_lookahead_local = NULL;
}
ret = ath10k_sdio_mbox_rx_process_packet(ar,
pkt,
lookaheads_local,
n_lookahead_local); if (ret) goto out;
if (!pkt->trailer_only) {
cb = ATH10K_SKB_RXCB(pkt->skb);
cb->eid = id;
/* The RX complete handler now owns the skb...*/
pkt->skb = NULL;
pkt->alloc_len = 0;
}
ret = 0;
out: /* Free all packets that was not passed on to the RX completion * handler...
*/ for (; i < ar_sdio->n_rx_pkts; i++)
ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
if (*bndl_cnt > max_msgs) {
ath10k_warn(ar, "HTC bundle length %u exceeds maximum %u\n",
le16_to_cpu(htc_hdr->len),
max_msgs); return -ENOMEM;
}
/* Allocate bndl_cnt extra skb's for the bundle. * The package containing the * ATH10K_HTC_FLAG_BUNDLE_MASK flag is not included * in bndl_cnt. The skb for that packet will be * allocated separately.
*/ for (i = 0; i < *bndl_cnt; i++) {
ret = ath10k_sdio_mbox_alloc_rx_pkt(&rx_pkts[i],
act_len,
full_len, true, false); if (ret) return ret;
}
return0;
}
staticint ath10k_sdio_mbox_rx_alloc(struct ath10k *ar,
u32 lookaheads[], int n_lookaheads)
{ struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); struct ath10k_htc_hdr *htc_hdr;
size_t full_len, act_len; bool last_in_bundle; int ret, i; int pkt_cnt = 0;
if (n_lookaheads > ATH10K_SDIO_MAX_RX_MSGS) {
ath10k_warn(ar, "the total number of pkts to be fetched (%u) exceeds maximum %u\n",
n_lookaheads, ATH10K_SDIO_MAX_RX_MSGS);
ret = -ENOMEM; goto err;
}
for (i = 0; i < n_lookaheads; i++) {
htc_hdr = (struct ath10k_htc_hdr *)&lookaheads[i];
last_in_bundle = false;
if (le16_to_cpu(htc_hdr->len) > ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH) {
ath10k_warn(ar, "payload length %d exceeds max htc length: %zu\n",
le16_to_cpu(htc_hdr->len),
ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH);
ret = -ENOMEM;
if (full_len > ATH10K_SDIO_MAX_BUFFER_SIZE) {
ath10k_warn(ar, "rx buffer requested with invalid htc_hdr length (%d, 0x%x): %d\n",
htc_hdr->eid, htc_hdr->flags,
le16_to_cpu(htc_hdr->len));
ret = -EINVAL; goto err;
}
if (ath10k_htc_get_bundle_count(
ar->htc.max_msgs_per_htc_bundle, htc_hdr->flags)) { /* HTC header indicates that every packet to follow * has the same padded length so that it can be * optimally fetched as a full bundle.
*/
size_t bndl_cnt;
ret = ath10k_sdio_mbox_alloc_bundle(ar,
&ar_sdio->rx_pkts[pkt_cnt],
htc_hdr,
full_len,
act_len,
&bndl_cnt);
if (ret) {
ath10k_warn(ar, "failed to allocate a bundle: %d\n",
ret); goto err;
}
pkt_cnt += bndl_cnt;
/* next buffer will be the last in the bundle */
last_in_bundle = true;
}
/* Allocate skb for packet. If the packet had the * ATH10K_HTC_FLAG_BUNDLE_MASK flag set, all bundled * packet skb's have been allocated in the previous step.
*/ if (htc_hdr->flags & ATH10K_HTC_FLAGS_RECV_1MORE_BLOCK)
full_len += ATH10K_HIF_MBOX_BLOCK_SIZE;
ret = ath10k_sdio_mbox_alloc_rx_pkt(&ar_sdio->rx_pkts[pkt_cnt],
act_len,
full_len,
last_in_bundle,
last_in_bundle); if (ret) {
ath10k_warn(ar, "alloc_rx_pkt error %d\n", ret); goto err;
}
pkt_cnt++;
}
ar_sdio->n_rx_pkts = pkt_cnt;
return0;
err: for (i = 0; i < ATH10K_SDIO_MAX_RX_MSGS; i++) { if (!ar_sdio->rx_pkts[i].alloc_len) break;
ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
}
err: /* Free all packets that was not successfully fetched. */ for (i = 0; i < ar_sdio->n_rx_pkts; i++)
ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]);
ar_sdio->n_rx_pkts = 0;
return ret;
}
/* This is the timeout for mailbox processing done in the sdio irq * handler. The timeout is deliberately set quite high since SDIO dump logs * over serial port can/will add a substantial overhead to the processing * (if enabled).
*/ #define SDIO_MBOX_PROCESSING_TIMEOUT_HZ (20 * HZ)
/* Copy the lookahead obtained from the HTC register table into our * temp array as a start value.
*/
lookaheads[0] = msg_lookahead;
timeout = jiffies + SDIO_MBOX_PROCESSING_TIMEOUT_HZ; do { /* Try to allocate as many HTC RX packets indicated by * n_lookaheads.
*/
ret = ath10k_sdio_mbox_rx_alloc(ar, lookaheads,
n_lookaheads); if (ret) break;
if (ar_sdio->n_rx_pkts >= 2) /* A recv bundle was detected, force IRQ status * re-check again.
*/
*done = false;
if (ar_sdio->n_rx_pkts > 1)
ret = ath10k_sdio_mbox_rx_fetch_bundle(ar); else
ret = ath10k_sdio_mbox_rx_fetch(ar);
/* Process fetched packets. This will potentially update * n_lookaheads depending on if the packets contain lookahead * reports.
*/
n_lookaheads = 0;
ret = ath10k_sdio_mbox_rx_process_packets(ar,
lookaheads,
&n_lookaheads);
if (!n_lookaheads || ret) break;
/* For SYNCH processing, if we get here, we are running * through the loop again due to updated lookaheads. Set * flag that we should re-check IRQ status registers again * before leaving IRQ processing, this can net better * performance in high throughput situations.
*/
*done = false;
} while (time_before(jiffies, timeout));
if (ret && (ret != -ECANCELED))
ath10k_warn(ar, "failed to get pending recv messages: %d\n",
ret);
return ret;
}
staticint ath10k_sdio_mbox_proc_dbg_intr(struct ath10k *ar)
{
u32 val; int ret;
/* read counter to clear the interrupt, the debug error interrupt is * counter 0.
*/
ret = ath10k_sdio_read32(ar, MBOX_COUNT_DEC_ADDRESS, &val); if (ret)
ath10k_warn(ar, "failed to clear debug interrupt: %d\n", ret);
/* NOTE: other modules like GMBOX may use the counter interrupt for * credit flow control on other counters, we only need to check for * the debug assertion counter interrupt.
*/ if (counter_int_status & ATH10K_SDIO_TARGET_DEBUG_INTR_MASK)
ret = ath10k_sdio_mbox_proc_dbg_intr(ar); else
ret = 0;
if (FIELD_GET(MBOX_ERROR_INT_STATUS_WAKEUP_MASK,
error_int_status))
ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio interrupt error wakeup\n");
if (FIELD_GET(MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
error_int_status))
ath10k_warn(ar, "rx underflow interrupt error\n");
if (FIELD_GET(MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
error_int_status))
ath10k_warn(ar, "tx overflow interrupt error\n");
/* Clear the interrupt */
irq_data->irq_proc_reg->error_int_status &= ~error_int_status;
/* set W1C value to clear the interrupt, this hits the register first */
ret = ath10k_sdio_writesb32(ar, MBOX_ERROR_INT_STATUS_ADDRESS,
error_int_status); if (ret) {
ath10k_warn(ar, "unable to write to error int status address: %d\n",
ret); return ret;
}
mutex_lock(&irq_data->mtx);
cpu_int_status = irq_data->irq_proc_reg->cpu_int_status &
irq_data->irq_en_reg->cpu_int_status_en; if (!cpu_int_status) {
ath10k_warn(ar, "CPU interrupt status is zero\n");
ret = -EIO; goto out;
}
/* Clear the interrupt */
irq_data->irq_proc_reg->cpu_int_status &= ~cpu_int_status;
/* Set up the register transfer buffer to hit the register 4 times, * this is done to make the access 4-byte aligned to mitigate issues * with host bus interconnects that restrict bus transfer lengths to * be a multiple of 4-bytes. * * Set W1C value to clear the interrupt, this hits the register first.
*/
ret = ath10k_sdio_writesb32(ar, MBOX_CPU_INT_STATUS_ADDRESS,
cpu_int_status); if (ret) {
ath10k_warn(ar, "unable to write to cpu interrupt status address: %d\n",
ret); goto out;
}
out:
mutex_unlock(&irq_data->mtx); if (cpu_int_status & MBOX_CPU_STATUS_ENABLE_ASSERT_MASK)
ath10k_sdio_fw_crashed_dump(ar);
/* int_status_en is supposed to be non zero, otherwise interrupts * shouldn't be enabled. There is however a short time frame during * initialization between the irq register and int_status_en init * where this can happen. * We silently ignore this condition.
*/ if (!irq_en_reg->int_status_en) {
ret = 0; goto out;
}
/* Read the first sizeof(struct ath10k_irq_proc_registers) * bytes of the HTC register table. This * will yield us the value of different int status * registers and the lookahead registers.
*/
ret = ath10k_sdio_read(ar, MBOX_HOST_INT_STATUS_ADDRESS,
irq_proc_reg, sizeof(*irq_proc_reg)); if (ret) {
ath10k_core_start_recovery(ar);
ath10k_warn(ar, "read int status fail, start recovery\n"); goto out;
}
/* Update only those registers that are enabled */
*host_int_status = irq_proc_reg->host_int_status &
irq_en_reg->int_status_en;
/* Look at mbox status */ if (!(*host_int_status & htc_mbox)) {
*lookahead = 0;
ret = 0; goto out;
}
/* Mask out pending mbox value, we use look ahead as * the real flag for mbox processing.
*/
*host_int_status &= ~htc_mbox; if (irq_proc_reg->rx_lookahead_valid & htc_mbox) {
*lookahead = le32_to_cpu(
irq_proc_reg->rx_lookahead[ATH10K_HTC_MAILBOX]); if (!*lookahead)
ath10k_warn(ar, "sdio mbox lookahead is zero\n");
}
/* NOTE: HIF implementation guarantees that the context of this * call allows us to perform SYNCHRONOUS I/O, that is we can block, * sleep or call any API that can block or switch thread/task * contexts. This is a fully schedulable context.
*/
ret = ath10k_sdio_mbox_read_int_status(ar,
&host_int_status,
&lookahead); if (ret) {
*done = true; goto out;
}
if (!host_int_status && !lookahead) {
ret = 0;
*done = true; goto out;
}
ret = ath10k_sdio_mbox_rxmsg_pending_handler(ar,
lookahead,
done); if (ret) goto out;
}
/* now, handle the rest of the interrupts */
ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio host_int_status 0x%x\n", host_int_status);
if (FIELD_GET(MBOX_HOST_INT_STATUS_CPU_MASK, host_int_status)) { /* CPU Interrupt */
ret = ath10k_sdio_mbox_proc_cpu_intr(ar); if (ret) goto out;
}
if (FIELD_GET(MBOX_HOST_INT_STATUS_ERROR_MASK, host_int_status)) { /* Error Interrupt */
ret = ath10k_sdio_mbox_proc_err_intr(ar); if (ret) goto out;
}
if (FIELD_GET(MBOX_HOST_INT_STATUS_COUNTER_MASK, host_int_status)) /* Counter Interrupt */
ret = ath10k_sdio_mbox_proc_counter_intr(ar);
ret = 0;
out: /* An optimization to bypass reading the IRQ status registers * unnecessarily which can re-wake the target, if upper layers * determine that we are in a low-throughput mode, we can rely on * taking another interrupt rather than re-checking the status * registers which can re-wake the target. * * NOTE : for host interfaces that makes use of detecting pending * mbox messages at hif can not use this optimization due to * possible side effects, SPI requires the host to drain all * messages from the mailbox before exiting the ISR routine.
*/
/* Read the counter register to get the command credits */
addr = MBOX_COUNT_DEC_ADDRESS + ATH10K_HIF_MBOX_NUM_MAX * 4;
timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
cmd_credits = 0;
while (time_before(jiffies, timeout) && !cmd_credits) { /* Hit the credit counter with a 4-byte access, the first byte * read will hit the counter and cause a decrement, while the * remaining 3 bytes has no effect. The rationale behind this * is to make all HIF accesses 4-byte aligned.
*/
ret = ath10k_sdio_read32(ar, addr, &cmd_credits); if (ret) {
ath10k_warn(ar, "unable to decrement the command credit count register: %d\n",
ret); return ret;
}
/* The counter is only 8 bits. * Ignore anything in the upper 3 bytes
*/
cmd_credits &= 0xFF;
}
if (!cmd_credits) {
ath10k_warn(ar, "bmi communication timeout\n"); return -ETIMEDOUT;
}
if (req) {
ret = ath10k_sdio_bmi_credits(ar); if (ret) return ret;
addr = ar_sdio->mbox_info.htc_addr;
memcpy(ar_sdio->bmi_buf, req, req_len);
ret = ath10k_sdio_write(ar, addr, ar_sdio->bmi_buf, req_len); if (ret) {
ath10k_warn(ar, "unable to send the bmi data to the device: %d\n",
ret); return ret;
}
}
if (!resp || !resp_len) /* No response expected */ return0;
/* During normal bootup, small reads may be required. * Rather than issue an HIF Read and then wait as the Target * adds successive bytes to the FIFO, we wait here until * we know that response data is available. * * This allows us to cleanly timeout on an unexpected * Target failure rather than risk problems at the HIF level. * In particular, this avoids SDIO timeouts and possibly garbage * data on some host controllers. And on an interconnect * such as Compact Flash (as well as some SDIO masters) which * does not provide any indication on data timeout, it avoids * a potential hang or garbage response. * * Synchronization is more difficult for reads larger than the * size of the MBOX FIFO (128B), because the Target is unable * to push the 129th byte of data until AFTER the Host posts an * HIF Read and removes some FIFO data. So for large reads the * Host proceeds to post an HIF Read BEFORE all the data is * actually available to read. Fortunately, large BMI reads do * not occur in practice -- they're supported for debug/development. * * So Host/Target BMI synchronization is divided into these cases: * CASE 1: length < 4 * Should not happen * * CASE 2: 4 <= length <= 128 * Wait for first 4 bytes to be in FIFO * If CONSERVATIVE_BMI_READ is enabled, also wait for * a BMI command credit, which indicates that the ENTIRE * response is available in the FIFO * * CASE 3: length > 128 * Wait for the first 4 bytes to be in FIFO * * For most uses, a small timeout should be sufficient and we will * usually see a response quickly; but there may be some unusual * (debug) cases of BMI_EXECUTE where we want an larger timeout. * For now, we use an unbounded busy loop while waiting for * BMI_EXECUTE. * * If BMI_EXECUTE ever needs to support longer-latency execution, * especially in production, this code needs to be enhanced to sleep * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently * a function of Host processor speed.
*/
ret = ath10k_sdio_bmi_get_rx_lookahead(ar); if (ret) return ret;
/* We always read from the start of the mbox address */
addr = ar_sdio->mbox_info.htc_addr;
ret = ath10k_sdio_read(ar, addr, ar_sdio->bmi_buf, *resp_len); if (ret) {
ath10k_warn(ar, "unable to read the bmi data from the device: %d\n",
ret); return ret;
}
ret = ath10k_sdio_read32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, &val); if (ret) {
ath10k_warn(ar, "failed to read fifo/chip control register: %d\n",
ret); goto release;
}
if (enable_sleep) {
val &= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF;
ar_sdio->mbox_state = SDIO_MBOX_SLEEP_STATE;
} else {
val |= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON;
ar_sdio->mbox_state = SDIO_MBOX_AWAKE_STATE;
}
ret = ath10k_sdio_write32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, val); if (ret) {
ath10k_warn(ar, "failed to write to FIFO_TIMEOUT_AND_CHIP_CONTROL: %d",
ret);
}
if (!enable_sleep) { do {
udelay(ATH10K_CIS_READ_WAIT_4_RTC_CYCLE_IN_US);
ret = ath10k_sdio_read_rtc_state(ar_sdio, &rtc_state);
if (ret) {
ath10k_warn(ar, "failed to disable mbox sleep: %d", ret); break;
}
/* Allocate a bus request for the message and queue it on the * SDIO workqueue.
*/
bus_req = ath10k_sdio_alloc_busreq(ar); if (!bus_req) {
ath10k_warn(ar, "unable to allocate bus request for async request\n"); return -ENOMEM;
}
/* Release the host during interrupts so we can pick it back up when * we process commands.
*/
sdio_release_host(ar_sdio->func);
timeout = jiffies + ATH10K_SDIO_HIF_COMMUNICATION_TIMEOUT_HZ; do {
ret = ath10k_sdio_mbox_proc_pending_irqs(ar, &done); if (ret) break;
} while (time_before(jiffies, timeout) && !done);
ath10k_mac_tx_push_pending(ar);
sdio_claim_host(ar_sdio->func);
if (ret && ret != -ECANCELED)
ath10k_warn(ar, "failed to process pending SDIO interrupts: %d\n",
ret);
}
/* Write TX data to the end of the mbox address space */
address = ar_sdio->mbox_addr[eid] + ar_sdio->mbox_size[eid] -
skb->len;
ret = ath10k_sdio_prep_async_req(ar, address, skb,
NULL, true, eid); if (ret) return ret;
}
/* Enable all but CPU interrupts */
regs->int_status_en = FIELD_PREP(MBOX_INT_STATUS_ENABLE_ERROR_MASK, 1) |
FIELD_PREP(MBOX_INT_STATUS_ENABLE_CPU_MASK, 1) |
FIELD_PREP(MBOX_INT_STATUS_ENABLE_COUNTER_MASK, 1);
/* NOTE: There are some cases where HIF can do detection of * pending mbox messages which is disabled now.
*/
regs->int_status_en |=
FIELD_PREP(MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK, 1);
/* Set up the CPU Interrupt Status Register, enable CPU sourced interrupt #0 * #0 is used for report assertion from target
*/
regs->cpu_int_status_en = FIELD_PREP(MBOX_CPU_STATUS_ENABLE_ASSERT_MASK, 1);
/* Set up the Error Interrupt status Register */
regs->err_int_status_en =
FIELD_PREP(MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, 1) |
FIELD_PREP(MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, 1);
/* Enable Counter interrupt status register to get fatal errors for * debugging.
*/
regs->cntr_int_status_en =
FIELD_PREP(MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
ATH10K_SDIO_TARGET_DEBUG_INTR_MASK);
ret = ath10k_sdio_write(ar, MBOX_INT_STATUS_ENABLE_ADDRESS,
®s->int_status_en, sizeof(*regs)); if (ret)
ath10k_warn(ar, "failed to update mbox interrupt status register : %d\n",
ret);
mem = kzalloc(buf_len, GFP_KERNEL); if (!mem) return -ENOMEM;
/* set window register to start read cycle */
ret = ath10k_sdio_write32(ar, MBOX_WINDOW_READ_ADDR_ADDRESS, address); if (ret) {
ath10k_warn(ar, "failed to set mbox window read address: %d", ret); goto out;
}
/* read the data */
ret = ath10k_sdio_read(ar, MBOX_WINDOW_DATA_ADDRESS, mem, buf_len); if (ret) {
ath10k_warn(ar, "failed to read from mbox window data address: %d\n",
ret); goto out;
}
val = kzalloc(sizeof(*val), GFP_KERNEL); if (!val) return -ENOMEM;
ret = ath10k_sdio_hif_diag_read(ar, address, val, sizeof(*val)); if (ret) goto out;
*value = __le32_to_cpu(*val);
out:
kfree(val);
return ret;
}
staticint ath10k_sdio_hif_diag_write_mem(struct ath10k *ar, u32 address, constvoid *data, int nbytes)
{ int ret;
/* set write data */
ret = ath10k_sdio_write(ar, MBOX_WINDOW_DATA_ADDRESS, data, nbytes); if (ret) {
ath10k_warn(ar, "failed to write 0x%p to mbox window data address: %d\n",
data, ret); return ret;
}
/* set window register, which starts the write cycle */
ret = ath10k_sdio_write32(ar, MBOX_WINDOW_WRITE_ADDR_ADDRESS, address); if (ret) {
ath10k_warn(ar, "failed to set mbox window write address: %d", ret); return ret;
}
return0;
}
staticint ath10k_sdio_hif_start_post(struct ath10k *ar)
{ struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar);
u32 addr, val; int ret = 0;
/* Sleep 20 ms before HIF interrupts are disabled. * This will give target plenty of time to process the BMI done * request before interrupts are disabled.
*/
msleep(20);
ret = ath10k_sdio_disable_intrs(ar); if (ret) return ret;
/* eid 0 always uses the lower part of the extended mailbox address * space (ext_info[0].htc_ext_addr).
*/
ar_sdio->mbox_addr[0] = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
ar_sdio->mbox_size[0] = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
sdio_claim_host(ar_sdio->func);
/* Register the isr */
ret = sdio_claim_irq(ar_sdio->func, ath10k_sdio_irq_handler); if (ret) {
ath10k_warn(ar, "failed to claim sdio interrupt: %d\n", ret);
sdio_release_host(ar_sdio->func); return ret;
}
sdio_release_host(ar_sdio->func);
ret = ath10k_sdio_enable_intrs(ar); if (ret)
ath10k_warn(ar, "failed to enable sdio interrupts: %d\n", ret);
/* Enable sleep and then disable it again */
ret = ath10k_sdio_set_mbox_sleep(ar, true); if (ret) return ret;
/* Wait for 20ms for the written value to take effect */
msleep(20);
ret = ath10k_sdio_set_mbox_sleep(ar, false); if (ret) return ret;
/* Wait for the completion of the IRQ disable request. * If there is a timeout we will try to disable irq's anyway.
*/
ret = wait_for_completion_timeout(&irqs_disabled_comp,
SDIO_IRQ_DISABLE_TIMEOUT_HZ); if (!ret)
ath10k_warn(ar, "sdio irq disable request timed out\n");
sdio_claim_host(ar_sdio->func);
ret = sdio_release_irq(ar_sdio->func); if (ret)
ath10k_warn(ar, "failed to release sdio interrupt: %d\n", ret);
/* For sdio, we are interested in the mapping between eid * and pipeid rather than service_id to pipe_id. * First we find out which eid has been allocated to the * service...
*/ for (i = 0; i < ATH10K_HTC_EP_COUNT; i++) { if (htc->endpoint[i].service_id == service_id) {
eid = htc->endpoint[i].eid;
ep_found = true; break;
}
}
if (!ep_found) return -EINVAL;
/* Then we create the simplest mapping possible between pipeid * and eid
*/
*ul_pipe = *dl_pipe = (u8)eid;
/* Normally, HTT will use the upper part of the extended * mailbox address space (ext_info[1].htc_ext_addr) and WMI ctrl * the lower part (ext_info[0].htc_ext_addr). * If fw wants swapping of mailbox addresses, the opposite is true.
*/ if (ar_sdio->swap_mbox) {
htt_addr = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
wmi_addr = ar_sdio->mbox_info.ext_info[1].htc_ext_addr;
htt_mbox_size = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
wmi_mbox_size = ar_sdio->mbox_info.ext_info[1].htc_ext_sz;
} else {
htt_addr = ar_sdio->mbox_info.ext_info[1].htc_ext_addr;
wmi_addr = ar_sdio->mbox_info.ext_info[0].htc_ext_addr;
htt_mbox_size = ar_sdio->mbox_info.ext_info[1].htc_ext_sz;
wmi_mbox_size = ar_sdio->mbox_info.ext_info[0].htc_ext_sz;
}
switch (service_id) { case ATH10K_HTC_SVC_ID_RSVD_CTRL: /* HTC ctrl ep mbox address has already been setup in * ath10k_sdio_hif_start
*/ break; case ATH10K_HTC_SVC_ID_WMI_CONTROL:
ar_sdio->mbox_addr[eid] = wmi_addr;
ar_sdio->mbox_size[eid] = wmi_mbox_size;
ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio wmi ctrl mbox_addr 0x%x mbox_size %d\n",
ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]); break; case ATH10K_HTC_SVC_ID_HTT_DATA_MSG:
ar_sdio->mbox_addr[eid] = htt_addr;
ar_sdio->mbox_size[eid] = htt_mbox_size;
ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio htt data mbox_addr 0x%x mbox_size %d\n",
ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]); break; default:
ath10k_warn(ar, "unsupported HTC service id: %d\n",
service_id); return -EINVAL;
}
if (ret)
ath10k_warn(ar, "unable to read host interest offset %d value\n",
item_offset);
return ret;
}
staticint ath10k_sdio_read_mem(struct ath10k *ar, u32 address, void *buf,
u32 buf_len)
{
u32 val; int i, ret;
for (i = 0; i < buf_len; i += 4) {
ret = ath10k_sdio_diag_read32(ar, address + i, &val); if (ret) {
ath10k_warn(ar, "unable to read mem %d value\n", address + i); break;
}
memcpy(buf + i, &val, 4);
}
staticvoid ath10k_sdio_dump_registers(struct ath10k *ar, struct ath10k_fw_crash_data *crash_data, bool fast_dump)
{
u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; int i, ret;
u32 reg_dump_area;
ret = ath10k_sdio_read_host_interest_value(ar, HI_ITEM(hi_failure_state),
®_dump_area); if (ret) {
ath10k_warn(ar, "failed to read firmware dump area: %d\n", ret); return;
}
if (fast_dump)
ret = ath10k_bmi_read_memory(ar, reg_dump_area, reg_dump_values, sizeof(reg_dump_values)); else
ret = ath10k_sdio_read_mem(ar, reg_dump_area, reg_dump_values, sizeof(reg_dump_values));
if (ret) {
ath10k_warn(ar, "failed to read firmware dump value: %d\n", ret); return;
}
ath10k_err(ar, "firmware register dump:\n"); for (i = 0; i < ARRAY_SIZE(reg_dump_values); i += 4)
ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
i,
reg_dump_values[i],
reg_dump_values[i + 1],
reg_dump_values[i + 2],
reg_dump_values[i + 3]);
if (!crash_data) return;
for (i = 0; i < ARRAY_SIZE(reg_dump_values); i++)
crash_data->registers[i] = __cpu_to_le32(reg_dump_values[i]);
}
/* fill the gap between the first register section and register * start address
*/ for (i = 0; i < skip_size; i++) {
*buf = ATH10K_MAGIC_NOT_COPIED;
buf++;
}
count = 0;
i = 0; for (; cur_section; cur_section = next_section) {
section_size = cur_section->end - cur_section->start;
if (section_size <= 0) {
ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n",
cur_section->start,
cur_section->end); break;
}
if (cur_section->end > next_section->start) {
ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n",
next_section->start,
cur_section->end); break;
}
if (buf_len < (skip_size + section_size)) {
ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len); break;
}
buf_len -= skip_size + section_size;
/* read section to dest memory */
ret = ath10k_sdio_read_mem(ar, cur_section->start,
buf, section_size); if (ret) {
ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n",
cur_section->start, ret); break;
}
buf += section_size;
count += section_size;
/* fill in the gap between this section and the next */ for (j = 0; j < skip_size; j++) {
*buf = ATH10K_MAGIC_NOT_COPIED;
buf++;
}
count += skip_size;
}
return count;
}
/* if an error happened returns < 0, otherwise the length */ staticint ath10k_sdio_dump_memory_generic(struct ath10k *ar, conststruct ath10k_mem_region *current_region,
u8 *buf, bool fast_dump)
{ int ret;
if (current_region->section_table.size > 0) /* Copy each section individually. */ return ath10k_sdio_dump_memory_section(ar,
current_region,
buf,
current_region->len);
/* No individual memory sections defined so we can * copy the entire memory region.
*/ if (fast_dump)
ret = ath10k_bmi_read_memory(ar,
current_region->start,
buf,
current_region->len); else
ret = ath10k_sdio_read_mem(ar,
current_region->start,
buf,
current_region->len);
if (ret) {
ath10k_warn(ar, "failed to copy ramdump region %s: %d\n",
current_region->name, ret); return ret;
}
/* Assumption: All SDIO based chipsets (so far) are QCA6174 based. * If there will be newer chipsets that does not use the hw reg * setup as defined in qca6174_regs and qca6174_values, this * assumption is no longer valid and hw_rev must be setup differently * depending on chipset.
*/
hw_rev = ATH10K_HW_QCA6174;
ar = ath10k_core_create(sizeof(*ar_sdio), &func->dev, ATH10K_BUS_SDIO,
hw_rev, &ath10k_sdio_hif_ops); if (!ar) {
dev_err(&func->dev, "failed to allocate core\n"); return -ENOMEM;
}
