// Load half of a vector and duplicated in other half static inline uint8x8_t vldh_dup_u8(const uint8_t *ptr) { return vreinterpret_u8_u32(vld1_dup_u32((const uint32_t *)ptr));
}
// Store half of a vector. static inline void vsth_u16(uint16_t *ptr, uint16x4_t val) {
vst1_lane_u32((uint32_t *)ptr, vreinterpret_u32_u16(val), 0);
}
// Store half of a vector. static inline void vsth_u8(uint8_t *ptr, uint8x8_t val) {
vst1_lane_u32((uint32_t *)ptr, vreinterpret_u32_u8(val), 0);
}
staticvoid cfl_luma_subsampling_420_lbd_neon(const uint8_t *input,
int input_stride,
uint16_t *pred_buf_q3, int width,
int height) { const uint16_t *end = pred_buf_q3 + (height >> 1) * CFL_BUF_LINE; const int luma_stride = input_stride << 1; do {
if (width == 4) { const uint16x4_t top = vpaddl_u8(vldh_dup_u8(input)); const uint16x4_t sum = vpadal_u8(top, vldh_dup_u8(input + input_stride));
vsth_u16(pred_buf_q3, vshl_n_u16(sum, 1));
} else if (width == 8) { const uint16x4_t top = vpaddl_u8(vld1_u8(input)); const uint16x4_t sum = vpadal_u8(top, vld1_u8(input + input_stride));
vst1_u16(pred_buf_q3, vshl_n_u16(sum, 1));
} else if (width == 16) { const uint16x8_t top = vpaddlq_u8(vld1q_u8(input)); const uint16x8_t sum = vpadalq_u8(top, vld1q_u8(input + input_stride));
vst1q_u16(pred_buf_q3, vshlq_n_u16(sum, 1));
} else { const uint8x8x4_t top = vld4_u8(input); const uint8x8x4_t bot = vld4_u8(input + input_stride); // equivalent to a vpaddlq_u8 (because vld4q interleaves) const uint16x8_t top_0 = vaddl_u8(top.val[0], top.val[1]); // equivalent to a vpaddlq_u8 (because vld4q interleaves) const uint16x8_t bot_0 = vaddl_u8(bot.val[0], bot.val[1]); // equivalent to a vpaddlq_u8 (because vld4q interleaves) const uint16x8_t top_1 = vaddl_u8(top.val[2], top.val[3]); // equivalent to a vpaddlq_u8 (because vld4q interleaves) const uint16x8_t bot_1 = vaddl_u8(bot.val[2], bot.val[3]);
uint16x8x2_t sum;
sum.val[0] = vshlq_n_u16(vaddq_u16(top_0, bot_0), 1);
sum.val[1] = vshlq_n_u16(vaddq_u16(top_1, bot_1), 1);
vst2q_u16(pred_buf_q3, sum);
}
input += luma_stride;
} while ((pred_buf_q3 += CFL_BUF_LINE) < end);
}
staticvoid cfl_luma_subsampling_422_lbd_neon(const uint8_t *input,
int input_stride,
uint16_t *pred_buf_q3, int width,
int height) { const uint16_t *end = pred_buf_q3 + height * CFL_BUF_LINE; do {
if (width == 4) { const uint16x4_t top = vpaddl_u8(vldh_dup_u8(input));
vsth_u16(pred_buf_q3, vshl_n_u16(top, 2));
} else if (width == 8) { const uint16x4_t top = vpaddl_u8(vld1_u8(input));
vst1_u16(pred_buf_q3, vshl_n_u16(top, 2));
} else if (width == 16) { const uint16x8_t top = vpaddlq_u8(vld1q_u8(input));
vst1q_u16(pred_buf_q3, vshlq_n_u16(top, 2));
} else { const uint8x8x4_t top = vld4_u8(input);
uint16x8x2_t sum; // vaddl_u8 is equivalent to a vpaddlq_u8 (because vld4q interleaves)
sum.val[0] = vshlq_n_u16(vaddl_u8(top.val[0], top.val[1]), 2);
sum.val[1] = vshlq_n_u16(vaddl_u8(top.val[2], top.val[3]), 2);
vst2q_u16(pred_buf_q3, sum);
}
input += input_stride;
} while ((pred_buf_q3 += CFL_BUF_LINE) < end);
}
staticvoid cfl_luma_subsampling_444_lbd_neon(const uint8_t *input,
int input_stride,
uint16_t *pred_buf_q3, int width,
int height) { const uint16_t *end = pred_buf_q3 + height * CFL_BUF_LINE; do {
if (width == 4) { const uint16x8_t top = vshll_n_u8(vldh_dup_u8(input), 3);
vst1_u16(pred_buf_q3, vget_low_u16(top));
} else if (width == 8) { const uint16x8_t top = vshll_n_u8(vld1_u8(input), 3);
vst1q_u16(pred_buf_q3, top);
} else { const uint8x16_t top = vld1q_u8(input);
vst1q_u16(pred_buf_q3, vshll_n_u8(vget_low_u8(top), 3));
vst1q_u16(pred_buf_q3 + 8, vshll_n_u8(vget_high_u8(top), 3));
if (width == 32) { const uint8x16_t next_top = vld1q_u8(input + 16);
vst1q_u16(pred_buf_q3 + 16, vshll_n_u8(vget_low_u8(next_top), 3));
vst1q_u16(pred_buf_q3 + 24, vshll_n_u8(vget_high_u8(next_top), 3));
}
}
input += input_stride;
} while ((pred_buf_q3 += CFL_BUF_LINE) < end);
}
#if CONFIG_AV1_HIGHBITDEPTH #if !AOM_ARCH_AARCH64 static uint16x8_t vpaddq_u16(uint16x8_t a, uint16x8_t b) { return vcombine_u16(vpadd_u16(vget_low_u16(a), vget_high_u16(a)),
vpadd_u16(vget_low_u16(b), vget_high_u16(b)));
} #endif
// Permute and add in such a way that each lane contains the block sum. // [A+C+B+D, B+D+A+C, C+A+D+B, D+B+C+A] #if AOM_ARCH_AARCH64
sum_32x4 = vpaddq_u32(sum_32x4, sum_32x4);
sum_32x4 = vpaddq_u32(sum_32x4, sum_32x4); #else
uint32x4_t flip =
vcombine_u32(vget_high_u32(sum_32x4), vget_low_u32(sum_32x4));
sum_32x4 = vaddq_u32(sum_32x4, flip);
sum_32x4 = vaddq_u32(sum_32x4, vrev64q_u32(sum_32x4)); #endif
// Computing the average could be done using scalars, but getting off the NEON // engine introduces latency, so we use vqrshrn.
int16x4_t avg_16x4; // Constant propagation makes for some ugly code. switch (num_pel_log2) { case4: avg_16x4 = vreinterpret_s16_u16(vqrshrn_n_u32(sum_32x4, 4)); break; case5: avg_16x4 = vreinterpret_s16_u16(vqrshrn_n_u32(sum_32x4, 5)); break; case6: avg_16x4 = vreinterpret_s16_u16(vqrshrn_n_u32(sum_32x4, 6)); break; case7: avg_16x4 = vreinterpret_s16_u16(vqrshrn_n_u32(sum_32x4, 7)); break; case8: avg_16x4 = vreinterpret_s16_u16(vqrshrn_n_u32(sum_32x4, 8)); break; case9: avg_16x4 = vreinterpret_s16_u16(vqrshrn_n_u32(sum_32x4, 9)); break; case10:
avg_16x4 = vreinterpret_s16_u16(vqrshrn_n_u32(sum_32x4, 10)); break; default: assert(0);
}
// Saturating negate 16-bit integers in a when the corresponding signed 16-bit // integer in b is negative. // Notes: // * Negating INT16_MIN results in INT16_MIN. However, this cannot occur in // practice, as scaled_luma is the multiplication of two absolute values. // * In the Intel equivalent, elements in a are zeroed out when the // corresponding elements in b are zero. Because vsign is used twice in a // row, with b in the first call becoming a in the second call, there's no // impact from not zeroing out. static int16x4_t vsign_s16(int16x4_t a, int16x4_t b) { const int16x4_t mask = vshr_n_s16(b, 15); return veor_s16(vadd_s16(a, mask), mask);
}
// Saturating negate 16-bit integers in a when the corresponding signed 16-bit // integer in b is negative. // Notes: // * Negating INT16_MIN results in INT16_MIN. However, this cannot occur in // practice, as scaled_luma is the multiplication of two absolute values. // * In the Intel equivalent, elements in a are zeroed out when the // corresponding elements in b are zero. Because vsignq is used twice in a // row, with b in the first call becoming a in the second call, there's no // impact from not zeroing out. static int16x8_t vsignq_s16(int16x8_t a, int16x8_t b) { const int16x8_t mask = vshrq_n_s16(b, 15); return veorq_s16(vaddq_s16(a, mask), mask);
}
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