/* * Copyright © 2018, VideoLAN and dav1d authors * Copyright © 2019, B Krishnan Iyer * Copyright © 2020, Martin Storsjo * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. "src/arm/asm.S" "util.S" sub r3, r3, #25align 2word 640f - L(ipred_dc_128_tbl) + CONFIG_THUMBword 320f - L(ipred_dc_128_tbl) + CONFIG_THUMBword 160f - L(ipred_dc_128_tbl) + CONFIG_THUMBword 8f - L(ipred_dc_128_tbl) + CONFIG_THUMBword 4f - L(ipred_dc_128_tbl) + CONFIG_THUMBsub r1, r1, #32! ! ! ! sub r1, r1, #96! ! ! ! ! ! sub r3, r3, #25align 2word 640f - L(ipred_v_tbl) + CONFIG_THUMBword 320f - L(ipred_v_tbl) + CONFIG_THUMBword 160f - L(ipred_v_tbl) + CONFIG_THUMBword 80f - L(ipred_v_tbl) + CONFIG_THUMBword 40f - L(ipred_v_tbl) + CONFIG_THUMB! sub r1, r1, #32! ! ! ! ! sub r1, r1, #96! ! ! ! ! ! ! ! ! sub r3, r3, #25sub r2, r2, #2align 2word 640f - L(ipred_h_tbl) + CONFIG_THUMBword 320f - L(ipred_h_tbl) + CONFIG_THUMBword 160f - L(ipred_h_tbl) + CONFIG_THUMBword 8f - L(ipred_h_tbl) + CONFIG_THUMBword 40f - L(ipred_h_tbl) + CONFIG_THUMBsub r2, r2, #6sub r1, r1, #16! ! ! ! sub r1, r1, #48! ! ! ! ! ! ! ! ! ! ! ! sub r1, r1, #96! ! ! ! ! ! sub r3, r3, #25align 2word 640f - L(ipred_dc_top_tbl) + CONFIG_THUMBword 320f - L(ipred_dc_top_tbl) + CONFIG_THUMBword 160f - L(ipred_dc_top_tbl) + CONFIG_THUMBword 80f - L(ipred_dc_top_tbl) + CONFIG_THUMBword 40f - L(ipred_dc_top_tbl) + CONFIG_THUMB! sub r1, r1, #32! ! ! ! ! ! ! sub r1, r1, #96! ! ! ! ! ! sub r2, r2, r4, lsl #1sub lr, lr, #25sub r3, r3, #20align 2word L(ipred_dc_left_h64) - L(ipred_dc_left_tbl) + CONFIG_THUMBword L(ipred_dc_left_h32) - L(ipred_dc_left_tbl) + CONFIG_THUMBword L(ipred_dc_left_h16) - L(ipred_dc_left_tbl) + CONFIG_THUMBword L(ipred_dc_left_h8) - L(ipred_dc_left_tbl) + CONFIG_THUMBword L(ipred_dc_left_h4) - L(ipred_dc_left_tbl) + CONFIG_THUMBword L(ipred_dc_left_w64) - L(ipred_dc_left_tbl) + CONFIG_THUMBword L(ipred_dc_left_w32) - L(ipred_dc_left_tbl) + CONFIG_THUMBword L(ipred_dc_left_w16) - L(ipred_dc_left_tbl) + CONFIG_THUMBword L(ipred_dc_left_w8) - L(ipred_dc_left_tbl) + CONFIG_THUMBword L(ipred_dc_left_w4) - L(ipred_dc_left_tbl) + CONFIG_THUMB! sub r1, r1, #32! ! ! ! ! ! ! sub r1, r1, #96! ! ! ! ! ! sub r2, r2, r4, lsl #1sub r3, r3, #20 // 25 leading bits, minus table offset 5sub r12, r12, #25align 2word L(ipred_dc_h64) - L(ipred_dc_tbl) + CONFIG_THUMBword L(ipred_dc_h32) - L(ipred_dc_tbl) + CONFIG_THUMBword L(ipred_dc_h16) - L(ipred_dc_tbl) + CONFIG_THUMBword L(ipred_dc_h8) - L(ipred_dc_tbl) + CONFIG_THUMBword L(ipred_dc_h4) - L(ipred_dc_tbl) + CONFIG_THUMBword L(ipred_dc_w64) - L(ipred_dc_tbl) + CONFIG_THUMBword L(ipred_dc_w32) - L(ipred_dc_tbl) + CONFIG_THUMBword L(ipred_dc_w16) - L(ipred_dc_tbl) + CONFIG_THUMBword L(ipred_dc_w8) - L(ipred_dc_tbl) + CONFIG_THUMBword L(ipred_dc_w4) - L(ipred_dc_tbl) + CONFIG_THUMB! ! ! ! ! ! sub r1, r1, #32! ! ! ! ! ! ! ! ! ! ! ! sub r1, r1, #96! ! ! ! ! ! sub lr, lr, #25sub r2, r2, #4align 2word 640f - L(ipred_paeth_tbl) + CONFIG_THUMBword 320f - L(ipred_paeth_tbl) + CONFIG_THUMBword 160f - L(ipred_paeth_tbl) + CONFIG_THUMBword 80f - L(ipred_paeth_tbl) + CONFIG_THUMBword 40f - L(ipred_paeth_tbl) + CONFIG_THUMBsub r2, r2, #4! sub r1, r1, r3, lsl #1! ! ! sub r6, r6, r12, lsl #1! sub lr, r2, r4, lsl #1sub r9, r9, #25align 2word 640f - L(ipred_smooth_tbl) + CONFIG_THUMBword 320f - L(ipred_smooth_tbl) + CONFIG_THUMBword 160f - L(ipred_smooth_tbl) + CONFIG_THUMBword 80f - L(ipred_smooth_tbl) + CONFIG_THUMBword 40f - L(ipred_smooth_tbl) + CONFIG_THUMBsub r2, r2, #8! // weights_ver sub r2, r2, #4! // weights_ver sub r2, r2, #4sub r1, r1, r3, lsl #1! // weights_ver ! // weights_hor ! // top ! ! sub r8, r8, r9, lsl #1sub r10, r10, r9sub r12, r2, r4, lsl #1sub lr, lr, #25align 2word 640f - L(ipred_smooth_v_tbl) + CONFIG_THUMBword 320f - L(ipred_smooth_v_tbl) + CONFIG_THUMBword 160f - L(ipred_smooth_v_tbl) + CONFIG_THUMBword 80f - L(ipred_smooth_v_tbl) + CONFIG_THUMBword 40f - L(ipred_smooth_v_tbl) + CONFIG_THUMB! // weights_ver ! // weights_ver Set up pointers for four rows in parallel; r0, r6, r5, lrsub r1, r1, r3, lsl #1! // weights_ver ! // top ! ! ! ! sub r2, r2, r12, lsl #1sub lr, lr, #25align 2word 640f - L(ipred_smooth_h_tbl) + CONFIG_THUMBword 320f - L(ipred_smooth_h_tbl) + CONFIG_THUMBword 160f - L(ipred_smooth_h_tbl) + CONFIG_THUMBword 80f - L(ipred_smooth_h_tbl) + CONFIG_THUMBword 40f - L(ipred_smooth_h_tbl) + CONFIG_THUMBsub r2, r2, #8sub r2, r2, #8sub r2, r2, #8Set up pointers for four rows in parallel; r0, r6, r5, lrsub r1, r1, r3, lsl #1! // weights_hor ! ! ! ! sub r8, r8, r12! sub lr, lr, #26sub r2, r2, #4align 2word 320f - L(ipred_filter\bpc\()_tbl) + CONFIG_THUMBword 160f - L(ipred_filter\bpc\()_tbl) + CONFIG_THUMBword 80f - L(ipred_filter\bpc\()_tbl) + CONFIG_THUMBword 40f - L(ipred_filter\bpc\()_tbl) + CONFIG_THUMBsub r1, r1, r3, lsl #1! // top(0-15) ! ! sub r8, r6, lr, lsl #1sub lr, lr, #25align 2word 640f - L(pal_pred_tbl) + CONFIG_THUMBword 320f - L(pal_pred_tbl) + CONFIG_THUMBword 160f - L(pal_pred_tbl) + CONFIG_THUMBword 80f - L(pal_pred_tbl) + CONFIG_THUMBword 40f - L(pal_pred_tbl) + CONFIG_THUMB! ! ! sub r1, r1, #32! ! ! sub r1, r1, #96! ! ! ! sub lr, lr, #26align 2word L(ipred_cfl_splat_w16) - L(ipred_cfl_128_tbl) + CONFIG_THUMBword L(ipred_cfl_splat_w16) - L(ipred_cfl_128_tbl) + CONFIG_THUMBword L(ipred_cfl_splat_w8) - L(ipred_cfl_128_tbl) + CONFIG_THUMBword L(ipred_cfl_splat_w4) - L(ipred_cfl_128_tbl) + CONFIG_THUMB! ! sub r1, r1, r3, lsl #1! ! ! ! sub lr, lr, #26align 2word 32f - L(ipred_cfl_top_tbl) + CONFIG_THUMBword 16f - L(ipred_cfl_top_tbl) + CONFIG_THUMBword 8f - L(ipred_cfl_top_tbl) + CONFIG_THUMBword 4f - L(ipred_cfl_top_tbl) + CONFIG_THUMB! sub r2, r2, r4, lsl #1sub lr, lr, #26sub r8, r8, #26align 2word L(ipred_cfl_left_h32) - L(ipred_cfl_left_tbl) + CONFIG_THUMBword L(ipred_cfl_left_h16) - L(ipred_cfl_left_tbl) + CONFIG_THUMBword L(ipred_cfl_left_h8) - L(ipred_cfl_left_tbl) + CONFIG_THUMBword L(ipred_cfl_left_h4) - L(ipred_cfl_left_tbl) + CONFIG_THUMB! sub r2, r2, r4, lsl #1sub lr, lr, #22 // 26 leading bits, minus table offset 4sub r6, r6, #26align 2word L(ipred_cfl_h32) - L(ipred_cfl_tbl) + CONFIG_THUMBword L(ipred_cfl_h16) - L(ipred_cfl_tbl) + CONFIG_THUMBword L(ipred_cfl_h8) - L(ipred_cfl_tbl) + CONFIG_THUMBword L(ipred_cfl_h4) - L(ipred_cfl_tbl) + CONFIG_THUMBword L(ipred_cfl_w32) - L(ipred_cfl_tbl) + CONFIG_THUMBword L(ipred_cfl_w16) - L(ipred_cfl_tbl) + CONFIG_THUMBword L(ipred_cfl_w8) - L(ipred_cfl_tbl) + CONFIG_THUMBword L(ipred_cfl_w4) - L(ipred_cfl_tbl) + CONFIG_THUMB! ! ! ! ! ! ! sub r8, r8, #27sub r8, r6, r4 // height - h_padalign 2word L(ipred_cfl_ac_420_w16) - L(ipred_cfl_ac_420_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_420_w8) - L(ipred_cfl_ac_420_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_420_w4) - L(ipred_cfl_ac_420_tbl) + CONFIG_THUMB! "cmp r4, #0" ! sub r0, r0, r6, lsl #3! ! ! "cmp r4, #0" ! ! align 2word L(ipred_cfl_ac_420_w16_wpad0) - L(ipred_cfl_ac_420_w16_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_420_w16_wpad1) - L(ipred_cfl_ac_420_w16_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_420_w16_wpad2) - L(ipred_cfl_ac_420_w16_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_420_w16_wpad3) - L(ipred_cfl_ac_420_w16_tbl) + CONFIG_THUMBsub r2, r2, #32! ! ! sub r2, r2, #32! ! ! ! ! "cmp r4, #0" ! ! sub r8, r8, #27sub r8, r6, r4 // height - h_padalign 2word L(ipred_cfl_ac_422_w16) - L(ipred_cfl_ac_422_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_422_w8) - L(ipred_cfl_ac_422_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_422_w4) - L(ipred_cfl_ac_422_tbl) + CONFIG_THUMB! ! ! ! ! align 2word L(ipred_cfl_ac_422_w16_wpad0) - L(ipred_cfl_ac_422_w16_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_422_w16_wpad1) - L(ipred_cfl_ac_422_w16_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_422_w16_wpad2) - L(ipred_cfl_ac_422_w16_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_422_w16_wpad3) - L(ipred_cfl_ac_422_w16_tbl) + CONFIG_THUMBsub r2, r2, #32! ! ! ! sub r2, r2, #32! ! ! ! ! ! ! ! sub r8, r8, #26sub r8, r6, r4 // height - h_padalign 2word L(ipred_cfl_ac_444_w32) - L(ipred_cfl_ac_444_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_444_w16) - L(ipred_cfl_ac_444_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_444_w8) - L(ipred_cfl_ac_444_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_444_w4) - L(ipred_cfl_ac_444_tbl) + CONFIG_THUMB! ! ! ! ! ! ! align 2word L(ipred_cfl_ac_444_w32_wpad0) - L(ipred_cfl_ac_444_w32_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_444_w32_wpad2) - L(ipred_cfl_ac_444_w32_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_444_w32_wpad4) - L(ipred_cfl_ac_444_w32_tbl) + CONFIG_THUMBword L(ipred_cfl_ac_444_w32_wpad6) - L(ipred_cfl_ac_444_w32_tbl) + CONFIG_THUMBsub r2, r2, #32! ! ! sub r2, r2, #32! ! ! ! ! ! ! "cmp r4, #0" ! !
Messung V0.5 in Prozent C=94 H=99 G=96
