/* SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, copy, * modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Copyright: * 2018-2020 Evan Nemerson <evan@nemerson.com> * 2020 Michael R. Crusoe <crusoe@debian.org> #include "sse.h" #if !defined (SIMDE_X86_AVX_H)#define SIMDE_X86_AVX_H#include "sse4.2.h" typedef union {#if defined (SIMDE_VECTOR_SUBSCRIPT)#if defined (SIMDE_HAVE_INT128_)#endif #else sizeof (int_fast32_t)];sizeof (uint_fast32_t)];#if defined (SIMDE_HAVE_INT128_)#endif #endif #if defined (SIMDE_X86_AVX_NATIVE)#elif defined (SIMDE_POWER_ALTIVEC_P6_NATIVE)unsigned char ) altivec_u8[2];unsigned short ) altivec_u16[2];unsigned int ) altivec_u32[2];signed char ) altivec_i8[2];signed short ) altivec_i16[2];int ) altivec_i32[2];float ) altivec_f32[2];#if defined (SIMDE_POWER_ALTIVEC_P7_NATIVE)unsigned long long ) altivec_u64[2];long long ) altivec_i64[2];double ) altivec_f64[2];#endif #endif typedef union {#if defined (SIMDE_VECTOR_SUBSCRIPT)#if defined (SIMDE_HAVE_INT128_)#endif #else #if defined (SIMDE_HAVE_INT128_)#endif sizeof (int_fast32_t)];sizeof (uint_fast32_t)];#endif #if defined (SIMDE_X86_AVX_NATIVE)#elif defined (SIMDE_POWER_ALTIVEC_P6_NATIVE)unsigned char ) altivec_u8[2];unsigned short ) altivec_u16[2];unsigned int ) altivec_u32[2];signed char ) altivec_i8[2];signed short ) altivec_i16[2];signed int ) altivec_i32[2];float ) altivec_f32[2];#if defined (SIMDE_POWER_ALTIVEC_P7_NATIVE)unsigned long long ) altivec_u64[2];signed long long ) altivec_i64[2];double ) altivec_f64[2];#endif #endif typedef union {#if defined (SIMDE_VECTOR_SUBSCRIPT)#if defined (SIMDE_HAVE_INT128_)#endif #else sizeof (int_fast32_t)];sizeof (uint_fast32_t)];#if defined (SIMDE_HAVE_INT128_)#endif #endif #if defined (SIMDE_X86_AVX_NATIVE)#elif defined (SIMDE_POWER_ALTIVEC_P6_NATIVE)unsigned char ) altivec_u8[2];unsigned short ) altivec_u16[2];unsigned int ) altivec_u32[2];signed char ) altivec_i8[2];signed short ) altivec_i16[2];signed int ) altivec_i32[2];float ) altivec_f32[2];#if defined (SIMDE_POWER_ALTIVEC_P7_NATIVE)unsigned long long ) altivec_u64[2];signed long long ) altivec_i64[2];double ) altivec_f64[2];#endif #endif #if defined (SIMDE_X86_AVX_NATIVE)typedef __m256 simde__m256;typedef __m256i simde__m256i;typedef __m256d simde__m256d;#elif defined (SIMDE_VECTOR_SUBSCRIPT)typedef simde_float32 simde__m256 SIMDE_ALIGN_TO_32 SIMDE_VECTOR(32) SIMDE_MAY_ALIAS;typedef int_fast32_t simde__m256i SIMDE_ALIGN_TO_32 SIMDE_VECTOR(32) SIMDE_MAY_ALIAS;typedef simde_float64 simde__m256d SIMDE_ALIGN_TO_32 SIMDE_VECTOR(32) SIMDE_MAY_ALIAS;#else typedef simde__m256_private simde__m256;typedef simde__m256i_private simde__m256i;typedef simde__m256d_private simde__m256d;#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#if !defined (HEDLEY_INTEL_VERSION) && !defined (_AVXINTRIN_H_INCLUDED) && !defined (__AVXINTRIN_H) && !defined (_CMP_EQ_OQ)typedef simde__m256 __m256;typedef simde__m256i __m256i;typedef simde__m256d __m256d;#else #undef __m256#define __m256 simde__m256#undef __m256i#define __m256i simde__m256i#undef __m256d#define __m256d simde__m256d#endif #endif sizeof (simde__m256), "simde__m256 size incorrect" );sizeof (simde__m256_private), "simde__m256_private size incorrect" );sizeof (simde__m256i), "simde__m256i size incorrect" );sizeof (simde__m256i_private), "simde__m256i_private size incorrect" );sizeof (simde__m256d), "simde__m256d size incorrect" );sizeof (simde__m256d_private), "simde__m256d_private size incorrect" );#if defined (SIMDE_CHECK_ALIGNMENT) && defined (SIMDE_ALIGN_OF)"simde__m256 is not 32-byte aligned" );"simde__m256_private is not 32-byte aligned" );"simde__m256i is not 32-byte aligned" );"simde__m256i_private is not 32-byte aligned" );"simde__m256d is not 32-byte aligned" );"simde__m256d_private is not 32-byte aligned" );#endif sizeof (r));return r;sizeof (r));return r;sizeof (r));return r;sizeof (r));return r;sizeof (r));return r;sizeof (r));return r;#define SIMDE_CMP_EQ_OQ 0#define SIMDE_CMP_LT_OS 1#define SIMDE_CMP_LE_OS 2#define SIMDE_CMP_UNORD_Q 3#define SIMDE_CMP_NEQ_UQ 4#define SIMDE_CMP_NLT_US 5#define SIMDE_CMP_NLE_US 6#define SIMDE_CMP_ORD_Q 7#define SIMDE_CMP_EQ_UQ 8#define SIMDE_CMP_NGE_US 9#define SIMDE_CMP_NGT_US 10#define SIMDE_CMP_FALSE_OQ 11#define SIMDE_CMP_NEQ_OQ 12#define SIMDE_CMP_GE_OS 13#define SIMDE_CMP_GT_OS 14#define SIMDE_CMP_TRUE_UQ 15#define SIMDE_CMP_EQ_OS 16#define SIMDE_CMP_LT_OQ 17#define SIMDE_CMP_LE_OQ 18#define SIMDE_CMP_UNORD_S 19#define SIMDE_CMP_NEQ_US 20#define SIMDE_CMP_NLT_UQ 21#define SIMDE_CMP_NLE_UQ 22#define SIMDE_CMP_ORD_S 23#define SIMDE_CMP_EQ_US 24#define SIMDE_CMP_NGE_UQ 25#define SIMDE_CMP_NGT_UQ 26#define SIMDE_CMP_FALSE_OS 27#define SIMDE_CMP_NEQ_OS 28#define SIMDE_CMP_GE_OQ 29#define SIMDE_CMP_GT_OQ 30#define SIMDE_CMP_TRUE_US 31#if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES) && !defined (_CMP_EQ_OQ)#define _CMP_EQ_OQ SIMDE_CMP_EQ_OQ#define _CMP_LT_OS SIMDE_CMP_LT_OS#define _CMP_LE_OS SIMDE_CMP_LE_OS#define _CMP_UNORD_Q SIMDE_CMP_UNORD_Q#define _CMP_NEQ_UQ SIMDE_CMP_NEQ_UQ#define _CMP_NLT_US SIMDE_CMP_NLT_US#define _CMP_NLE_US SIMDE_CMP_NLE_US#define _CMP_ORD_Q SIMDE_CMP_ORD_Q#define _CMP_EQ_UQ SIMDE_CMP_EQ_UQ#define _CMP_NGE_US SIMDE_CMP_NGE_US#define _CMP_NGT_US SIMDE_CMP_NGT_US#define _CMP_FALSE_OQ SIMDE_CMP_FALSE_OQ#define _CMP_NEQ_OQ SIMDE_CMP_NEQ_OQ#define _CMP_GE_OS SIMDE_CMP_GE_OS#define _CMP_GT_OS SIMDE_CMP_GT_OS#define _CMP_TRUE_UQ SIMDE_CMP_TRUE_UQ#define _CMP_EQ_OS SIMDE_CMP_EQ_OS#define _CMP_LT_OQ SIMDE_CMP_LT_OQ#define _CMP_LE_OQ SIMDE_CMP_LE_OQ#define _CMP_UNORD_S SIMDE_CMP_UNORD_S#define _CMP_NEQ_US SIMDE_CMP_NEQ_US#define _CMP_NLT_UQ SIMDE_CMP_NLT_UQ#define _CMP_NLE_UQ SIMDE_CMP_NLE_UQ#define _CMP_ORD_S SIMDE_CMP_ORD_S#define _CMP_EQ_US SIMDE_CMP_EQ_US#define _CMP_NGE_UQ SIMDE_CMP_NGE_UQ#define _CMP_NGT_UQ SIMDE_CMP_NGT_UQ#define _CMP_FALSE_OS SIMDE_CMP_FALSE_OS#define _CMP_NEQ_OS SIMDE_CMP_NEQ_OS#define _CMP_GE_OQ SIMDE_CMP_GE_OQ#define _CMP_GT_OQ SIMDE_CMP_GT_OQ#define _CMP_TRUE_US SIMDE_CMP_TRUE_US#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_castps_pd(a);#else return *HEDLEY_REINTERPRET_CAST(simde__m256d*, &a);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_castps_pd#define _mm256_castps_pd(a) simde_mm256_castps_pd(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_castps_si256(a);#else return *HEDLEY_REINTERPRET_CAST(simde__m256i*, &a);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_castps_si256#define _mm256_castps_si256(a) simde_mm256_castps_si256(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_castsi256_pd(a);#else return *HEDLEY_REINTERPRET_CAST(simde__m256d*, &a);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_castsi256_pd#define _mm256_castsi256_pd(a) simde_mm256_castsi256_pd(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_castsi256_ps(a);#else return *HEDLEY_REINTERPRET_CAST(simde__m256*, &a);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_castsi256_ps#define _mm256_castsi256_ps(a) simde_mm256_castsi256_ps(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_castpd_ps(a);#else return *HEDLEY_REINTERPRET_CAST(simde__m256*, &a);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_castpd_ps#define _mm256_castpd_ps(a) simde_mm256_castpd_ps(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_castpd_si256(a);#else return *HEDLEY_REINTERPRET_CAST(simde__m256i*, &a);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_castpd_si256#define _mm256_castpd_si256(a) simde_mm256_castpd_si256(a)#endif void ) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_setzero_si256();#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.i32f) / sizeof (r_.i32f[0])) ; i++) {#endif return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_setzero_si256#define _mm256_setzero_si256() simde_mm256_setzero_si256()#endif void ) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_setzero_ps();#else return simde_mm256_castsi256_ps(simde_mm256_setzero_si256());#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_setzero_ps#define _mm256_setzero_ps() simde_mm256_setzero_ps()#endif void ) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_setzero_pd();#else return simde_mm256_castsi256_pd(simde_mm256_setzero_si256());#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_setzero_pd#define _mm256_setzero_pd() simde_mm256_setzero_pd()#endif #if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#elif SIMDE_NATURAL_VECTOR_SIZE_GE(128)#else for (size_t i = 0 ; i < (sizeof (r_.i32) / sizeof (r_.i32[0])) ; i++) {#endif return simde__m256_from_private(r_);/* This function is for when you want to blend two elements together * according to a mask. It is similar to _mm256_blendv_ps, except that * it is undefined whether the blend is based on the highest bit in * each lane (like blendv) or just bitwise operations. This allows * us to implement the function efficiently everywhere. * * Basically, you promise that all the lanes in mask are either 0 or #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_blendv_ps(a, b, mask);#else #if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#elif SIMDE_NATURAL_VECTOR_SIZE_GE(128)#else for (size_t i = 0 ; i < (sizeof (r_.i32) / sizeof (r_.i32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#elif SIMDE_NATURAL_VECTOR_SIZE_GE(128)#else for (size_t i = 0 ; i < (sizeof (r_.i64) / sizeof (r_.i64[0])) ; i++) {#endif return simde__m256d_from_private(r_);/* This function is for when you want to blend two elements together * according to a mask. It is similar to _mm256_blendv_pd, except that * it is undefined whether the blend is based on the highest bit in * each lane (like blendv) or just bitwise operations. This allows * us to implement the function efficiently everywhere. * * Basically, you promise that all the lanes in mask are either 0 or #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_blendv_pd(a, b, mask);#else #if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#elif SIMDE_NATURAL_VECTOR_SIZE_GE(128)#else for (size_t i = 0 ; i < (sizeof (r_.i64) / sizeof (r_.i64[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif void ) {#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#elif defined (SIMDE_X86_AVX2_NATIVE)#else for (size_t i = 0 ; i < (sizeof (r_.i32f) / sizeof (r_.i32f[0])) ; i++) {#endif return simde__m256i_from_private(r_);void ) {return simde_mm256_castsi256_ps(simde_x_mm256_setone_si256());void ) {return simde_mm256_castsi256_pd(simde_x_mm256_setone_si256());#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set_epi8(e31, e30, e29, e28, e27, e26, e25, e24,#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else #endif return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set_epi8#define _mm256_set_epi8(e31, e30, e29, e28, e27, e26, e25, e24, e23, e22, e21, e20, e19, e18, e17, e16, e15, e14, e13, e12, e11, e10, e9, e8, e7, e6, e5, e4, e3, e2, e1, e0) \, e16, e15, e14, e13, e12, e11, e10, e9, e8, e7, e6, e5, e4, e3, e2, e1, e0)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set_epi16(e15, e14, e13, e12, e11, e10, e9, e8,#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else #endif return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set_epi16#define _mm256_set_epi16(e15, e14, e13, e12, e11, e10, e9, e8, e7, e6, e5, e4, e3, e2, e1, e0) \#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set_epi32(e7, e6, e5, e4, e3, e2, e1, e0);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else #endif return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set_epi32#define _mm256_set_epi32(e7, e6, e5, e4, e3, e2, e1, e0) \#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set_epi64x(e3, e2, e1, e0);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else #endif return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set_epi64x#define _mm256_set_epi64x(e3, e2, e1, e0) simde_mm256_set_epi64x(e3, e2, e1, e0)#endif return simde__m256i_from_private(r_);return simde__m256i_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set_epi32(HEDLEY_STATIC_CAST(int32_t, e7), HEDLEY_STATIC_CAST(int32_t, e6), HEDLEY_STATIC_CAST(int32_t, e5), HEDLEY_STATIC_CAST(int32_t, e4),(int32_t, e1), HEDLEY_STATIC_CAST(int32_t, e0));#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)(int32_t, e2), HEDLEY_STATIC_CAST(int32_t, e1), HEDLEY_STATIC_CAST(int32_t, e0));(int32_t, e6), HEDLEY_STATIC_CAST(int32_t, e5), HEDLEY_STATIC_CAST(int32_t, e4));#else #endif return simde__m256i_from_private(r_);#endif return simde__m256i_from_private(r_);e4,#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set_ps(e7, e6, e5, e4, e3, e2, e1, e0);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else #endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set_ps#define _mm256_set_ps(e7, e6, e5, e4, e3, e2, e1, e0) \#endif e0) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set_pd(e3, e2, e1, e0);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else #endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set_pd#define _mm256_set_pd(e3, e2, e1, e0) \#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_insertf128_ps(_mm256_castps128_ps256(e0), e1, 1);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_HAVE_INT128_)#else #endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set_m128#define _mm256_set_m128(e1, e0) simde_mm256_set_m128(e1, e0)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_insertf128_pd(_mm256_castpd128_pd256(e0), e1, 1);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else #endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set_m128d#define _mm256_set_m128d(e1, e0) simde_mm256_set_m128d(e1, e0)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_insertf128_si256(_mm256_castsi128_si256(e0), e1, 1);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else #endif return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set_m128i#define _mm256_set_m128i(e1, e0) simde_mm256_set_m128i(e1, e0)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set1_epi8(a);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.i8) / sizeof (r_.i8[0])) ; i++) {#endif return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set1_epi8#define _mm256_set1_epi8(a) simde_mm256_set1_epi8(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set1_epi16(a);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.i16) / sizeof (r_.i16[0])) ; i++) {#endif return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set1_epi16#define _mm256_set1_epi16(a) simde_mm256_set1_epi16(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set1_epi32(a);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.i32) / sizeof (r_.i32[0])) ; i++) {#endif return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set1_epi32#define _mm256_set1_epi32(a) simde_mm256_set1_epi32(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set1_epi64x(a);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.i64) / sizeof (r_.i64[0])) ; i++) {#endif return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set1_epi64x#define _mm256_set1_epi64x(a) simde_mm256_set1_epi64x(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set1_ps(a);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set1_ps#define _mm256_set1_ps(a) simde_mm256_set1_ps(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_set1_pd(a);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_set1_pd#define _mm256_set1_pd(a) simde_mm256_set1_pd(a)#endif #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_SHUFFLE_VECTOR_)24, 26, 28, 30);#else const size_t halfway_point = (sizeof (r_.i16) / sizeof (r_.i16[0])) / 2;const size_t quarter_point = (sizeof (r_.i16) / sizeof (r_.i16[0])) / 4;for (size_t i = 0 ; i < quarter_point ; i++) {#endif return simde__m256i_from_private(r_);#if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_SHUFFLE_VECTOR_)25, 27, 29, 31);#else const size_t halfway_point = (sizeof (r_.i16) / sizeof (r_.i16[0])) / 2;const size_t quarter_point = (sizeof (r_.i16) / sizeof (r_.i16[0])) / 4;for (size_t i = 0 ; i < quarter_point ; i++) {#endif return simde__m256i_from_private(r_);#if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_SHUFFLE_VECTOR_)#else const size_t halfway_point = (sizeof (r_.i32) / sizeof (r_.i32[0])) / 2;const size_t quarter_point = (sizeof (r_.i32) / sizeof (r_.i32[0])) / 4;for (size_t i = 0 ; i < quarter_point ; i++) {#endif return simde__m256i_from_private(r_);#if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_SHUFFLE_VECTOR_)#else const size_t halfway_point = (sizeof (r_.i32) / sizeof (r_.i32[0])) / 2;const size_t quarter_point = (sizeof (r_.i32) / sizeof (r_.i32[0])) / 4;for (size_t i = 0 ; i < quarter_point ; i++) {#endif return simde__m256i_from_private(r_);#if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_SHUFFLE_VECTOR_)#else const size_t halfway_point = (sizeof (r_.f32) / sizeof (r_.f32[0])) / 2;const size_t quarter_point = (sizeof (r_.f32) / sizeof (r_.f32[0])) / 4;for (size_t i = 0 ; i < quarter_point ; i++) {#endif return simde__m256_from_private(r_);#if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_SHUFFLE_VECTOR_)#else const size_t halfway_point = (sizeof (r_.f32) / sizeof (r_.f32[0])) / 2;const size_t quarter_point = (sizeof (r_.f32) / sizeof (r_.f32[0])) / 4;for (size_t i = 0 ; i < quarter_point ; i++) {#endif return simde__m256_from_private(r_);#if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_SHUFFLE_VECTOR_)#else const size_t halfway_point = (sizeof (r_.f64) / sizeof (r_.f64[0])) / 2;const size_t quarter_point = (sizeof (r_.f64) / sizeof (r_.f64[0])) / 4;for (size_t i = 0 ; i < quarter_point ; i++) {#endif return simde__m256d_from_private(r_);#if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_SHUFFLE_VECTOR_)#else const size_t halfway_point = (sizeof (r_.f64) / sizeof (r_.f64[0])) / 2;const size_t quarter_point = (sizeof (r_.f64) / sizeof (r_.f64[0])) / 4;for (size_t i = 0 ; i < quarter_point ; i++) {#endif return simde__m256d_from_private(r_);for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {return simde__m256_from_private(r_);for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {return simde__m256d_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_add_ps(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_add_ps#define _mm256_add_ps(a, b) simde_mm256_add_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_hadd_ps(a, b);#else return simde_mm256_add_ps(simde_x_mm256_deinterleaveeven_ps(a, b), simde_x_mm256_deinterleaveodd_ps(a, b));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_hadd_ps#define _mm256_hadd_ps(a, b) simde_mm256_hadd_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_add_pd(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_add_pd#define _mm256_add_pd(a, b) simde_mm256_add_pd(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_hadd_pd(a, b);#else return simde_mm256_add_pd(simde_x_mm256_deinterleaveeven_pd(a, b), simde_x_mm256_deinterleaveodd_pd(a, b));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_hadd_pd#define _mm256_hadd_pd(a, b) simde_mm256_hadd_pd(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_addsub_ps(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i += 2) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_addsub_ps#define _mm256_addsub_ps(a, b) simde_mm256_addsub_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_addsub_pd(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i += 2) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_addsub_pd#define _mm256_addsub_pd(a, b) simde_mm256_addsub_pd(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_and_ps(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.i32f) / sizeof (r_.i32f[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_and_ps#define _mm256_and_ps(a, b) simde_mm256_and_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_and_pd(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.i32f) / sizeof (r_.i32f[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_and_pd#define _mm256_and_pd(a, b) simde_mm256_and_pd(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_andnot_ps(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.i32f) / sizeof (r_.i32f[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_andnot_ps#define _mm256_andnot_ps(a, b) simde_mm256_andnot_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_andnot_pd(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.i32f) / sizeof (r_.i32f[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_andnot_pd#define _mm256_andnot_pd(a, b) simde_mm256_andnot_pd(a, b)#endif const int imm8)for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {return simde__m256_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm256_blend_ps(a, b, imm8) _mm256_blend_ps(a, b, imm8)#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128)# define simde_mm256_blend_ps(a, b, imm8) \), (imm8) >> 4), \), (imm8) & 0x0F))#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_blend_ps#define _mm256_blend_ps(a, b, imm8) simde_mm256_blend_ps(a, b, imm8)#endif const int imm8)for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {return simde__m256d_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm256_blend_pd(a, b, imm8) _mm256_blend_pd(a, b, imm8)#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128)# define simde_mm256_blend_pd(a, b, imm8) \), (imm8) >> 2), \), (imm8) & 3))#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_blend_pd#define _mm256_blend_pd(a, b, imm8) simde_mm256_blend_pd(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_blendv_ps(a, b, mask);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.u32) / sizeof (r_.u32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_blendv_ps#define _mm256_blendv_ps(a, b, imm8) simde_mm256_blendv_ps(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_blendv_pd(a, b, mask);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.u64) / sizeof (r_.u64[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_blendv_pd#define _mm256_blendv_pd(a, b, imm8) simde_mm256_blendv_pd(a, b, imm8)#endif const * mem_addr) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_broadcast_pd(mem_addr);#else const *, mem_addr));return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_broadcast_pd#define _mm256_broadcast_pd(mem_addr) simde_mm256_broadcast_pd(mem_addr)#endif const * mem_addr) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_broadcast_ps(mem_addr);#else const *, mem_addr));return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_broadcast_ps#define _mm256_broadcast_ps(mem_addr) simde_mm256_broadcast_ps(HEDLEY_REINTERPRET_CAST(simde__m128 const *, mem_addr))#endif const * a) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_broadcast_sd(a);#else return simde_mm256_set1_pd(*a);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_broadcast_sd#define _mm256_broadcast_sd(mem_addr) simde_mm256_broadcast_sd(HEDLEY_REINTERPRET_CAST(double const *, mem_addr))#endif const * a) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm_broadcast_ss(a);#elif defined (SIMDE_WASM_SIMD128_NATIVE)return simde__m128_from_wasm_v128(wasm_v128_load32_splat(a));#else return simde_mm_set1_ps(*a);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_broadcast_ss#define _mm_broadcast_ss(mem_addr) simde_mm_broadcast_ss(mem_addr)#endif const * a) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_broadcast_ss(a);#else return simde_mm256_set1_ps(*a);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_broadcast_ss#define _mm256_broadcast_ss(mem_addr) simde_mm256_broadcast_ss(mem_addr)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_castpd128_pd256(a);#else return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_castpd128_pd256#define _mm256_castpd128_pd256(a) simde_mm256_castpd128_pd256(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_castpd256_pd128(a);#else return a_.m128d[0];#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_castpd256_pd128#define _mm256_castpd256_pd128(a) simde_mm256_castpd256_pd128(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_castps128_ps256(a);#else return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_castps128_ps256#define _mm256_castps128_ps256(a) simde_mm256_castps128_ps256(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_castps256_ps128(a);#else return a_.m128[0];#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_castps256_ps128#define _mm256_castps256_ps128(a) simde_mm256_castps256_ps128(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_castsi128_si256(a);#else return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_castsi128_si256#define _mm256_castsi128_si256(a) simde_mm256_castsi128_si256(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_castsi256_si128(a);#else return a_.m128i[0];#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_castsi256_si128#define _mm256_castsi256_si128(a) simde_mm256_castsi256_si128(a)#endif const int rounding) {switch (rounding & ~SIMDE_MM_FROUND_NO_EXC) {#if defined (simde_math_nearbyintf)case SIMDE_MM_FROUND_CUR_DIRECTION:for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {break ;#endif #if defined (simde_math_roundf)case SIMDE_MM_FROUND_TO_NEAREST_INT:for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {break ;#endif #if defined (simde_math_floorf)case SIMDE_MM_FROUND_TO_NEG_INF:for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {break ;#endif #if defined (simde_math_ceilf)case SIMDE_MM_FROUND_TO_POS_INF:for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {break ;#endif #if defined (simde_math_truncf)case SIMDE_MM_FROUND_TO_ZERO:for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {break ;#endif default :return simde__m256_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)#define simde_mm256_round_ps(a, rounding) _mm256_round_ps(a, rounding)#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) && defined (SIMDE_STATEMENT_EXPR_)#define simde_mm256_round_ps(a, rounding) SIMDE_STATEMENT_EXPR_(({ \for (size_t simde_mm256_round_ps_i = 0 ; simde_mm256_round_ps_i < (sizeof (simde_mm256_round_ps_r_.m128) / sizeof (simde_mm256_round_ps_r_.m128[0])) ; simde_mm256_round_ps_i++) { \56_round_ps_a_.m128[simde_mm256_round_ps_i], rounding); \#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_round_ps#define _mm256_round_ps(a, rounding) simde_mm256_round_ps(a, rounding)#endif const int rounding) {switch (rounding & ~SIMDE_MM_FROUND_NO_EXC) {#if defined (simde_math_nearbyint)case SIMDE_MM_FROUND_CUR_DIRECTION:for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {break ;#endif #if defined (simde_math_round)case SIMDE_MM_FROUND_TO_NEAREST_INT:for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {break ;#endif #if defined (simde_math_floor)case SIMDE_MM_FROUND_TO_NEG_INF:for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {break ;#endif #if defined (simde_math_ceil)case SIMDE_MM_FROUND_TO_POS_INF:for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {break ;#endif #if defined (simde_math_trunc)case SIMDE_MM_FROUND_TO_ZERO:for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {break ;#endif default :return simde__m256d_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)#define simde_mm256_round_pd(a, rounding) _mm256_round_pd(a, rounding)#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) && defined (SIMDE_STATEMENT_EXPR_)#define simde_mm256_round_pd(a, rounding) SIMDE_STATEMENT_EXPR_(({ \for (size_t simde_mm256_round_pd_i = 0 ; simde_mm256_round_pd_i < (sizeof (simde_mm256_round_pd_r_.m128d) / sizeof (simde_mm256_round_pd_r_.m128d[0])) ; simde_mm256_round_pd_i++) { \256_round_pd_a_.m128d[simde_mm256_round_pd_i], rounding); \#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_round_pd#define _mm256_round_pd(a, rounding) simde_mm256_round_pd(a, rounding)#endif return simde_mm256_round_pd(a, SIMDE_MM_FROUND_TO_POS_INF);#if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_ceil_pd#define _mm256_ceil_pd(a) simde_mm256_ceil_pd(a)#endif return simde_mm256_round_ps(a, SIMDE_MM_FROUND_TO_POS_INF);#if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_ceil_ps#define _mm256_ceil_ps(a) simde_mm256_ceil_ps(a)#endif /* This implementation does not support signaling NaNs (yet?) */ const int imm8)switch (imm8) {case SIMDE_CMP_EQ_UQ:case SIMDE_CMP_EQ_US:return simde_mm_or_pd(simde_mm_cmpunord_pd(a, b), simde_mm_cmpeq_pd(a, b));break ;case SIMDE_CMP_EQ_OQ:case SIMDE_CMP_EQ_OS:return simde_mm_cmpeq_pd(a, b);break ;case SIMDE_CMP_NGE_US:case SIMDE_CMP_NGE_UQ:return simde_x_mm_not_pd(simde_mm_cmpge_pd(a, b));break ;case SIMDE_CMP_LT_OS:case SIMDE_CMP_LT_OQ:return simde_mm_cmplt_pd(a, b);break ;case SIMDE_CMP_NGT_US:case SIMDE_CMP_NGT_UQ:return simde_x_mm_not_pd(simde_mm_cmpgt_pd(a, b));break ;case SIMDE_CMP_LE_OS:case SIMDE_CMP_LE_OQ:return simde_mm_cmple_pd(a, b);break ;case SIMDE_CMP_NEQ_UQ:case SIMDE_CMP_NEQ_US:return simde_mm_cmpneq_pd(a, b);break ;case SIMDE_CMP_NEQ_OQ:case SIMDE_CMP_NEQ_OS:return simde_mm_and_pd(simde_mm_cmpord_pd(a, b), simde_mm_cmpneq_pd(a, b));break ;case SIMDE_CMP_NLT_US:case SIMDE_CMP_NLT_UQ:return simde_x_mm_not_pd(simde_mm_cmplt_pd(a, b));break ;case SIMDE_CMP_GE_OS:case SIMDE_CMP_GE_OQ:return simde_mm_cmpge_pd(a, b);break ;case SIMDE_CMP_NLE_US:case SIMDE_CMP_NLE_UQ:return simde_x_mm_not_pd(simde_mm_cmple_pd(a, b));break ;case SIMDE_CMP_GT_OS:case SIMDE_CMP_GT_OQ:return simde_mm_cmpgt_pd(a, b);break ;case SIMDE_CMP_FALSE_OQ:case SIMDE_CMP_FALSE_OS:return simde_mm_setzero_pd();break ;case SIMDE_CMP_TRUE_UQ:case SIMDE_CMP_TRUE_US:return simde_x_mm_setone_pd();break ;case SIMDE_CMP_UNORD_Q:case SIMDE_CMP_UNORD_S:return simde_mm_cmpunord_pd(a, b);break ;case SIMDE_CMP_ORD_Q:case SIMDE_CMP_ORD_S:return simde_mm_cmpord_pd(a, b);break ;#if defined (__clang__) && defined (__AVX512DQ__)#define simde_mm_cmp_pd(a, b, imm8) (__extension__ ({ \switch (imm8) { \case SIMDE_CMP_FALSE_OQ: \case SIMDE_CMP_FALSE_OS: \break ; \case SIMDE_CMP_TRUE_UQ: \case SIMDE_CMP_TRUE_US: \break ; \default : \break ; \#elif defined (SIMDE_X86_AVX_NATIVE)# define simde_mm_cmp_pd(a, b, imm8) _mm_cmp_pd(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_cmp_pd#define _mm_cmp_pd(a, b, imm8) simde_mm_cmp_pd(a, b, imm8)#endif const int imm8)switch (imm8) {case SIMDE_CMP_EQ_UQ:case SIMDE_CMP_EQ_US:return simde_mm_or_ps(simde_mm_cmpunord_ps(a, b), simde_mm_cmpeq_ps(a, b));break ;case SIMDE_CMP_EQ_OQ:case SIMDE_CMP_EQ_OS:return simde_mm_cmpeq_ps(a, b);break ;case SIMDE_CMP_NGE_US:case SIMDE_CMP_NGE_UQ:return simde_x_mm_not_ps(simde_mm_cmpge_ps(a, b));break ;case SIMDE_CMP_LT_OS:case SIMDE_CMP_LT_OQ:return simde_mm_cmplt_ps(a, b);break ;case SIMDE_CMP_NGT_US:case SIMDE_CMP_NGT_UQ:return simde_x_mm_not_ps(simde_mm_cmpgt_ps(a, b));break ;case SIMDE_CMP_LE_OS:case SIMDE_CMP_LE_OQ:return simde_mm_cmple_ps(a, b);break ;case SIMDE_CMP_NEQ_UQ:case SIMDE_CMP_NEQ_US:return simde_mm_cmpneq_ps(a, b);break ;case SIMDE_CMP_NEQ_OQ:case SIMDE_CMP_NEQ_OS:return simde_mm_and_ps(simde_mm_cmpord_ps(a, b), simde_mm_cmpneq_ps(a, b));break ;case SIMDE_CMP_NLT_US:case SIMDE_CMP_NLT_UQ:return simde_x_mm_not_ps(simde_mm_cmplt_ps(a, b));break ;case SIMDE_CMP_GE_OS:case SIMDE_CMP_GE_OQ:return simde_mm_cmpge_ps(a, b);break ;case SIMDE_CMP_NLE_US:case SIMDE_CMP_NLE_UQ:return simde_x_mm_not_ps(simde_mm_cmple_ps(a, b));break ;case SIMDE_CMP_GT_OS:case SIMDE_CMP_GT_OQ:return simde_mm_cmpgt_ps(a, b);break ;case SIMDE_CMP_FALSE_OQ:case SIMDE_CMP_FALSE_OS:return simde_mm_setzero_ps();break ;case SIMDE_CMP_TRUE_UQ:case SIMDE_CMP_TRUE_US:return simde_x_mm_setone_ps();break ;case SIMDE_CMP_UNORD_Q:case SIMDE_CMP_UNORD_S:return simde_mm_cmpunord_ps(a, b);break ;case SIMDE_CMP_ORD_Q:case SIMDE_CMP_ORD_S:return simde_mm_cmpord_ps(a, b);break ;/* Prior to 9.0 clang has problems with _mm{,256}_cmp_{ps,pd} for all four of the true/false #if defined (__clang__) && defined (__AVX512DQ__)#define simde_mm_cmp_ps(a, b, imm8) (__extension__ ({ \switch (imm8) { \case SIMDE_CMP_FALSE_OQ: \case SIMDE_CMP_FALSE_OS: \break ; \case SIMDE_CMP_TRUE_UQ: \case SIMDE_CMP_TRUE_US: \break ; \default : \break ; \#elif defined (SIMDE_X86_AVX_NATIVE)#define simde_mm_cmp_ps(a, b, imm8) _mm_cmp_ps(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_cmp_ps#define _mm_cmp_ps(a, b, imm8) simde_mm_cmp_ps(a, b, imm8)#endif const int imm8)switch (imm8) {case SIMDE_CMP_EQ_OQ:case SIMDE_CMP_EQ_OS:break ;case SIMDE_CMP_LT_OQ:case SIMDE_CMP_LT_OS:break ;case SIMDE_CMP_LE_OQ:case SIMDE_CMP_LE_OS:break ;case SIMDE_CMP_UNORD_Q:case SIMDE_CMP_UNORD_S:);break ;case SIMDE_CMP_NEQ_UQ:case SIMDE_CMP_NEQ_US:f64[0])) ? ~INT64_C(0) : INT64_C(0);break ;case SIMDE_CMP_NEQ_OQ:case SIMDE_CMP_NEQ_OS:f64[0])) ? ~INT64_C(0) : INT64_C(0);break ;case SIMDE_CMP_NLT_UQ:case SIMDE_CMP_NLT_US:break ;case SIMDE_CMP_NLE_UQ:case SIMDE_CMP_NLE_US:break ;case SIMDE_CMP_ORD_Q:case SIMDE_CMP_ORD_S:C(0);break ;case SIMDE_CMP_EQ_UQ:case SIMDE_CMP_EQ_US:? ~INT64_C(0) : INT64_C(0);break ;case SIMDE_CMP_NGE_UQ:case SIMDE_CMP_NGE_US:break ;case SIMDE_CMP_NGT_UQ:case SIMDE_CMP_NGT_US:break ;case SIMDE_CMP_FALSE_OQ:case SIMDE_CMP_FALSE_OS:break ;case SIMDE_CMP_GE_OQ:case SIMDE_CMP_GE_OS:break ;case SIMDE_CMP_GT_OQ:case SIMDE_CMP_GT_OS:break ;case SIMDE_CMP_TRUE_UQ:case SIMDE_CMP_TRUE_US:break ;default :return simde__m128d_from_private(a_);#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm_cmp_sd(a, b, imm8) _mm_cmp_sd(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_cmp_sd#define _mm_cmp_sd(a, b, imm8) simde_mm_cmp_sd(a, b, imm8)#endif const int imm8)switch (imm8) {case SIMDE_CMP_EQ_OQ:case SIMDE_CMP_EQ_OS:break ;case SIMDE_CMP_LT_OQ:case SIMDE_CMP_LT_OS:break ;case SIMDE_CMP_LE_OQ:case SIMDE_CMP_LE_OS:break ;case SIMDE_CMP_UNORD_Q:case SIMDE_CMP_UNORD_S:);break ;case SIMDE_CMP_NEQ_UQ:case SIMDE_CMP_NEQ_US:f32[0])) ? ~INT32_C(0) : INT32_C(0);break ;case SIMDE_CMP_NEQ_OQ:case SIMDE_CMP_NEQ_OS:f32[0])) ? ~INT32_C(0) : INT32_C(0);break ;case SIMDE_CMP_NLT_UQ:case SIMDE_CMP_NLT_US:break ;case SIMDE_CMP_NLE_UQ:case SIMDE_CMP_NLE_US:break ;case SIMDE_CMP_ORD_Q:case SIMDE_CMP_ORD_S:C(0);break ;case SIMDE_CMP_EQ_UQ:case SIMDE_CMP_EQ_US:? ~INT32_C(0) : INT32_C(0);break ;case SIMDE_CMP_NGE_UQ:case SIMDE_CMP_NGE_US:break ;case SIMDE_CMP_NGT_UQ:case SIMDE_CMP_NGT_US:break ;case SIMDE_CMP_FALSE_OQ:case SIMDE_CMP_FALSE_OS:break ;case SIMDE_CMP_GE_OQ:case SIMDE_CMP_GE_OS:break ;case SIMDE_CMP_GT_OQ:case SIMDE_CMP_GT_OS:break ;case SIMDE_CMP_TRUE_UQ:case SIMDE_CMP_TRUE_US:break ;default :return simde__m128_from_private(a_);#if defined (SIMDE_X86_AVX_NATIVE)#define simde_mm_cmp_ss(a, b, imm8) _mm_cmp_ss(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_cmp_ss#define _mm_cmp_ss(a, b, imm8) simde_mm_cmp_ss(a, b, imm8)#endif #if defined (__clang__) && defined (__AVX512DQ__)#else #endif const int imm8)switch (imm8) {case SIMDE_CMP_EQ_OQ:case SIMDE_CMP_EQ_OS:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif break ;case SIMDE_CMP_LT_OQ:case SIMDE_CMP_LT_OS:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif break ;case SIMDE_CMP_LE_OQ:case SIMDE_CMP_LE_OS:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif break ;case SIMDE_CMP_UNORD_Q:case SIMDE_CMP_UNORD_S:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)64));#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {);#endif break ;case SIMDE_CMP_NEQ_UQ:case SIMDE_CMP_NEQ_US:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif break ;case SIMDE_CMP_NEQ_OQ:case SIMDE_CMP_NEQ_OS:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)b_.f64) & (a_.f64 != b_.f64));#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {f64[i])) ? ~INT32_C(0) : INT32_C(0);#endif break ;case SIMDE_CMP_NLT_UQ:case SIMDE_CMP_NLT_US:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif break ;case SIMDE_CMP_NLE_UQ:case SIMDE_CMP_NLE_US:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif break ;case SIMDE_CMP_ORD_Q:case SIMDE_CMP_ORD_S:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)= b_.f64)));#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {C(0);#endif break ;case SIMDE_CMP_EQ_UQ:case SIMDE_CMP_EQ_US:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)64) | (a_.f64 == b_.f64));#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {? ~INT32_C(0) : INT32_C(0);#endif break ;case SIMDE_CMP_NGE_UQ:case SIMDE_CMP_NGE_US:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif break ;case SIMDE_CMP_NGT_UQ:case SIMDE_CMP_NGT_US:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif break ;case SIMDE_CMP_FALSE_OQ:case SIMDE_CMP_FALSE_OS:break ;case SIMDE_CMP_GE_OQ:case SIMDE_CMP_GE_OS:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif break ;case SIMDE_CMP_GT_OQ:case SIMDE_CMP_GT_OS:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif break ;case SIMDE_CMP_TRUE_UQ:case SIMDE_CMP_TRUE_US:break ;default :return simde__m256d_from_private(r_);#if defined (__clang__) && defined (__AVX512DQ__)#define simde_mm256_cmp_pd(a, b, imm8) (__extension__ ({ \switch (imm8) { \case SIMDE_CMP_FALSE_OQ: \case SIMDE_CMP_FALSE_OS: \break ; \case SIMDE_CMP_TRUE_UQ: \case SIMDE_CMP_TRUE_US: \break ; \default : \break ; \#elif defined (SIMDE_X86_AVX_NATIVE)#define simde_mm256_cmp_pd(a, b, imm8) _mm256_cmp_pd(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cmp_pd#define _mm256_cmp_pd(a, b, imm8) simde_mm256_cmp_pd(a, b, imm8)#endif #if defined (__clang__) && defined (__AVX512DQ__)#else #endif const int imm8)switch (imm8) {case SIMDE_CMP_EQ_OQ:case SIMDE_CMP_EQ_OS:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif break ;case SIMDE_CMP_LT_OQ:case SIMDE_CMP_LT_OS:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif break ;case SIMDE_CMP_LE_OQ:case SIMDE_CMP_LE_OS:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif break ;case SIMDE_CMP_UNORD_Q:case SIMDE_CMP_UNORD_S:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)32));#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {);#endif break ;case SIMDE_CMP_NEQ_UQ:case SIMDE_CMP_NEQ_US:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif break ;case SIMDE_CMP_NEQ_OQ:case SIMDE_CMP_NEQ_OS:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)b_.f32) & (a_.f32 != b_.f32));#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {f32[i])) ? ~INT32_C(0) : INT32_C(0);#endif break ;case SIMDE_CMP_NLT_UQ:case SIMDE_CMP_NLT_US:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif break ;case SIMDE_CMP_NLE_UQ:case SIMDE_CMP_NLE_US:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif break ;case SIMDE_CMP_ORD_Q:case SIMDE_CMP_ORD_S:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)= b_.f32)));#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {C(0);#endif break ;case SIMDE_CMP_EQ_UQ:case SIMDE_CMP_EQ_US:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)32) | (a_.f32 == b_.f32));#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {? ~INT32_C(0) : INT32_C(0);#endif break ;case SIMDE_CMP_NGE_UQ:case SIMDE_CMP_NGE_US:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif break ;case SIMDE_CMP_NGT_UQ:case SIMDE_CMP_NGT_US:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif break ;case SIMDE_CMP_FALSE_OQ:case SIMDE_CMP_FALSE_OS:break ;case SIMDE_CMP_GE_OQ:case SIMDE_CMP_GE_OS:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif break ;case SIMDE_CMP_GT_OQ:case SIMDE_CMP_GT_OS:#if defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif break ;case SIMDE_CMP_TRUE_UQ:case SIMDE_CMP_TRUE_US:break ;default :return simde__m256_from_private(r_);#if defined (__clang__) && defined (__AVX512DQ__)#define simde_mm256_cmp_ps(a, b, imm8) (__extension__ ({ \switch (imm8) { \case SIMDE_CMP_FALSE_OQ: \case SIMDE_CMP_FALSE_OS: \break ; \case SIMDE_CMP_TRUE_UQ: \case SIMDE_CMP_TRUE_US: \break ; \default : \break ; \#elif defined (SIMDE_X86_AVX_NATIVE)#define simde_mm256_cmp_ps(a, b, imm8) _mm256_cmp_ps(a, b, imm8)#elif defined (SIMDE_STATEMENT_EXPR_) && SIMDE_NATURAL_VECTOR_SIZE_LE(128)#define simde_mm256_cmp_ps(a, b, imm8) SIMDE_STATEMENT_EXPR_(({ \for (size_t i = 0 ; i < (sizeof (simde_mm256_cmp_ps_r_.m128) / sizeof (simde_mm256_cmp_ps_r_.m128[0])) ; i++) { \e_mm256_cmp_ps_b_.m128[i], (imm8)); \#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cmp_ps#define _mm256_cmp_ps(a, b, imm8) simde_mm256_cmp_ps(a, b, imm8)#endif #if defined (simde_math_copysignf)for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#else imde_mm256_set1_ps(-SIMDE_FLOAT32_C(0.0)));return simde_mm256_xor_ps(simde_mm256_and_ps(sgnbit, src), simde_mm256_andnot_ps(sgnbit, dest));#endif return simde__m256_from_private(r_);#if defined (simde_math_copysign)for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#else simde_mm256_set1_pd(-SIMDE_FLOAT64_C(0.0)));return simde_mm256_xor_pd(simde_mm256_and_pd(sgnbit, src), simde_mm256_andnot_pd(sgnbit, dest));#endif return simde__m256d_from_private(r_);/* -Wfloat-equal */ #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_cvtepi32_pd(a);#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cvtepi32_pd#define _mm256_cvtepi32_pd(a) simde_mm256_cvtepi32_pd(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_cvtepi32_ps(a);#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cvtepi32_ps#define _mm256_cvtepi32_ps(a) simde_mm256_cvtepi32_ps(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_cvtpd_epi32(a);#else #if defined (simde_math_nearbyint)for (size_t i = 0 ; i < (sizeof (a_.f64) / sizeof (a_.f64[0])) ; i++) {#else #endif return simde__m128i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cvtpd_epi32#define _mm256_cvtpd_epi32(a) simde_mm256_cvtpd_epi32(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_cvtpd_ps(a);#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {return simde__m128_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cvtpd_ps#define _mm256_cvtpd_ps(a) simde_mm256_cvtpd_ps(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_cvtps_epi32(a);#else #if defined (simde_math_nearbyintf)for (size_t i = 0 ; i < (sizeof (a_.f32) / sizeof (a_.f32[0])) ; i++) {#else #endif return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cvtps_epi32#define _mm256_cvtps_epi32(a) simde_mm256_cvtps_epi32(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_cvtps_pd(a);#else for (size_t i = 0 ; i < (sizeof (a_.f32) / sizeof (a_.f32[0])) ; i++) {double , a_.f32[i]);return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cvtps_pd#define _mm256_cvtps_pd(a) simde_mm256_cvtps_pd(a)#endif #if defined (SIMDE_X86_AVX_NATIVE) && ( \return _mm256_cvtsd_f64(a);#else return a_.f64[0];#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cvtsd_f64#define _mm256_cvtsd_f64(a) simde_mm256_cvtsd_f64(a)#endif #if defined (SIMDE_X86_AVX_NATIVE) && ( \return _mm256_cvtsi256_si32(a);#else return a_.i32[0];#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cvtsi256_si32#define _mm256_cvtsi256_si32(a) simde_mm256_cvtsi256_si32(a)#endif #if defined (SIMDE_X86_AVX_NATIVE) && ( \return _mm256_cvtss_f32(a);#else return a_.f32[0];#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cvtss_f32#define _mm256_cvtss_f32(a) simde_mm256_cvtss_f32(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_cvttpd_epi32(a);#else #if defined (simde_math_trunc)for (size_t i = 0 ; i < (sizeof (a_.f64) / sizeof (a_.f64[0])) ; i++) {#else #endif return simde__m128i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cvttpd_epi32#define _mm256_cvttpd_epi32(a) simde_mm256_cvttpd_epi32(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_cvttps_epi32(a);#else #if defined (simde_math_truncf)for (size_t i = 0 ; i < (sizeof (a_.f32) / sizeof (a_.f32[0])) ; i++) {#else #endif return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_cvttps_epi32#define _mm256_cvttps_epi32(a) simde_mm256_cvttps_epi32(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_div_ps(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_div_ps#define _mm256_div_ps(a, b) simde_mm256_div_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_div_pd(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_div_pd#define _mm256_div_pd(a, b) simde_mm256_div_pd(a, b)#endif const int imm8)return a_.m128d[imm8];#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm256_extractf128_pd(a, imm8) _mm256_extractf128_pd(a, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_extractf128_pd#define _mm256_extractf128_pd(a, imm8) simde_mm256_extractf128_pd(a, imm8)#endif const int imm8)return a_.m128[imm8];#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm256_extractf128_ps(a, imm8) _mm256_extractf128_ps(a, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_extractf128_ps#define _mm256_extractf128_ps(a, imm8) simde_mm256_extractf128_ps(a, imm8)#endif const int imm8)return a_.m128i[imm8];#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm256_extractf128_si256(a, imm8) _mm256_extractf128_si256(a, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_extractf128_si256#define _mm256_extractf128_si256(a, imm8) simde_mm256_extractf128_si256(a, imm8)#endif return simde_mm256_round_pd(a, SIMDE_MM_FROUND_TO_NEG_INF);#if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_floor_pd#define _mm256_floor_pd(a) simde_mm256_floor_pd(a)#endif return simde_mm256_round_ps(a, SIMDE_MM_FROUND_TO_NEG_INF);#if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_floor_ps#define _mm256_floor_ps(a) simde_mm256_floor_ps(a)#endif const int index)return simde__m256i_from_private(a_);#if defined (SIMDE_X86_AVX_NATIVE) && \defined (HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,10,0))#define simde_mm256_insert_epi8(a, i, index) _mm256_insert_epi8(a, i, index)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_insert_epi8#define _mm256_insert_epi8(a, i, index) simde_mm256_insert_epi8(a, i, index)#endif const int index)return simde__m256i_from_private(a_);#if defined (SIMDE_X86_AVX_NATIVE) && \defined (HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,10,0))#define simde_mm256_insert_epi16(a, i, index) _mm256_insert_epi16(a, i, index)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_insert_epi16#define _mm256_insert_epi16(a, i, imm8) simde_mm256_insert_epi16(a, i, imm8)#endif const int index)return simde__m256i_from_private(a_);#if defined (SIMDE_X86_AVX_NATIVE) && \defined (HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,10,0))#define simde_mm256_insert_epi32(a, i, index) _mm256_insert_epi32(a, i, index)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_insert_epi32#define _mm256_insert_epi32(a, i, index) simde_mm256_insert_epi32(a, i, index)#endif const int index)return simde__m256i_from_private(a_);#if defined (SIMDE_X86_AVX_NATIVE) && defined (SIMDE_ARCH_AMD64) && \defined (HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0)) && \#define simde_mm256_insert_epi64(a, i, index) _mm256_insert_epi64(a, i, index)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES) || (defined (SIMDE_ENABLE_NATIVE_ALIASES) && !defined (SIMDE_ARCH_AMD64))#undef _mm256_insert_epi64#define _mm256_insert_epi64(a, i, index) simde_mm256_insert_epi64(a, i, index)#endif int imm8)return simde__m256d_from_private(a_);#if defined (SIMDE_X86_AVX_NATIVE)#define simde_mm256_insertf128_pd(a, b, imm8) _mm256_insertf128_pd(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_insertf128_pd#define _mm256_insertf128_pd(a, b, imm8) simde_mm256_insertf128_pd(a, b, imm8)#endif int imm8)return simde__m256_from_private(a_);#if defined (SIMDE_X86_AVX_NATIVE)#define simde_mm256_insertf128_ps(a, b, imm8) _mm256_insertf128_ps(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_insertf128_ps#define _mm256_insertf128_ps(a, b, imm8) simde_mm256_insertf128_ps(a, b, imm8)#endif int imm8)return simde__m256i_from_private(a_);#if defined (SIMDE_X86_AVX_NATIVE)#define simde_mm256_insertf128_si256(a, b, imm8) _mm256_insertf128_si256(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_insertf128_si256#define _mm256_insertf128_si256(a, b, imm8) simde_mm256_insertf128_si256(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm256_dp_ps(a, b, imm8) _mm256_dp_ps(a, b, imm8)#else # define simde_mm256_dp_ps(a, b, imm8) \mm8), \mm8))#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_dp_ps#define _mm256_dp_ps(a, b, imm8) simde_mm256_dp_ps(a, b, imm8)#endif const int index)return a_.i32[index];#if defined (SIMDE_X86_AVX_NATIVE) && \defined (HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,10,0))#define simde_mm256_extract_epi32(a, index) _mm256_extract_epi32(a, index)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_extract_epi32#define _mm256_extract_epi32(a, index) simde_mm256_extract_epi32(a, index)#endif const int index)return a_.i64[index];#if defined (SIMDE_X86_AVX_NATIVE) && defined (SIMDE_ARCH_AMD64)#if !defined (HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0)#define simde_mm256_extract_epi64(a, index) _mm256_extract_epi64(a, index)#endif #endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES) || (defined (SIMDE_ENABLE_NATIVE_ALIASES) && !defined (SIMDE_ARCH_AMD64))#undef _mm256_extract_epi64#define _mm256_extract_epi64(a, index) simde_mm256_extract_epi64(a, index)#endif const * mem_addr) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_loadu_si256(mem_addr);#else sizeof (r));return r;#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_lddqu_si256#define _mm256_lddqu_si256(a) simde_mm256_lddqu_si256(a)#endif const double mem_addr[HEDLEY_ARRAY_PARAM(4)]) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_load_pd(mem_addr);#else sizeof (r));return r;#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_load_pd#define _mm256_load_pd(a) simde_mm256_load_pd(a)#endif const float mem_addr[HEDLEY_ARRAY_PARAM(8)]) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_load_ps(mem_addr);#else sizeof (r));return r;#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_load_ps#define _mm256_load_ps(a) simde_mm256_load_ps(a)#endif const * mem_addr) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_load_si256(mem_addr);#else sizeof (r));return r;#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_load_si256#define _mm256_load_si256(a) simde_mm256_load_si256(a)#endif const double a[HEDLEY_ARRAY_PARAM(4)]) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_loadu_pd(a);#else sizeof (r));return r;#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_loadu_pd#define _mm256_loadu_pd(a) simde_mm256_loadu_pd(a)#endif const float a[HEDLEY_ARRAY_PARAM(8)]) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_loadu_ps(a);#else sizeof (r));return r;#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_loadu_ps#define _mm256_loadu_ps(a) simde_mm256_loadu_ps(a)#endif #if defined (SIMDE_X86_AVX512VL_NATIVE) && defined (SIMDE_X86_AVX512BW_NATIVE) \defined (SIMDE_BUG_GCC_95483) && !defined (SIMDE_BUG_CLANG_REV_344862) \defined (HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))#define simde_mm256_loadu_epi8(mem_addr) _mm256_loadu_epi8(mem_addr)#else void const * mem_addr) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_loadu_si256(SIMDE_ALIGN_CAST(__m256i const *, mem_addr));#else sizeof (r));return r;#endif #endif #define simde_x_mm256_loadu_epi8(mem_addr) simde_mm256_loadu_epi8(mem_addr)#if defined (SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined (SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES) || (defined (SIMDE_ENABLE_NATIVE_ALIASES) && (defined (SIMDE_BUG_GCC_95483) || defined (SIMDE_BUG_CLANG_REV_344862)))#undef _mm256_loadu_epi8#define _mm256_loadu_epi8(a) simde_mm256_loadu_epi8(a)#endif #if defined (SIMDE_X86_AVX512VL_NATIVE) && defined (SIMDE_X86_AVX512BW_NATIVE) \defined (SIMDE_BUG_GCC_95483) && !defined (SIMDE_BUG_CLANG_REV_344862) \defined (HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))#define simde_mm256_loadu_epi16(mem_addr) _mm256_loadu_epi16(mem_addr)#else void const * mem_addr) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_loadu_si256(SIMDE_ALIGN_CAST(__m256i const *, mem_addr));#else sizeof (r));return r;#endif #endif #define simde_x_mm256_loadu_epi16(mem_addr) simde_mm256_loadu_epi16(mem_addr)#if defined (SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || defined (SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES) || (defined (SIMDE_ENABLE_NATIVE_ALIASES) && (defined (SIMDE_BUG_GCC_95483) || defined (SIMDE_BUG_CLANG_REV_344862)))#undef _mm256_loadu_epi16#define _mm256_loadu_epi16(a) simde_mm256_loadu_epi16(a)#endif #if defined (SIMDE_X86_AVX512VL_NATIVE) && !defined (SIMDE_BUG_GCC_95483) \defined (SIMDE_BUG_CLANG_REV_344862) \defined (HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))#define simde_mm256_loadu_epi32(mem_addr) _mm256_loadu_epi32(mem_addr)#else void const * mem_addr) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_loadu_si256(SIMDE_ALIGN_CAST(__m256i const *, mem_addr));#else sizeof (r));return r;#endif #endif #define simde_x_mm256_loadu_epi32(mem_addr) simde_mm256_loadu_epi32(mem_addr)#if defined (SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || (defined (SIMDE_ENABLE_NATIVE_ALIASES) && (defined (SIMDE_BUG_GCC_95483) || defined (SIMDE_BUG_CLANG_REV_344862)))#undef _mm256_loadu_epi32#define _mm256_loadu_epi32(a) simde_mm256_loadu_epi32(a)#endif #if defined (SIMDE_X86_AVX512VL_NATIVE) && !defined (SIMDE_BUG_GCC_95483) \defined (SIMDE_BUG_CLANG_REV_344862) \defined (HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))#define simde_mm256_loadu_epi64(mem_addr) _mm256_loadu_epi64(mem_addr)#else void const * mem_addr) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_loadu_si256(SIMDE_ALIGN_CAST(__m256i const *, mem_addr));#else sizeof (r));return r;#endif #endif #define simde_x_mm256_loadu_epi64(mem_addr) simde_mm256_loadu_epi64(mem_addr)#if defined (SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES) || (defined (SIMDE_ENABLE_NATIVE_ALIASES) && (defined (SIMDE_BUG_GCC_95483) || defined (SIMDE_BUG_CLANG_REV_344862)))#undef _mm256_loadu_epi64#define _mm256_loadu_epi64(a) simde_mm256_loadu_epi64(a)#endif void const * mem_addr) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_loadu_si256(SIMDE_ALIGN_CAST(const __m256i*, mem_addr));#else sizeof (r));return r;#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_loadu_si256#define _mm256_loadu_si256(mem_addr) simde_mm256_loadu_si256(mem_addr)#endif const float hiaddr[HEDLEY_ARRAY_PARAM(4)], const float loaddr[HEDLEY_ARRAY_PARAM(4)]) {#if defined (SIMDE_X86_AVX_NATIVE) && !defined (SIMDE_BUG_GCC_91341) && !defined (SIMDE_BUG_MCST_LCC_MISSING_AVX_LOAD_STORE_M128_FUNCS)return _mm256_loadu2_m128(hiaddr, loaddr);#else return ,#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_loadu2_m128#define _mm256_loadu2_m128(hiaddr, loaddr) simde_mm256_loadu2_m128(hiaddr, loaddr)#endif const double hiaddr[HEDLEY_ARRAY_PARAM(2)], const double loaddr[HEDLEY_ARRAY_PARAM(2)]) {#if defined (SIMDE_X86_AVX_NATIVE) && !defined (SIMDE_BUG_GCC_91341) && !defined (SIMDE_BUG_MCST_LCC_MISSING_AVX_LOAD_STORE_M128_FUNCS)return _mm256_loadu2_m128d(hiaddr, loaddr);#else return ,#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_loadu2_m128d#define _mm256_loadu2_m128d(hiaddr, loaddr) simde_mm256_loadu2_m128d(hiaddr, loaddr)#endif const simde__m128i* hiaddr, const simde__m128i* loaddr) {#if defined (SIMDE_X86_AVX_NATIVE) && !defined (SIMDE_BUG_GCC_91341) && !defined (SIMDE_BUG_MCST_LCC_MISSING_AVX_LOAD_STORE_M128_FUNCS)return _mm256_loadu2_m128i(hiaddr, loaddr);#else return addr)),#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_loadu2_m128i#define _mm256_loadu2_m128i(hiaddr, loaddr) simde_mm256_loadu2_m128i(hiaddr, loaddr)#endif const simde_float64 mem_addr[HEDLEY_ARRAY_PARAM(2)], simde__m128i mask) {#if defined (SIMDE_X86_AVX_NATIVE)#if defined (__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(3,8,0)return _mm_maskload_pd(mem_addr, HEDLEY_REINTERPRET_CAST(simde__m128d, mask));#else return _mm_maskload_pd(mem_addr, mask);#endif #else #if defined (SIMDE_ARM_NEON_A32V7_NATIVE)#elif defined (SIMDE_WASM_SIMD128_NATIVE)return simde_mm_and_pd(simde_mm_load_pd(mem_addr),#else for (size_t i = 0 ; i < (sizeof (mask_.i64) / sizeof (mask_.i64[0])) ; i++) {#endif for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {return simde__m128d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_maskload_pd#define _mm_maskload_pd(mem_addr, mask) simde_mm_maskload_pd(HEDLEY_REINTERPRET_CAST(double const *, mem_addr), mask)#endif const simde_float64 mem_addr[HEDLEY_ARRAY_PARAM(4)], simde__m256i mask) {#if defined (SIMDE_X86_AVX_NATIVE)#if defined (__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(3,8,0)return _mm256_maskload_pd(mem_addr, HEDLEY_REINTERPRET_CAST(simde__m256d, mask));#else return _mm256_maskload_pd(mem_addr, mask);#endif #else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_maskload_pd#define _mm256_maskload_pd(mem_addr, mask) simde_mm256_maskload_pd(HEDLEY_REINTERPRET_CAST(double const *, mem_addr), mask)#endif const simde_float32 mem_addr[HEDLEY_ARRAY_PARAM(4)], simde__m128i mask) {#if defined (SIMDE_X86_AVX_NATIVE)#if defined (__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(3,8,0)return _mm_maskload_ps(mem_addr, HEDLEY_REINTERPRET_CAST(simde__m128, mask));#else return _mm_maskload_ps(mem_addr, mask);#endif #else #if defined (SIMDE_ARM_NEON_A32V7_NATIVE)#elif defined (SIMDE_WASM_SIMD128_NATIVE)return simde_mm_and_ps(simde_mm_load_ps(mem_addr),#else for (size_t i = 0 ; i < (sizeof (mask_.i32) / sizeof (mask_.i32[0])) ; i++) {#endif for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {return simde__m128_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_maskload_ps#define _mm_maskload_ps(mem_addr, mask) simde_mm_maskload_ps(HEDLEY_REINTERPRET_CAST(float const *, mem_addr), mask)#endif const simde_float32 mem_addr[HEDLEY_ARRAY_PARAM(8)], simde__m256i mask) {#if defined (SIMDE_X86_AVX_NATIVE)#if defined (__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(3,8,0)return _mm256_maskload_ps(mem_addr, HEDLEY_REINTERPRET_CAST(simde__m256, mask));#else return _mm256_maskload_ps(mem_addr, mask);#endif #else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_maskload_ps#define _mm256_maskload_ps(mem_addr, mask) simde_mm256_maskload_ps(HEDLEY_REINTERPRET_CAST(float const *, mem_addr), mask)#endif void ask, simde__m128d a) {#if defined (SIMDE_X86_AVX_NATIVE)#if defined (__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(3,8,0)#else #endif #else #if defined (SIMDE_WASM_SIMD128_NATIVE)if ((HEDLEY_STATIC_CAST(unsigned long long , wasm_i64x2_extract_lane(mask_.wasm_v128, 0)) & 0x8000000000000000ull) != 0)if ((HEDLEY_STATIC_CAST(unsigned long long , wasm_i64x2_extract_lane(mask_.wasm_v128, 1)) & 0x8000000000000000ull) != 0)#else for (size_t i = 0 ; i < (sizeof (a_.f64) / sizeof (a_.f64[0])) ; i++) {if (mask_.u64[i] >> 63)#endif #endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_maskstore_pd#define _mm_maskstore_pd(mem_addr, mask, a) simde_mm_maskstore_pd(HEDLEY_REINTERPRET_CAST(double *, mem_addr), mask, a)#endif void 6i mask, simde__m256d a) {#if defined (SIMDE_X86_AVX_NATIVE)#if defined (__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(3,8,0)#else #endif #else for (size_t i = 0 ; i < (sizeof (a_.f64) / sizeof (a_.f64[0])) ; i++) {if (mask_.u64[i] & (UINT64_C(1) << 63))#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_maskstore_pd#define _mm256_maskstore_pd(mem_addr, mask, a) simde_mm256_maskstore_pd(HEDLEY_REINTERPRET_CAST(double *, mem_addr), mask, a)#endif void ask, simde__m128 a) {#if defined (SIMDE_X86_AVX_NATIVE)#if defined (__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(3,8,0)#else #endif #else #if defined (SIMDE_WASM_SIMD128_NATIVE)if ((HEDLEY_STATIC_CAST(unsigned long long , wasm_i32x4_extract_lane(mask_.wasm_v128, 0)) & 0x80000000ull) != 0)if ((HEDLEY_STATIC_CAST(unsigned long long , wasm_i32x4_extract_lane(mask_.wasm_v128, 1)) & 0x80000000ull) != 0)if ((HEDLEY_STATIC_CAST(unsigned long long , wasm_i32x4_extract_lane(mask_.wasm_v128, 2)) & 0x80000000ull) != 0)if ((HEDLEY_STATIC_CAST(unsigned long long , wasm_i32x4_extract_lane(mask_.wasm_v128, 3)) & 0x80000000ull) != 0)#else for (size_t i = 0 ; i < (sizeof (a_.f32) / sizeof (a_.f32[0])) ; i++) {if (mask_.u32[i] & (UINT32_C(1) << 31))#endif #endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_maskstore_ps#define _mm_maskstore_ps(mem_addr, mask, a) simde_mm_maskstore_ps(HEDLEY_REINTERPRET_CAST(float *, mem_addr), mask, a)#endif void 6i mask, simde__m256 a) {#if defined (SIMDE_X86_AVX_NATIVE)#if defined (__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(3,8,0)#else #endif #else for (size_t i = 0 ; i < (sizeof (a_.f32) / sizeof (a_.f32[0])) ; i++) {if (mask_.u32[i] & (UINT32_C(1) << 31))#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_maskstore_ps#define _mm256_maskstore_ps(mem_addr, mask, a) simde_mm256_maskstore_ps(HEDLEY_REINTERPRET_CAST(float *, mem_addr), mask, a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_min_ps(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_min_ps#define _mm256_min_ps(a, b) simde_mm256_min_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_min_pd(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_min_pd#define _mm256_min_pd(a, b) simde_mm256_min_pd(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_max_ps(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_max_ps#define _mm256_max_ps(a, b) simde_mm256_max_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_max_pd(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_max_pd#define _mm256_max_pd(a, b) simde_mm256_max_pd(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_movedup_pd(a);#else #if defined (SIMDE_SHUFFLE_VECTOR_)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i += 2) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_movedup_pd#define _mm256_movedup_pd(a) simde_mm256_movedup_pd(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_movehdup_ps(a);#else #if defined (SIMDE_SHUFFLE_VECTOR_)#else for (size_t i = 1 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i += 2) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_movehdup_ps#define _mm256_movehdup_ps(a) simde_mm256_movehdup_ps(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_moveldup_ps(a);#else #if defined (SIMDE_SHUFFLE_VECTOR_)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i += 2) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_moveldup_ps#define _mm256_moveldup_ps(a) simde_mm256_moveldup_ps(a)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_movemask_ps(a);#else int r = 0;for (size_t i = 0 ; i < (sizeof (a_.f32) / sizeof (a_.f32[0])) ; i++) {return r;#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_movemask_ps#define _mm256_movemask_ps(a) simde_mm256_movemask_ps(a)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_movemask_pd(a);#else int r = 0;for (size_t i = 0 ; i < (sizeof (a_.f64) / sizeof (a_.f64[0])) ; i++) {return r;#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_movemask_pd#define _mm256_movemask_pd(a) simde_mm256_movemask_pd(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_mul_ps(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_mul_ps#define _mm256_mul_ps(a, b) simde_mm256_mul_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_mul_pd(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_mul_pd#define _mm256_mul_pd(a, b) simde_mm256_mul_pd(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_or_ps(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.u32) / sizeof (r_.u32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_or_ps#define _mm256_or_ps(a, b) simde_mm256_or_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_or_pd(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.u64) / sizeof (r_.u64[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_or_pd#define _mm256_or_pd(a, b) simde_mm256_or_pd(a, b)#endif const int imm8)for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {return simde__m256_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm256_permute_ps(a, imm8) _mm256_permute_ps(a, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_permute_ps#define _mm256_permute_ps(a, imm8) simde_mm256_permute_ps(a, imm8)#endif const int imm8)for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {return simde__m256d_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm256_permute_pd(a, imm8) _mm256_permute_pd(a, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_permute_pd#define _mm256_permute_pd(a, imm8) simde_mm256_permute_pd(a, imm8)#endif const int imm8)for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {return simde__m128_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm_permute_ps(a, imm8) _mm_permute_ps(a, imm8)#elif defined (SIMDE_WASM_SIMD128_NATIVE)# define simde_mm_permute_ps(a, imm8) simde__m128_from_wasm_v128(wasm_i32x4_shuffle(simde__m128_to_wasm_v128(a), simde__m128_to_wasm_v128(a), ((imm8) & 3), (((imm8) >> 2) & 3 ), (((imm8) >> 4) & 3), (((imm8) >> 6) & 3)))#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_permute_ps#define _mm_permute_ps(a, imm8) simde_mm_permute_ps(a, imm8)#endif const int imm8)for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {return simde__m128d_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm_permute_pd(a, imm8) _mm_permute_pd(a, imm8)#elif defined (SIMDE_WASM_SIMD128_NATIVE)# define simde_mm_permute_pd(a, imm8) simde__m128d_from_wasm_v128(wasm_i64x2_shuffle(simde__m128d_to_wasm_v128(a), simde__m128d_to_wasm_v128(a), ((imm8) & 1), (((imm8) >> 1) & 1 )))#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_permute_pd#define _mm_permute_pd(a, imm8) simde_mm_permute_pd(a, imm8)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm_permutevar_ps(a, b);#else #if defined (SIMDE_WASM_SIMD128_NATIVE)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif return simde__m128_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_permutevar_ps#define _mm_permutevar_ps(a, b) simde_mm_permutevar_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm_permutevar_pd(a, b);#else #if defined (SIMDE_WASM_SIMD128_NATIVE)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif return simde__m128d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_permutevar_pd#define _mm_permutevar_pd(a, b) simde_mm_permutevar_pd(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_permutevar_ps(a, b);#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_permutevar_ps#define _mm256_permutevar_ps(a, b) simde_mm256_permutevar_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_permutevar_pd(a, b);#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_permutevar_pd#define _mm256_permutevar_pd(a, b) simde_mm256_permutevar_pd(a, b)#endif const int imm8): ((imm8 & 0x02) ? b_.m128_private[(imm8 ) & 1] : a_.m128_private[(imm8 ) & 1]);: ((imm8 & 0x20) ? b_.m128_private[(imm8 >> 4) & 1] : a_.m128_private[(imm8 >> 4) & 1]);return simde__m256_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm256_permute2f128_ps(a, b, imm8) _mm256_permute2f128_ps(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_permute2f128_ps#define _mm256_permute2f128_ps(a, b, imm8) simde_mm256_permute2f128_ps(a, b, imm8)#endif const int imm8))) : ((imm8 & 0x02) ? b_.m128d_private[(imm8 ) & 1] : a_.m128d_private[(imm8 ) & 1]);)) : ((imm8 & 0x20) ? b_.m128d_private[(imm8 >> 4) & 1] : a_.m128d_private[(imm8 >> 4) & 1]);return simde__m256d_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm256_permute2f128_pd(a, b, imm8) _mm256_permute2f128_pd(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_permute2f128_pd#define _mm256_permute2f128_pd(a, b, imm8) simde_mm256_permute2f128_pd(a, b, imm8)#endif const int imm8)28()) : ((imm8 & 0x02) ? b_.m128i_private[(imm8 ) & 1] : a_.m128i_private[(imm8 ) & ;1]);28()) : ((imm8 & 0x20) ? b_.m128i_private[(imm8 >> 4) & 1] : a_.m128i_private[(imm8 >> 4) & 1]);return simde__m256i_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)# define simde_mm256_permute2f128_si128(a, b, imm8) _mm256_permute2f128_si128(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_permute2f128_si256#define _mm256_permute2f128_si256(a, b, imm8) simde_mm256_permute2f128_si256(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_rcp_ps(a);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_rcp_ps#define _mm256_rcp_ps(a) simde_mm256_rcp_ps(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_rsqrt_ps(a);#else #if defined (simde_math_sqrtf)for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#else #endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_rsqrt_ps#define _mm256_rsqrt_ps(a) simde_mm256_rsqrt_ps(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_setr_epi8(#else return simde_mm256_set_epi8(#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_setr_epi8#define _mm256_setr_epi8(e31, e30, e29, e28, e27, e26, e25, e24, e23, e22, e21, e20, e19, e18, e17, e16, e15, e14, e13, e12, e11, e10, e9, e8, e7, e6, e5, e4, e3, e2, e1, e0) \7, e16, e15, e14, e13, e12, e11, e10, e9, e8, e7, e6, e5, e4, e3, e2, e1, e0)#endif 6_t e8,{#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_setr_epi16(#else return simde_mm256_set_epi16(#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_setr_epi16#define _mm256_setr_epi16(e15, e14, e13, e12, e11, e10, e9, e8, e7, e6, e5, e4, e3, e2, e1, e0) \#endif {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_setr_epi32(e7, e6, e5, e4, e3, e2, e1, e0);#else return simde_mm256_set_epi32(e0, e1, e2, e3, e4, e5, e6, e7);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_setr_epi32#define _mm256_setr_epi32(e7, e6, e5, e4, e3, e2, e1, e0) \#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_setr_epi64x(e3, e2, e1, e0);#else return simde_mm256_set_epi64x(e0, e1, e2, e3);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_setr_epi64x#define _mm256_setr_epi64x(e3, e2, e1, e0) \#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_setr_ps(e7, e6, e5, e4, e3, e2, e1, e0);#else return simde_mm256_set_ps(e0, e1, e2, e3, e4, e5, e6, e7);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_setr_ps#define _mm256_setr_ps(e7, e6, e5, e4, e3, e2, e1, e0) \#endif 4 e0) {#if defined (SIMDE_X86_AVX_NATIVE)return _mm256_setr_pd(e3, e2, e1, e0);#else return simde_mm256_set_pd(e0, e1, e2, e3);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_setr_pd#define _mm256_setr_pd(e3, e2, e1, e0) \#endif #if defined (SIMDE_X86_AVX_NATIVE) && \defined (SIMDE_BUG_GCC_REV_247851) && \return _mm256_setr_m128(lo, hi);#else return simde_mm256_set_m128(hi, lo);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_setr_m128#define _mm256_setr_m128(lo, hi) \#endif #if defined (SIMDE_X86_AVX_NATIVE) && \defined (SIMDE_BUG_GCC_REV_247851) && \return _mm256_setr_m128d(lo, hi);#else return simde_mm256_set_m128d(hi, lo);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_setr_m128d#define _mm256_setr_m128d(lo, hi) \#endif #if defined (SIMDE_X86_AVX_NATIVE) && \defined (SIMDE_BUG_GCC_REV_247851) && \return _mm256_setr_m128i(lo, hi);#else return simde_mm256_set_m128i(hi, lo);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_setr_m128i#define _mm256_setr_m128i(lo, hi) \#endif const int imm8)return simde__m256_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)#define simde_mm256_shuffle_ps(a, b, imm8) _mm256_shuffle_ps(a, b, imm8)#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128)#define simde_mm256_shuffle_ps(a, b, imm8) \, 1), (imm8)), \, 0), (imm8)))#elif defined (SIMDE_SHUFFLE_VECTOR_)#define simde_mm256_shuffle_ps(a, b, imm8) \#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_shuffle_ps#define _mm256_shuffle_ps(a, b, imm8) simde_mm256_shuffle_ps(a, b, imm8)#endif const int imm8)return simde__m256d_from_private(r_);#if defined (SIMDE_X86_AVX_NATIVE)#define simde_mm256_shuffle_pd(a, b, imm8) _mm256_shuffle_pd(a, b, imm8)#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128)#define simde_mm256_shuffle_pd(a, b, imm8) \, 1), (imm8 >> 0) & 3), \, 0), (imm8 >> 2) & 3))#elif defined (SIMDE_SHUFFLE_VECTOR_)#define simde_mm256_shuffle_pd(a, b, imm8) \#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_shuffle_pd#define _mm256_shuffle_pd(a, b, imm8) simde_mm256_shuffle_pd(a, b, imm8)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_sqrt_ps(a);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (simde_math_sqrtf)for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#else #endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_sqrt_ps#define _mm256_sqrt_ps(a) simde_mm256_sqrt_ps(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_sqrt_pd(a);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (simde_math_sqrt)for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#else #endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_sqrt_pd#define _mm256_sqrt_pd(a) simde_mm256_sqrt_pd(a)#endif void #if defined (SIMDE_X86_AVX_NATIVE)#else sizeof (a));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_store_ps#define _mm256_store_ps(mem_addr, a) simde_mm256_store_ps(HEDLEY_REINTERPRET_CAST(float *, mem_addr), a)#endif void #if defined (SIMDE_X86_AVX_NATIVE)#else sizeof (a));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_store_pd#define _mm256_store_pd(mem_addr, a) simde_mm256_store_pd(HEDLEY_REINTERPRET_CAST(double *, mem_addr), a)#endif void #if defined (SIMDE_X86_AVX_NATIVE)#else sizeof (a));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_store_si256#define _mm256_store_si256(mem_addr, a) simde_mm256_store_si256(mem_addr, a)#endif void #if defined (SIMDE_X86_AVX_NATIVE)#else sizeof (a));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_storeu_ps#define _mm256_storeu_ps(mem_addr, a) simde_mm256_storeu_ps(HEDLEY_REINTERPRET_CAST(float *, mem_addr), a)#endif void #if defined (SIMDE_X86_AVX_NATIVE)#else sizeof (a));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_storeu_pd#define _mm256_storeu_pd(mem_addr, a) simde_mm256_storeu_pd(HEDLEY_REINTERPRET_CAST(double *, mem_addr), a)#endif void void * mem_addr, simde__m256i a) {#if defined (SIMDE_X86_AVX_NATIVE)#else sizeof (a));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_storeu_si256#define _mm256_storeu_si256(mem_addr, a) simde_mm256_storeu_si256(mem_addr, a)#endif void m256 a) {#if defined (SIMDE_X86_AVX_NATIVE) && !defined (SIMDE_BUG_GCC_91341) && !defined (SIMDE_BUG_MCST_LCC_MISSING_AVX_LOAD_STORE_M128_FUNCS)#else #endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_storeu2_m128#define _mm256_storeu2_m128(hi_addr, lo_addr, a) simde_mm256_storeu2_m128(hi_addr, lo_addr, a)#endif void _m256d a) {#if defined (SIMDE_X86_AVX_NATIVE) && !defined (SIMDE_BUG_GCC_91341) && !defined (SIMDE_BUG_MCST_LCC_MISSING_AVX_LOAD_STORE_M128_FUNCS)#else #endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_storeu2_m128d#define _mm256_storeu2_m128d(hi_addr, lo_addr, a) simde_mm256_storeu2_m128d(hi_addr, lo_addr, a)#endif void a) {#if defined (SIMDE_X86_AVX_NATIVE) && !defined (SIMDE_BUG_GCC_91341) && !defined (SIMDE_BUG_MCST_LCC_MISSING_AVX_LOAD_STORE_M128_FUNCS)#else #endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_storeu2_m128i#define _mm256_storeu2_m128i(hi_addr, lo_addr, a) simde_mm256_storeu2_m128i(hi_addr, lo_addr, a)#endif void #if defined (SIMDE_X86_AVX_NATIVE)#else sizeof (a));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_stream_ps#define _mm256_stream_ps(mem_addr, a) simde_mm256_stream_ps(HEDLEY_REINTERPRET_CAST(float *, mem_addr), a)#endif void #if defined (SIMDE_X86_AVX_NATIVE)#else sizeof (a));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_stream_pd#define _mm256_stream_pd(mem_addr, a) simde_mm256_stream_pd(HEDLEY_REINTERPRET_CAST(double *, mem_addr), a)#endif void #if defined (SIMDE_X86_AVX_NATIVE)#else sizeof (a));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_stream_si256#define _mm256_stream_si256(mem_addr, a) simde_mm256_stream_si256(mem_addr, a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_sub_ps(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_sub_ps#define _mm256_sub_ps(a, b) simde_mm256_sub_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_hsub_ps(a, b);#else return simde_mm256_sub_ps(simde_x_mm256_deinterleaveeven_ps(a, b), simde_x_mm256_deinterleaveodd_ps(a, b));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_hsub_ps#define _mm256_hsub_ps(a, b) simde_mm256_hsub_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_sub_pd(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_sub_pd#define _mm256_sub_pd(a, b) simde_mm256_sub_pd(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_hsub_pd(a, b);#else return simde_mm256_sub_pd(simde_x_mm256_deinterleaveeven_pd(a, b), simde_x_mm256_deinterleaveodd_pd(a, b));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_hsub_pd#define _mm256_hsub_pd(a, b) simde_mm256_hsub_pd(a, b)#endif #if defined (SIMDE_DIAGNOSTIC_DISABLE_UNINITIALIZED_)#endif void ) {#if \defined (SIMDE_X86_AVX_NATIVE) && \defined (HEDLEY_GCC_VERSION) || HEDLEY_GCC_VERSION_CHECK(5,0,0)) && \defined (__has_builtin) || HEDLEY_HAS_BUILTIN(__builtin_ia32_undef256))#elif !defined (SIMDE_DIAGNOSTIC_DISABLE_UNINITIALIZED_)#endif return simde__m256_from_private(r_);#if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_undefined_ps#define _mm256_undefined_ps() simde_mm256_undefined_ps()#endif void ) {#if \defined (SIMDE_X86_AVX_NATIVE) && \defined (HEDLEY_GCC_VERSION) || HEDLEY_GCC_VERSION_CHECK(5,0,0)) && \defined (__has_builtin) || HEDLEY_HAS_BUILTIN(__builtin_ia32_undef256))#elif !defined (SIMDE_DIAGNOSTIC_DISABLE_UNINITIALIZED_)#endif return simde__m256d_from_private(r_);#if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_undefined_pd#define _mm256_undefined_pd() simde_mm256_undefined_pd()#endif void ) {#if \defined (SIMDE_X86_AVX_NATIVE) && \defined (HEDLEY_GCC_VERSION) || HEDLEY_GCC_VERSION_CHECK(5,0,0)) && \defined (__has_builtin) || HEDLEY_HAS_BUILTIN(__builtin_ia32_undef256))#elif !defined (SIMDE_DIAGNOSTIC_DISABLE_UNINITIALIZED_)#endif return simde__m256i_from_private(r_);#if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_undefined_si256#define _mm256_undefined_si256() simde_mm256_undefined_si256()#endif #if defined (SIMDE_DIAGNOSTIC_DISABLE_UNINITIALIZED_)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_xor_ps(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.u32) / sizeof (r_.u32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_xor_ps#define _mm256_xor_ps(a, b) simde_mm256_xor_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_xor_pd(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)#elif defined (SIMDE_VECTOR_SUBSCRIPT_OPS)#else for (size_t i = 0 ; i < (sizeof (r_.u64) / sizeof (r_.u64[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_xor_pd#define _mm256_xor_pd(a, b) simde_mm256_xor_pd(a, b)#endif return simde_mm256_xor_ps(simde_mm256_and_ps(simde_mm256_set1_ps(-0.0f), src), dest);return simde_mm256_xor_pd(simde_mm256_and_pd(simde_mm256_set1_pd(-0.0), src), dest);#if defined (SIMDE_X86_AVX_NATIVE)return simde_mm256_xor_ps(a,_mm256_set1_ps(SIMDE_FLOAT32_C(-0.0)));#else #if defined (SIMDE_VECTOR_NEGATE)#else for (size_t i = 0 ; i < (sizeof (r_.f32) / sizeof (r_.f32[0])) ; i++) {#endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX2_NATIVE)return simde_mm256_xor_pd(a, _mm256_set1_pd(SIMDE_FLOAT64_C(-0.0)));#else #if defined (SIMDE_VECTOR_NEGATE)#else for (size_t i = 0 ; i < (sizeof (r_.f64) / sizeof (r_.f64[0])) ; i++) {#endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_unpackhi_ps(a, b);#else #if defined (SIMDE_SHUFFLE_VECTOR_)#else #endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_unpackhi_ps#define _mm256_unpackhi_ps(a, b) simde_mm256_unpackhi_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_unpackhi_pd(a, b);#else #if defined (SIMDE_SHUFFLE_VECTOR_)#else #endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_unpackhi_pd#define _mm256_unpackhi_pd(a, b) simde_mm256_unpackhi_pd(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_unpacklo_ps(a, b);#else #if defined (SIMDE_SHUFFLE_VECTOR_)#else #endif return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_unpacklo_ps#define _mm256_unpacklo_ps(a, b) simde_mm256_unpacklo_ps(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_unpacklo_pd(a, b);#else #if defined (SIMDE_SHUFFLE_VECTOR_)#else #endif return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_unpacklo_pd#define _mm256_unpacklo_pd(a, b) simde_mm256_unpacklo_pd(a, b)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_insertf128_ps(_mm256_setzero_ps(), a, 0);#else return simde__m256_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_zextps128_ps256#define _mm256_zextps128_ps256(a) simde_mm256_zextps128_ps256(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_insertf128_pd(_mm256_setzero_pd(), a, 0);#else return simde__m256d_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_zextpd128_pd256#define _mm256_zextpd128_pd256(a) simde_mm256_zextpd128_pd256(a)#endif #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_insertf128_si256(_mm256_setzero_si256(), a, 0);#else return simde__m256i_from_private(r_);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_zextsi128_si256#define _mm256_zextsi128_si256(a) simde_mm256_zextsi128_si256(a)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm_testc_ps(a, b);#else #if defined (SIMDE_WASM_SIMD128_NATIVE));return wasm_i32x4_extract_lane(m, 0);#else for (size_t i = 0 ; i < (sizeof (a_.u32) / sizeof (a_.u32[0])) ; i++) {return HEDLEY_STATIC_CAST(int , ((~r >> 31) & 1));#endif #endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_testc_ps#define _mm_testc_ps(a, b) simde_mm_testc_ps(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm_testc_pd(a, b);#else #if defined (SIMDE_WASM_SIMD128_NATIVE));return HEDLEY_STATIC_CAST(int , wasm_i64x2_extract_lane(m, 0) & wasm_i64x2_extract_lane(m, 1));#else for (size_t i = 0 ; i < (sizeof (a_.u64) / sizeof (a_.u64[0])) ; i++) {return HEDLEY_STATIC_CAST(int , ((~r >> 63) & 1));#endif #endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_testc_pd#define _mm_testc_pd(a, b) simde_mm_testc_pd(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_testc_ps(a, b);#else for (size_t i = 0 ; i < (sizeof (a_.u32) / sizeof (a_.u32[0])) ; i++) {return HEDLEY_STATIC_CAST(int , ((~r >> 31) & 1));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_testc_ps#define _mm256_testc_ps(a, b) simde_mm256_testc_ps(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_testc_pd(a, b);#else for (size_t i = 0 ; i < (sizeof (a_.u64) / sizeof (a_.u64[0])) ; i++) {return HEDLEY_STATIC_CAST(int , ((~r >> 63) & 1));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_testc_pd#define _mm256_testc_pd(a, b) simde_mm256_testc_pd(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_testc_si256(a, b);#else for (size_t i = 0 ; i < (sizeof (a_.i32f) / sizeof (a_.i32f[0])) ; i++) {return HEDLEY_STATIC_CAST(int , !r);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_testc_si256#define _mm256_testc_si256(a, b) simde_mm256_testc_si256(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm_testz_ps(a, b);#else #if defined (SIMDE_WASM_SIMD128_NATIVE)1);return wasm_i32x4_extract_lane(m, 0);#else for (size_t i = 0 ; i < (sizeof (a_.u32) / sizeof (a_.u32[0])) ; i++) {return HEDLEY_STATIC_CAST(int , ((~r >> 31) & 1));#endif #endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_testz_ps#define _mm_testz_ps(a, b) simde_mm_testz_ps(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm_testz_pd(a, b);#else #if defined (SIMDE_WASM_SIMD128_NATIVE)3);return HEDLEY_STATIC_CAST(int , wasm_i64x2_extract_lane(m, 0) & wasm_i64x2_extract_lane(m, 1));#else for (size_t i = 0 ; i < (sizeof (a_.u64) / sizeof (a_.u64[0])) ; i++) {return HEDLEY_STATIC_CAST(int , ((~r >> 63) & 1));#endif #endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_testz_pd#define _mm_testz_pd(a, b) simde_mm_testz_pd(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_testz_ps(a, b);#else for (size_t i = 0 ; i < (sizeof (a_.u32) / sizeof (a_.u32[0])) ; i++) {return HEDLEY_STATIC_CAST(int , ((~r >> 31) & 1));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_testz_ps#define _mm256_testz_ps(a, b) simde_mm256_testz_ps(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_testz_pd(a, b);#else for (size_t i = 0 ; i < (sizeof (a_.u64) / sizeof (a_.u64[0])) ; i++) {return HEDLEY_STATIC_CAST(int , ((~r >> 63) & 1));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_testz_pd#define _mm256_testz_pd(a, b) simde_mm256_testz_pd(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_testz_si256(a, b);#else #if SIMDE_NATURAL_VECTOR_SIZE_LE(128)b_.m128i[1]);#else for (size_t i = 0 ; i < (sizeof (a_.i32f) / sizeof (a_.i32f[0])) ; i++) {#endif return HEDLEY_STATIC_CAST(int , r);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_testz_si256#define _mm256_testz_si256(a, b) simde_mm256_testz_si256(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm_testnzc_ps(a, b);#else #if defined (SIMDE_WASM_SIMD128_NATIVE)return wasm_i32x4_extract_lane(m, 0) & wasm_i32x4_extract_lane(m2, 0);#else for (size_t i = 0 ; i < (sizeof (a_.u32) / sizeof (a_.u32[0])) ; i++) {return sizeof (rc) * CHAR_BIT) - 1)) &sizeof (rz) * CHAR_BIT) - 1));#endif #endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_testnzc_ps#define _mm_testnzc_ps(a, b) simde_mm_testnzc_ps(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm_testnzc_pd(a, b);#else #if defined (SIMDE_WASM_SIMD128_NATIVE)return HEDLEY_STATIC_CAST(int , (wasm_i64x2_extract_lane(m, 0) | wasm_i64x2_extract_lane(m, 1))#else for (size_t i = 0 ; i < (sizeof (a_.u64) / sizeof (a_.u64[0])) ; i++) {return sizeof (rc) * CHAR_BIT) - 1)) &sizeof (rz) * CHAR_BIT) - 1));#endif #endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm_testnzc_pd#define _mm_testnzc_pd(a, b) simde_mm_testnzc_pd(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_testnzc_ps(a, b);#else for (size_t i = 0 ; i < (sizeof (a_.u32) / sizeof (a_.u32[0])) ; i++) {return sizeof (rc) * CHAR_BIT) - 1)) &sizeof (rz) * CHAR_BIT) - 1));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_testnzc_ps#define _mm256_testnzc_ps(a, b) simde_mm256_testnzc_ps(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_testnzc_pd(a, b);#else for (size_t i = 0 ; i < (sizeof (a_.u64) / sizeof (a_.u64[0])) ; i++) {return sizeof (rc) * CHAR_BIT) - 1)) &sizeof (rz) * CHAR_BIT) - 1));#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_testnzc_pd#define _mm256_testnzc_pd(a, b) simde_mm256_testnzc_pd(a, b)#endif int #if defined (SIMDE_X86_AVX_NATIVE)return _mm256_testnzc_si256(a, b);#else for (size_t i = 0 ; i < (sizeof (a_.i32f) / sizeof (a_.i32f[0])) ; i++) {return !!(rc & rz);#endif #if defined (SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)#undef _mm256_testnzc_si256#define _mm256_testnzc_si256(a, b) simde_mm256_testnzc_si256(a, b)#endif #endif /* !defined(SIMDE_X86_AVX_H) */
Messung V0.5 in Prozent C=95 H=93 G=93
¤ Dauer der Verarbeitung: 0.129 Sekunden
(vorverarbeitet am 2026-04-25)
¤ *© Formatika GbR, Deutschland
