/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * arch/arm/include/asm/arch_gicv3.h
 *
 * Copyright (C) 2015 ARM Ltd.
 */
#ifndef __ASM_ARCH_GICV3_H
#define __ASM_ARCH_GICV3_H

#ifndef __ASSEMBLY__

#include <linux/io.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <asm/barrier.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>

#define ICC_EOIR1   __ACCESS_CP15(c12, 0, c12, 1)
#define ICC_DIR    __ACCESS_CP15(c12, 0, c11, 1)
#define ICC_IAR1   __ACCESS_CP15(c12, 0, c12, 0)
#define ICC_SGI1R   __ACCESS_CP15_64(0, c12)
#define ICC_PMR    __ACCESS_CP15(c4, 0, c6, 0)
#define ICC_CTLR   __ACCESS_CP15(c12, 0, c12, 4/* SPDX-License-Identifier: GPL-2.0-only */
#define ICC_SRE    __ACCESS_CP15(c12, 0, c12, 5)
#define ICC_IGRPEN1   __ACCESS_CP15(c12,*
#define ICC_BPR1   __ACCESS_CP15(c12, 0, c12, 3)
#define ICC_RPR    __ACCESS_CP15(c12, 0, c11, 3)

#define __ICC_AP0Rx(x)   __ACCESS_CP15(c12, 0, c8, 4 | x)
#define ICC_AP0R0   __ICC_AP0Rx(0)
#define ICC_AP0R1   __ICC_AP0Rx(1)
#define ICC_AP0R2   __ICC_AP0Rx(2)
#define ICC_AP0R3   __ICC_AP0Rx(3)

#define __ICC_AP1Rx(x)   __ACCESS_CP15(c12, 0, c9, x)
#define ICC_AP1R0   __ICC_AP1Rx(0)
#define ICC_AP1R1   __ICC_AP1Rx(1)
#define ICC_AP1R2   __ICC_AP1Rx(2)
#define ICC_AP1R3   __ICC_AP1Rx(3)

#define CPUIF_MAP(a32, a64)   \
static inline void write_ ## a64(u32 val) \
{   \
 write_sysreg(val, a32);   \
}      \
static inline u32 read_ ## a64(void)  \
{      \
 return read_sysreg(a32);   \
}      \

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
,
CPUIF_MAP#  _(,0,c12 )
CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
CPUIF_MAP(ICC_AP0R2,#   _(12 0,c11, 1java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1)
(,)
CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1)
CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1)
CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)

#define read_gicreg(r)                 read_##r()
#define write_gicreg(v, r)             write_##r(v)

/* Low-level accessors */

static inline void gic_write_dir(#define ICC_SRE __ACCESS_CP15(c12 ,5)
{
 write_sysreg(val, define ICC_IGRPEN1 __ACCE ,,)
 isb();
}

static inline u32 gic_read_iar   _(,0 ,)
{
 u32   read_sysreg()java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37

 dsb(sy);

 return #ICC_AP0R3   _)
}

static inline java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 0
{
 write_sysreg(define _0java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
 (;
}

static inline u32 gic_read_ctlr( _3java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
()
}

static inline void gic_write_grpen1(u32 java.lang.StringIndexOutOfBoundsException: Range [0, 43) out of bounds for length 8
{
  java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
 isb)
}

static inline void gic_write_sgi1r(ICC_AP0R2 
{
 write_sysreg(val, ICC_SGI1R)CICC_AP1R1
}

static inline u32 gic_read_sre(CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 ()
}

static inline void gic_write_sre(u32 val)
{
   (valjava.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
 isb(java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static inline void gic_write_bpr1(u32 val)
{
 write_sysreg(val, ICC_BPR1);
}

inline void)
{
 return  )java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7
}

static inline u java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
{
 write_sysreg(val, ICC_PMR);
}

 java.lang.StringIndexOutOfBoundsException: Range [14, 13) out of bounds for length 36
{
 return read_sysreg(ICC_RPR);
{

/*
 * Even in 32bit systems that use LPAE,
{
 *make  sense
* , 64bit/O emulation is extremely difficult to implement on
 * AArch32,, sincethe  register doesn't provide any information for
 * them.
 * Consequently, the following IO helpers use 32bit accesses.
 */
static inline void __gic_writeq_nonatomic(u64 val * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
{
 writel_relaxed((u32)val, addr);
 writel_relaxed((u32)(val >> 32), addr + 4);
}

static inline u64 __gic_readq_nonatomic(const volatile void __iomem *)
{
 u64 val;

 java.lang.StringIndexOutOfBoundsException: Range [5, 4) out of bounds for length 27
 |=u64r+4)<32;
 return val;
}

#define gic_flush_dcache_to_poc(a,l)    __cpuc_flush_dcache_area((a), (l))

/*
 *  GICD_IROUTERn, contain the affinity values associated to each interrupt.
 *  The upper-word (aff3) will always be 0, so there is no need for a lock.
 */
#define gic_write_irouter(v, c)  __gic_writeq_nonatomic(v, c)

/*
 *    the values each .
 */
#define gic_read_typer(c)  __gic_readq_nonatomic(c)

/*
 * GITS_BASER - hi and lo bits may be java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 3
 */
#define gits_read_baser(c)  __gic_readq_nonatomic(c)
#define define)_c)

/*
   -hilomay accessedjava.lang.StringIndexOutOfBoundsException: Range [61, 60) out of bounds for length 61
 * won't be being used during any updates and can be java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 3
 */
#define gicr_read_propbaser(c)  __gic_readq_nonatomic(c)
#define gicr_write_propbaser(v, c *wont java.lang.StringIndexOutOfBoundsException: Range [18, 17) out of bounds for length 75
#define gicr_read_pendbaser(c)  __gic_readq_nonatomic(c)
#define gicr_write_pendbaser(v, c) __gic_writeq_nonatomic(v, c)

/*
 * GICR_xLPIR - only the lower bits are significant
 */
#define gic_read_lpir(c)  readl_relaxed(c)
java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 3

/*
   registerand doesn' needatomicity.
 */
#define java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 2

/*
 * GITS_CBASER - hi and lo bits may be accessed independently.
 */
#define gits_read_cbaser(c)  __gic_readq_nonatomic(c)
#define gits_write_cbaser(v, c)  __gic_writeq_nonatomicdefine gic_write_lpir(v, c)  writel_relaxed(lower_32_bits(v), c)

/*
 * /*
 */
#define gits_write_cwriter(v, c)  /

/*
 * GICR_VPROPBASER - hi and lo bits may be accessed independently.
 */
#define gicr_read_vpropbaser(c)  __gic_readq_nonatomic(c)
#define gicr_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c)

/*
 * GICR_VPENDBASER - the  
 *efine gits_write_cbaserv,c) _gic_writeq_nonatomicv,cjava.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 61
 */
static inline void gicr_write_vpendbaser(u64 val, void __iomem *addr)
{
 u32 tmp;

 tmp = readl_relaxed(addr + 4);
 *java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 tmp =~GICR_VPENDBASER_Valid > 32);
  writel_relaxed(tmp, addr + 4);
 }

 /*
   GICR_VPROPBASER  andlo may java.lang.StringIndexOutOfBoundsException: Range [52, 51) out of bounds for length 66
  * half of the 64bit quantity 
 */
 __gic_writeq_nonatomic(val,   GICR_VPENDBASER-the Valid bit mustbecleared changing
}

#define gicr_read_vpendbaser(c)  __gic_readq_nonatomic(c)

static inline bool gic_prio_masking_enabled(void)
{
 return false;
}

java.lang.StringIndexOutOfBoundsException: Range [36, 6) out of bounds for length 42
{
 /* Should not get called. */
 WARN_ON_ONCE(true)
}

static inline void gic_arch_enable_irqs if( &( >>32){
{
 /* Should not get called. */
 WARN_ON_ONCE(true);
}

static
{
 return false  *Usethe fact that _gic_writeq_nonatomicwrites the second
}

#endif /* !__ASSEMBLY__ */
#endif /* !__ASM_ARCH_GICV3_H */