SSL ar9003_eeprom.c
Interaktion und
/* * Copyright (c) 2010-2011 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. #include <linux/unaligned.h>#include <linux/kernel.h>#include "hw.h" #include "ar9003_phy.h" #include "ar9003_eeprom.h" #include "ar9003_mci.h" #define COMP_HDR_LEN 4 #define COMP_CKSUM_LEN 2 #define LE16(x) cpu_to_le16(x)#define LE32(x) cpu_to_le32(x)/* Local defines to distinguish between extension and control CTL's */ #define EXT_ADDITIVE (0 x8000)#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6 ))#define EEPROM_DATA_LEN_9485 1088 static int ar9003_hw_power_interpolate(int32_t x,static const struct ar9300_eeprom ar9300_default = {2 ,2 ,0 , 2 , 3 , 4 , 5 , 6 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 },0 ), LE16(0 x1f) },0 x77, /* 4 bits tx and 4 bits rx */ 0 ,0 ,0 ,5 , /* takes lower byte in eeprom location */ 0 , 0 },0 x0c,/* * bit0 - enable tx temp comp - disabled * bit1 - enable tx volt comp - disabled * bit2 - enable fastClock - enabled * bit3 - enable doubling - enabled * bit4 - enable internal regulator - disabled * bit5 - enable pa predistortion - disabled 0 , /* bit0 - turn down drivestrength */ 3 ,0 ,8 ,0 xff,0 ,0 ,/* ar9300_modal_eep_header 2g */ /* 4 idle,t1,t2,b(4 bits per setting) */ 0 x110),/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 0 x22222),/* * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, * rx1, rx12, b (2 bits each) 0 x150), LE16(0 x150), LE16(0 x150) },/* * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db * for ar9280 (0xa20c/b20c 5:0) 0 , 0 , 0 },/* * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin * for ar9280 (0xa20c/b20c 16:12 0 , 0 , 0 },36 ,0 ,/* * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur * channels in usual fbin coding format 0 , 0 , 0 , 0 , 0 },/* * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check * if the register is per chain 1 , 0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 },0 ,0 ,0 x0e,0 x0e,3 , /* 4 bits tx_clip, 4 bits dac_scale_cck */ 0 ,0 x2c,30 ,0 ,0 x2,0 xe,28 ,0 x0cf0e0e0),0 x6cf0e0e0),0 ,0 ,0 , 0 , 0 , 0 , 0 , 0 , 0 ,0 ,0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 }2412 , 1 ),2437 , 1 ),2472 , 1 ),/* ar9300_cal_data_per_freq_op_loop 2g */ 0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },2412 , 1 ),2484 , 1 ),2412 , 1 ),2437 , 1 ),2472 , 1 )2412 , 1 ),2437 , 1 ),2472 , 1 )2412 , 1 ),2437 , 1 ),2472 , 1 )/* 1L-5L,5S,11L,11S */ 36 , 36 , 36 , 36 } },36 , 36 , 36 , 36 } },/* 6-24,36,48,54 */ 32 , 32 , 28 , 24 } },32 , 32 , 28 , 24 } },32 , 32 , 28 , 24 } },32 , 32 , 32 , 32 , 28 , 20 , 32 , 32 , 28 , 20 , 32 , 32 , 28 , 20 } },32 , 32 , 32 , 32 , 28 , 20 , 32 , 32 , 28 , 20 , 32 , 32 , 28 , 20 } },32 , 32 , 32 , 32 , 28 , 20 , 32 , 32 , 28 , 20 , 32 , 32 , 28 , 20 } },32 , 32 , 32 , 32 , 28 , 20 , 32 , 32 , 28 , 20 , 32 , 32 , 28 , 20 } },32 , 32 , 32 , 32 , 28 , 20 , 32 , 32 , 28 , 20 , 32 , 32 , 28 , 20 } },32 , 32 , 32 , 32 , 28 , 20 , 32 , 32 , 28 , 20 , 32 , 32 , 28 , 20 } },0 x11, 0 x12, 0 x15, 0 x17, 0 x41, 0 x42,0 x45, 0 x47, 0 x31, 0 x32, 0 x35, 0 x37,2412 , 1 ),2417 , 1 ),2457 , 1 ),2462 , 1 )2412 , 1 ),2417 , 1 ),2462 , 1 ),0 xFF,2412 , 1 ),2417 , 1 ),2462 , 1 ),0 xFF,2422 , 1 ),2427 , 1 ),2447 , 1 ),2452 , 1 )/* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 0 ,/* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2472 , 1 ),0 ,/* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 0 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 0 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 1 ) } },60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ) } },/* 4 idle,t1,t2,b (4 bits per setting) */ 0 x110),/* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 0 x22222),/* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 0 x000), LE16(0 x000), LE16(0 x000),/* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 0 , 0 , 0 },/* * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin * for merlin (0xa20c/b20c 16:12 0 , 0 , 0 },68 ,0 ,/* spurChans spur channels in usual fbin coding format */ 0 , 0 , 0 , 0 , 0 },/* noiseFloorThreshCh Check if the register is per chain */ 1 , 0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 },0 ,0 ,0 x0e,0 x0e,3 , /* 4 bits tx_clip, 4 bits dac_scale_cck */ 0 ,0 x2d,30 ,0 ,0 x2,0 xe,28 ,0 x0c80c080),0 x0080c080),0 ,0 ,0 , 0 , 0 , 0 , 0 , 0 , 0 ,0 ,0 ,0 , 0 , 0 },0 , 0 , 0 },0 , 0 , 0 },0 , 0 , 0 }5180 , 0 ),5220 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5600 , 0 ),5725 , 0 ),5825 , 0 )0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },5180 , 0 ),5220 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5600 , 0 ),5725 , 0 ),5825 , 0 )5180 , 0 ),5240 , 0 ),5320 , 0 ),5500 , 0 ),5700 , 0 ),5745 , 0 ),5725 , 0 ),5825 , 0 )5180 , 0 ),5240 , 0 ),5320 , 0 ),5500 , 0 ),5700 , 0 ),5745 , 0 ),5725 , 0 ),5825 , 0 )/* 6-24,36,48,54 */ 20 , 20 , 20 , 10 } },20 , 20 , 20 , 10 } },20 , 20 , 20 , 10 } },20 , 20 , 20 , 10 } },20 , 20 , 20 , 10 } },20 , 20 , 20 , 10 } },20 , 20 , 20 , 10 } },20 , 20 , 20 , 10 } },/* * 0_8_16,1-3_9-11_17-19, * 4,5,6,7,12,13,14,15,20,21,22,23 20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },/* * 0_8_16,1-3_9-11_17-19, * 4,5,6,7,12,13,14,15,20,21,22,23 20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },20 , 20 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 , 10 , 10 , 0 , 0 } },0 x10, 0 x16, 0 x18, 0 x40, 0 x46,0 x48, 0 x30, 0 x36, 0 x38/* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[3].ctlEdges[6].bChannel */ 0xFF, /* Data[3].ctlEdges[7].bChannel */ 0xFF, /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), /* Data[4].ctlEdges[4].bChannel */ 0xFF, /* Data[4].ctlEdges[5].bChannel */ 0xFF, /* Data[4].ctlEdges[6].bChannel */ 0xFF, /* Data[4].ctlEdges[7].bChannel */ 0xFF, /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), /* Data[5].ctlEdges[6].bChannel */ 0xFF, /* Data[5].ctlEdges[7].bChannel */ 0xFF /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) 60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),static const struct ar9300_eeprom ar9300_x113 = {2 ,6 ,0 x00, 0 x03, 0 x7f, 0 x0, 0 x0, 0 x0},"x113-023-f0000" },0 ), LE16(0 x1f) },0 x77, /* 4 bits tx and 4 bits rx */ 0 ,0 ,0 ,5 , /* takes lower byte in eeprom location */ 0 , 0 },0 x0d,/* * bit0 - enable tx temp comp - disabled * bit1 - enable tx volt comp - disabled * bit2 - enable fastClock - enabled * bit3 - enable doubling - enabled * bit4 - enable internal regulator - disabled * bit5 - enable pa predistortion - disabled 0 , /* bit0 - turn down drivestrength */ 6 ,0 ,8 ,0 xff,0 x21,0 ,/* ar9300_modal_eep_header 2g */ /* 4 idle,t1,t2,b(4 bits per setting) */ 0 x110),/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 0 x44444),/* * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, * rx1, rx12, b (2 bits each) 0 x150), LE16(0 x150), LE16(0 x150) },/* * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db * for ar9280 (0xa20c/b20c 5:0) 0 , 0 , 0 },/* * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin * for ar9280 (0xa20c/b20c 16:12 0 , 0 , 0 },25 ,0 ,/* * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur * channels in usual fbin coding format 2464 , 1 ), 0 , 0 , 0 , 0 },/* * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check * if the register is per chain 1 , 0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 },0 ,0 ,0 x0e,0 x0e,3 , /* 4 bits tx_clip, 4 bits dac_scale_cck */ 0 ,0 x2c,30 ,0 ,0 x2,0 xe,28 ,0 x0c80c080),0 x0080c080),0 ,0 ,0 , 0 , 0 , 0 , 0 , 0 , 0 ,0 ,0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 }2412 , 1 ),2437 , 1 ),2472 , 1 ),/* ar9300_cal_data_per_freq_op_loop 2g */ 0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },2412 , 1 ),2472 , 1 ),2412 , 1 ),2437 , 1 ),2472 , 1 )2412 , 1 ),2437 , 1 ),2472 , 1 )2412 , 1 ),2437 , 1 ),2472 , 1 )/* 1L-5L,5S,11L,11S */ 34 , 34 , 34 , 34 } },34 , 34 , 34 , 34 } },/* 6-24,36,48,54 */ 34 , 34 , 32 , 32 } },34 , 34 , 32 , 32 } },34 , 34 , 32 , 32 } },32 , 32 , 32 , 32 , 32 , 28 , 32 , 32 , 30 , 28 , 0 , 0 , 0 , 0 } },32 , 32 , 32 , 32 , 32 , 28 , 32 , 32 , 30 , 28 , 0 , 0 , 0 , 0 } },32 , 32 , 32 , 32 , 32 , 28 , 32 , 32 , 30 , 28 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 30 , 30 , 28 , 30 , 30 , 28 , 26 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 30 , 30 , 28 , 30 , 30 , 28 , 26 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 30 , 30 , 28 , 30 , 30 , 28 , 26 , 0 , 0 , 0 , 0 } },0 x11, 0 x12, 0 x15, 0 x17, 0 x41, 0 x42,0 x45, 0 x47, 0 x31, 0 x32, 0 x35, 0 x37,2412 , 1 ),2417 , 1 ),2457 , 1 ),2462 , 1 )2412 , 1 ),2417 , 1 ),2462 , 1 ),0 xFF,2412 , 1 ),2417 , 1 ),2462 , 1 ),0 xFF,2422 , 1 ),2427 , 1 ),2447 , 1 ),2452 , 1 )/* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 0 ,/* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2472 , 1 ),0 ,/* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 0 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 0 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 1 ) } },60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ) } },/* 4 idle,t1,t2,b (4 bits per setting) */ 0 x220),/* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 0 x11111),/* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 0 x150), LE16(0 x150), LE16(0 x150),/* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 0 , 0 , 0 },/* * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin * for merlin (0xa20c/b20c 16:12 0 , 0 , 0 },68 ,0 ,/* spurChans spur channels in usual fbin coding format */ 5500 , 0 ), 0 , 0 , 0 , 0 },/* noiseFloorThreshCh Check if the register is per chain */ 1 , 0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 },0 ,0 xf,0 x0e,0 x0e,3 , /* 4 bits tx_clip, 4 bits dac_scale_cck */ 0 ,0 x2d,30 ,0 ,0 x2,0 xe,28 ,0 x0cf0e0e0),0 x6cf0e0e0),0 ,0 ,0 , 0 , 0 , 0 , 0 , 0 , 0 ,72 ,105 ,0 , 0 , 0 },0 , 0 , 0 },0 , 0 , 0 },0 , 0 , 0 }5180 , 0 ),5240 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5600 , 0 ),5745 , 0 ),5785 , 0 )0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },5180 , 0 ),5220 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5600 , 0 ),5745 , 0 ),5785 , 0 )5180 , 0 ),5240 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5700 , 0 ),5745 , 0 ),5825 , 0 )5190 , 0 ),5230 , 0 ),5320 , 0 ),5410 , 0 ),5510 , 0 ),5670 , 0 ),5755 , 0 ),5825 , 0 )/* 6-24,36,48,54 */ 42 , 40 , 40 , 34 } },42 , 40 , 40 , 34 } },42 , 40 , 40 , 34 } },42 , 40 , 40 , 34 } },42 , 40 , 40 , 34 } },42 , 40 , 40 , 34 } },42 , 40 , 40 , 34 } },42 , 40 , 40 , 34 } },/* * 0_8_16,1-3_9-11_17-19, * 4,5,6,7,12,13,14,15,20,21,22,23 40 , 40 , 40 , 40 , 32 , 28 , 40 , 40 , 32 , 28 , 40 , 40 , 32 , 20 } },40 , 40 , 40 , 40 , 32 , 28 , 40 , 40 , 32 , 28 , 40 , 40 , 32 , 20 } },40 , 40 , 40 , 40 , 32 , 28 , 40 , 40 , 32 , 28 , 40 , 40 , 32 , 20 } },40 , 40 , 40 , 40 , 32 , 28 , 40 , 40 , 32 , 28 , 40 , 40 , 32 , 20 } },40 , 40 , 40 , 40 , 32 , 28 , 40 , 40 , 32 , 28 , 40 , 40 , 32 , 20 } },40 , 40 , 40 , 40 , 32 , 28 , 40 , 40 , 32 , 28 , 40 , 40 , 32 , 20 } },38 , 38 , 38 , 38 , 32 , 28 , 38 , 38 , 32 , 28 , 38 , 38 , 32 , 26 } },36 , 36 , 36 , 36 , 32 , 28 , 36 , 36 , 32 , 28 , 36 , 36 , 32 , 26 } },/* * 0_8_16,1-3_9-11_17-19, * 4,5,6,7,12,13,14,15,20,21,22,23 40 , 40 , 40 , 38 , 30 , 26 , 40 , 40 , 30 , 26 , 40 , 40 , 30 , 24 } },40 , 40 , 40 , 38 , 30 , 26 , 40 , 40 , 30 , 26 , 40 , 40 , 30 , 24 } },40 , 40 , 40 , 38 , 30 , 26 , 40 , 40 , 30 , 26 , 40 , 40 , 30 , 24 } },40 , 40 , 40 , 38 , 30 , 26 , 40 , 40 , 30 , 26 , 40 , 40 , 30 , 24 } },40 , 40 , 40 , 38 , 30 , 26 , 40 , 40 , 30 , 26 , 40 , 40 , 30 , 24 } },40 , 40 , 40 , 38 , 30 , 26 , 40 , 40 , 30 , 26 , 40 , 40 , 30 , 24 } },36 , 36 , 36 , 36 , 30 , 26 , 36 , 36 , 30 , 26 , 36 , 36 , 30 , 24 } },34 , 34 , 34 , 34 , 30 , 26 , 34 , 34 , 30 , 26 , 34 , 34 , 30 , 24 } },0 x10, 0 x16, 0 x18, 0 x40, 0 x46,0 x48, 0 x30, 0 x36, 0 x38/* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[3].ctlEdges[6].bChannel */ 0xFF, /* Data[3].ctlEdges[7].bChannel */ 0xFF, /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), /* Data[4].ctlEdges[4].bChannel */ 0xFF, /* Data[4].ctlEdges[5].bChannel */ 0xFF, /* Data[4].ctlEdges[6].bChannel */ 0xFF, /* Data[4].ctlEdges[7].bChannel */ 0xFF, /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), /* Data[5].ctlEdges[6].bChannel */ 0xFF, /* Data[5].ctlEdges[7].bChannel */ 0xFF /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) 60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),static const struct ar9300_eeprom ar9300_h112 = {2 ,3 ,0 x00, 0 x03, 0 x7f, 0 x0, 0 x0, 0 x0},"h112-241-f0000" },0 ), LE16(0 x1f) },0 x77, /* 4 bits tx and 4 bits rx */ 0 ,0 ,0 ,5 , /* takes lower byte in eeprom location */ 0 , 0 },0 x0d,/* * bit0 - enable tx temp comp - disabled * bit1 - enable tx volt comp - disabled * bit2 - enable fastClock - enabled * bit3 - enable doubling - enabled * bit4 - enable internal regulator - disabled * bit5 - enable pa predistortion - disabled 0 , /* bit0 - turn down drivestrength */ 6 ,0 ,8 ,0 xff,0 x10,0 ,/* ar9300_modal_eep_header 2g */ /* 4 idle,t1,t2,b(4 bits per setting) */ 0 x110),/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 0 x44444),/* * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, * rx1, rx12, b (2 bits each) 0 x150), LE16(0 x150), LE16(0 x150) },/* * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db * for ar9280 (0xa20c/b20c 5:0) 0 , 0 , 0 },/* * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin * for ar9280 (0xa20c/b20c 16:12 0 , 0 , 0 },25 ,0 ,/* * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur * channels in usual fbin coding format 2464 , 1 ), 0 , 0 , 0 , 0 },/* * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check * if the register is per chain 1 , 0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 },0 ,0 ,0 x0e,0 x0e,3 , /* 4 bits tx_clip, 4 bits dac_scale_cck */ 0 ,0 x2c,30 ,0 ,0 x2,0 xe,28 ,0 x0c80c080),0 x0080c080),0 ,0 ,0 , 0 , 0 , 0 , 0 , 0 , 0 ,0 ,0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 }2412 , 1 ),2437 , 1 ),2462 , 1 ),/* ar9300_cal_data_per_freq_op_loop 2g */ 0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },2412 , 1 ),2472 , 1 ),2412 , 1 ),2437 , 1 ),2472 , 1 )2412 , 1 ),2437 , 1 ),2472 , 1 )2412 , 1 ),2437 , 1 ),2472 , 1 )/* 1L-5L,5S,11L,11S */ 34 , 34 , 34 , 34 } },34 , 34 , 34 , 34 } },/* 6-24,36,48,54 */ 34 , 34 , 32 , 32 } },34 , 34 , 32 , 32 } },34 , 34 , 32 , 32 } },32 , 32 , 32 , 32 , 32 , 30 , 32 , 32 , 30 , 28 , 28 , 28 , 28 , 24 } },32 , 32 , 32 , 32 , 32 , 30 , 32 , 32 , 30 , 28 , 28 , 28 , 28 , 24 } },32 , 32 , 32 , 32 , 32 , 30 , 32 , 32 , 30 , 28 , 28 , 28 , 28 , 24 } },30 , 30 , 30 , 30 , 30 , 28 , 30 , 30 , 28 , 26 , 26 , 26 , 26 , 22 } },30 , 30 , 30 , 30 , 30 , 28 , 30 , 30 , 28 , 26 , 26 , 26 , 26 , 22 } },30 , 30 , 30 , 30 , 30 , 28 , 30 , 30 , 28 , 26 , 26 , 26 , 26 , 22 } },0 x11, 0 x12, 0 x15, 0 x17, 0 x41, 0 x42,0 x45, 0 x47, 0 x31, 0 x32, 0 x35, 0 x37,2412 , 1 ),2417 , 1 ),2457 , 1 ),2462 , 1 )2412 , 1 ),2417 , 1 ),2462 , 1 ),0 xFF,2412 , 1 ),2417 , 1 ),2462 , 1 ),0 xFF,2422 , 1 ),2427 , 1 ),2447 , 1 ),2452 , 1 )/* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 0 ,/* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2472 , 1 ),0 ,/* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 0 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 0 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 1 ) } },60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ) } },/* 4 idle,t1,t2,b (4 bits per setting) */ 0 x220),/* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 0 x44444),/* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 0 x150), LE16(0 x150), LE16(0 x150),/* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 0 , 0 , 0 },/* * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin * for merlin (0xa20c/b20c 16:12 0 , 0 , 0 },45 ,0 ,/* spurChans spur channels in usual fbin coding format */ 0 , 0 , 0 , 0 , 0 },/* noiseFloorThreshCh Check if the register is per chain */ 1 , 0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 },0 ,0 ,0 x0e,0 x0e,3 , /* 4 bits tx_clip, 4 bits dac_scale_cck */ 0 ,0 x2d,30 ,0 ,0 x2,0 xe,28 ,0 x0cf0e0e0),0 x6cf0e0e0),0 ,0 ,0 , 0 , 0 , 0 , 0 , 0 , 0 ,40 ,50 ,0 , 0 , 0 },0 , 0 , 0 },0 , 0 , 0 },0 , 0 , 0 }5180 , 0 ),5220 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5600 , 0 ),5700 , 0 ),5785 , 0 )0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },5180 , 0 ),5240 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5600 , 0 ),5700 , 0 ),5825 , 0 )5180 , 0 ),5240 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5700 , 0 ),5745 , 0 ),5825 , 0 )5180 , 0 ),5240 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5700 , 0 ),5745 , 0 ),5825 , 0 )/* 6-24,36,48,54 */ 30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },/* * 0_8_16,1-3_9-11_17-19, * 4,5,6,7,12,13,14,15,20,21,22,23 30 , 30 , 30 , 28 , 24 , 20 , 30 , 28 , 24 , 20 , 20 , 20 , 20 , 16 } },30 , 30 , 30 , 28 , 24 , 20 , 30 , 28 , 24 , 20 , 20 , 20 , 20 , 16 } },30 , 30 , 30 , 26 , 22 , 18 , 30 , 26 , 22 , 18 , 18 , 18 , 18 , 16 } },30 , 30 , 30 , 26 , 22 , 18 , 30 , 26 , 22 , 18 , 18 , 18 , 18 , 16 } },30 , 30 , 30 , 24 , 20 , 16 , 30 , 24 , 20 , 16 , 16 , 16 , 16 , 14 } },30 , 30 , 30 , 24 , 20 , 16 , 30 , 24 , 20 , 16 , 16 , 16 , 16 , 14 } },30 , 30 , 30 , 22 , 18 , 14 , 30 , 22 , 18 , 14 , 14 , 14 , 14 , 12 } },30 , 30 , 30 , 22 , 18 , 14 , 30 , 22 , 18 , 14 , 14 , 14 , 14 , 12 } },/* * 0_8_16,1-3_9-11_17-19, * 4,5,6,7,12,13,14,15,20,21,22,23 28 , 28 , 28 , 26 , 22 , 18 , 28 , 26 , 22 , 18 , 18 , 18 , 18 , 14 } },28 , 28 , 28 , 26 , 22 , 18 , 28 , 26 , 22 , 18 , 18 , 18 , 18 , 14 } },28 , 28 , 28 , 24 , 20 , 16 , 28 , 24 , 20 , 16 , 16 , 16 , 16 , 12 } },28 , 28 , 28 , 24 , 20 , 16 , 28 , 24 , 20 , 16 , 16 , 16 , 16 , 12 } },28 , 28 , 28 , 22 , 18 , 14 , 28 , 22 , 18 , 14 , 14 , 14 , 14 , 10 } },28 , 28 , 28 , 22 , 18 , 14 , 28 , 22 , 18 , 14 , 14 , 14 , 14 , 10 } },28 , 28 , 28 , 20 , 16 , 12 , 28 , 20 , 16 , 12 , 12 , 12 , 12 , 8 } },28 , 28 , 28 , 20 , 16 , 12 , 28 , 20 , 16 , 12 , 12 , 12 , 12 , 8 } },0 x10, 0 x16, 0 x18, 0 x40, 0 x46,0 x48, 0 x30, 0 x36, 0 x38/* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[3].ctlEdges[6].bChannel */ 0xFF, /* Data[3].ctlEdges[7].bChannel */ 0xFF, /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), /* Data[4].ctlEdges[4].bChannel */ 0xFF, /* Data[4].ctlEdges[5].bChannel */ 0xFF, /* Data[4].ctlEdges[6].bChannel */ 0xFF, /* Data[4].ctlEdges[7].bChannel */ 0xFF, /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), /* Data[5].ctlEdges[6].bChannel */ 0xFF, /* Data[5].ctlEdges[7].bChannel */ 0xFF /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) 60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),static const struct ar9300_eeprom ar9300_x112 = {2 ,5 ,0 x00, 0 x03, 0 x7f, 0 x0, 0 x0, 0 x0},"x112-041-f0000" },0 ), LE16(0 x1f) },0 x77, /* 4 bits tx and 4 bits rx */ 0 ,0 ,0 ,5 , /* takes lower byte in eeprom location */ 0 , 0 },0 x0d,/* * bit0 - enable tx temp comp - disabled * bit1 - enable tx volt comp - disabled * bit2 - enable fastclock - enabled * bit3 - enable doubling - enabled * bit4 - enable internal regulator - disabled * bit5 - enable pa predistortion - disabled 0 , /* bit0 - turn down drivestrength */ 6 ,0 ,8 ,0 xff,0 x0,0 ,/* ar9300_modal_eep_header 2g */ /* 4 idle,t1,t2,b(4 bits per setting) */ 0 x110),/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 0 x22222),/* * antCtrlChain[ar9300_max_chains]; 6 idle, t, r, * rx1, rx12, b (2 bits each) 0 x10), LE16(0 x10), LE16(0 x10) },/* * xatten1DB[AR9300_max_chains]; 3 xatten1_db * for ar9280 (0xa20c/b20c 5:0) 0 x1b, 0 x1b, 0 x1b},/* * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin * for ar9280 (0xa20c/b20c 16:12 0 x15, 0 x15, 0 x15},50 ,0 ,/* * spurChans[OSPrey_eeprom_modal_sPURS]; spur * channels in usual fbin coding format 2464 , 1 ), 0 , 0 , 0 , 0 },/* * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check * if the register is per chain 1 , 0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 },0 ,0 ,0 x0e,0 x0e,3 , /* 4 bits tx_clip, 4 bits dac_scale_cck */ 0 ,0 x2c,30 ,0 ,0 x2,0 xe,28 ,0 x0c80c080),0 x0080c080),0 ,0 ,0 , 0 , 0 , 0 , 0 , 0 , 0 ,0 ,0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 }2412 , 1 ),2437 , 1 ),2472 , 1 ),/* ar9300_cal_data_per_freq_op_loop 2g */ 0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },2412 , 1 ),2472 , 1 ),2412 , 1 ),2437 , 1 ),2472 , 1 )2412 , 1 ),2437 , 1 ),2472 , 1 )2412 , 1 ),2437 , 1 ),2472 , 1 )/* 1L-5L,5S,11L,11s */ 38 , 38 , 38 , 38 } },38 , 38 , 38 , 38 } },/* 6-24,36,48,54 */ 38 , 38 , 36 , 34 } },38 , 38 , 36 , 34 } },38 , 38 , 34 , 32 } },36 , 36 , 36 , 36 , 36 , 34 , 34 , 32 , 30 , 28 , 28 , 28 , 28 , 26 } },36 , 36 , 36 , 36 , 36 , 34 , 36 , 34 , 32 , 30 , 30 , 30 , 28 , 26 } },36 , 36 , 36 , 36 , 36 , 34 , 34 , 32 , 30 , 28 , 28 , 28 , 28 , 26 } },36 , 36 , 36 , 36 , 34 , 32 , 32 , 30 , 28 , 26 , 26 , 26 , 26 , 24 } },36 , 36 , 36 , 36 , 34 , 32 , 34 , 32 , 30 , 28 , 28 , 28 , 28 , 24 } },36 , 36 , 36 , 36 , 34 , 32 , 32 , 30 , 28 , 26 , 26 , 26 , 26 , 24 } },0 x11, 0 x12, 0 x15, 0 x17, 0 x41, 0 x42,0 x45, 0 x47, 0 x31, 0 x32, 0 x35, 0 x37,2412 , 1 ),2417 , 1 ),2457 , 1 ),2462 , 1 )2412 , 1 ),2417 , 1 ),2462 , 1 ),0 xFF,2412 , 1 ),2417 , 1 ),2462 , 1 ),0 xFF,2422 , 1 ),2427 , 1 ),2447 , 1 ),2452 , 1 )/* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1), /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 0 ,/* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 2472 , 1 ),0 ,/* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1), /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1), /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1), /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1), /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 0 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 0 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1), /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1), /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1), /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1), 60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 1 ) } },60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ) } },/* 4 idle,t1,t2,b (4 bits per setting) */ 0 x110),/* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 0 x22222),/* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 0 x0), LE16(0 x0), LE16(0 x0),/* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */ 0 x13, 0 x19, 0 x17},/* * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin * for merlin (0xa20c/b20c 16:12 0 x19, 0 x19, 0 x19},70 ,15 ,/* spurChans spur channels in usual fbin coding format */ 0 , 0 , 0 , 0 , 0 },/* noiseFloorThreshch check if the register is per chain */ 1 , 0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 },0 ,0 ,0 x0e,0 x0e,3 , /* 4 bits tx_clip, 4 bits dac_scale_cck */ 0 ,0 x2d,30 ,0 ,0 x2,0 xe,28 ,0 x0cf0e0e0),0 x6cf0e0e0),0 ,0 ,0 , 0 , 0 , 0 , 0 , 0 , 0 ,72 ,105 ,0 x10, 0 x14, 0 x10},0 x19, 0 x19 , 0 x19},0 x1d, 0 x20, 0 x24},0 x10, 0 x10, 0 x10}5180 , 0 ),5220 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5600 , 0 ),5700 , 0 ),5785 , 0 )0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },5180 , 0 ),5220 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5600 , 0 ),5725 , 0 ),5825 , 0 )5180 , 0 ),5220 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5600 , 0 ),5725 , 0 ),5825 , 0 )5180 , 0 ),5220 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5600 , 0 ),5725 , 0 ),5825 , 0 )/* 6-24,36,48,54 */ 32 , 32 , 28 , 26 } },32 , 32 , 28 , 26 } },32 , 32 , 28 , 26 } },32 , 32 , 26 , 24 } },32 , 32 , 26 , 24 } },32 , 32 , 24 , 22 } },30 , 30 , 24 , 22 } },30 , 30 , 24 , 22 } },/* * 0_8_16,1-3_9-11_17-19, * 4,5,6,7,12,13,14,15,20,21,22,23 32 , 32 , 32 , 32 , 28 , 26 , 32 , 28 , 26 , 24 , 24 , 24 , 22 , 22 } },32 , 32 , 32 , 32 , 28 , 26 , 32 , 28 , 26 , 24 , 24 , 24 , 22 , 22 } },32 , 32 , 32 , 32 , 28 , 26 , 32 , 28 , 26 , 24 , 24 , 24 , 22 , 22 } },32 , 32 , 32 , 32 , 28 , 26 , 32 , 26 , 24 , 22 , 22 , 22 , 20 , 20 } },32 , 32 , 32 , 32 , 28 , 26 , 32 , 26 , 24 , 22 , 20 , 18 , 16 , 16 } },32 , 32 , 32 , 32 , 28 , 26 , 32 , 24 , 20 , 16 , 18 , 16 , 14 , 14 } },30 , 30 , 30 , 30 , 28 , 26 , 30 , 24 , 20 , 16 , 18 , 16 , 14 , 14 } },30 , 30 , 30 , 30 , 28 , 26 , 30 , 24 , 20 , 16 , 18 , 16 , 14 , 14 } },/* * 0_8_16,1-3_9-11_17-19, * 4,5,6,7,12,13,14,15,20,21,22,23 32 , 32 , 32 , 30 , 28 , 26 , 30 , 28 , 26 , 24 , 24 , 24 , 22 , 22 } },32 , 32 , 32 , 30 , 28 , 26 , 30 , 28 , 26 , 24 , 24 , 24 , 22 , 22 } },32 , 32 , 32 , 30 , 28 , 26 , 30 , 28 , 26 , 24 , 24 , 24 , 22 , 22 } },32 , 32 , 32 , 30 , 28 , 26 , 30 , 26 , 24 , 22 , 22 , 22 , 20 , 20 } },32 , 32 , 32 , 30 , 28 , 26 , 30 , 26 , 24 , 22 , 20 , 18 , 16 , 16 } },32 , 32 , 32 , 30 , 28 , 26 , 30 , 22 , 20 , 16 , 18 , 16 , 14 , 14 } },30 , 30 , 30 , 30 , 28 , 26 , 30 , 22 , 20 , 16 , 18 , 16 , 14 , 14 } },30 , 30 , 30 , 30 , 28 , 26 , 30 , 22 , 20 , 16 , 18 , 16 , 14 , 14 } },0 x10, 0 x16, 0 x18, 0 x40, 0 x46,0 x48, 0 x30, 0 x36, 0 x38/* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0), /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0), /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0), /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0), /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0), /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0), /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0), /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0), /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0), /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0), /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0) /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0), /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0), /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0), /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0), /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), /* Data[3].ctledges[6].bchannel */ 0xFF, /* Data[3].ctledges[7].bchannel */ 0xFF, /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0), /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0), /* Data[4].ctledges[4].bchannel */ 0xFF, /* Data[4].ctledges[5].bchannel */ 0xFF, /* Data[4].ctledges[6].bchannel */ 0xFF, /* Data[4].ctledges[7].bchannel */ 0xFF, /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0), /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0), /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0), /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0), /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0), /* Data[5].ctledges[6].bchannel */ 0xFF, /* Data[5].ctledges[7].bchannel */ 0xFF /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0), /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0), /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0), /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0), /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0), /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0), /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0) /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0), /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0), /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0), /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0), /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0), /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0), /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0), /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0), /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0) 60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),static const struct ar9300_eeprom ar9300_h116 = {2 ,4 ,0 x00, 0 x03, 0 x7f, 0 x0, 0 x0, 0 x0},"h116-041-f0000" },0 ), LE16(0 x1f) },0 x33, /* 4 bits tx and 4 bits rx */ 0 ,0 ,0 ,5 , /* takes lower byte in eeprom location */ 0 , 0 },0 x0d,/* * bit0 - enable tx temp comp - disabled * bit1 - enable tx volt comp - disabled * bit2 - enable fastClock - enabled * bit3 - enable doubling - enabled * bit4 - enable internal regulator - disabled * bit5 - enable pa predistortion - disabled 0 , /* bit0 - turn down drivestrength */ 6 ,0 ,8 ,0 xff,0 x10,0 ,/* ar9300_modal_eep_header 2g */ /* 4 idle,t1,t2,b(4 bits per setting) */ 0 x110),/* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 0 x44444),/* * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, * rx1, rx12, b (2 bits each) 0 x10), LE16(0 x10), LE16(0 x10) },/* * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db * for ar9280 (0xa20c/b20c 5:0) 0 x1f, 0 x1f, 0 x1f},/* * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin * for ar9280 (0xa20c/b20c 16:12 0 x12, 0 x12, 0 x12},25 ,0 ,/* * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur * channels in usual fbin coding format 2464 , 1 ), 0 , 0 , 0 , 0 },/* * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check * if the register is per chain 1 , 0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 },0 ,0 ,0 x0e,0 x0e,3 , /* 4 bits tx_clip, 4 bits dac_scale_cck */ 0 ,0 x2c,30 ,0 ,0 x2,0 xe,28 ,0 x0c80C080),0 x0080C080),0 ,0 ,0 , 0 , 0 , 0 , 0 , 0 , 0 ,0 ,0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 }2412 , 1 ),2437 , 1 ),2462 , 1 ),/* ar9300_cal_data_per_freq_op_loop 2g */ 0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 }, {0 , 0 , 0 , 0 , 0 , 0 } },2412 , 1 ),2472 , 1 ),2412 , 1 ),2437 , 1 ),2472 , 1 )2412 , 1 ),2437 , 1 ),2472 , 1 )2412 , 1 ),2437 , 1 ),2472 , 1 )/* 1L-5L,5S,11L,11S */ 34 , 34 , 34 , 34 } },34 , 34 , 34 , 34 } },/* 6-24,36,48,54 */ 34 , 34 , 32 , 32 } },34 , 34 , 32 , 32 } },34 , 34 , 32 , 32 } },32 , 32 , 32 , 32 , 32 , 30 , 32 , 32 , 30 , 28 , 0 , 0 , 0 , 0 } },32 , 32 , 32 , 32 , 32 , 30 , 32 , 32 , 30 , 28 , 0 , 0 , 0 , 0 } },32 , 32 , 32 , 32 , 32 , 30 , 32 , 32 , 30 , 28 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 30 , 30 , 28 , 30 , 30 , 28 , 26 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 30 , 30 , 28 , 30 , 30 , 28 , 26 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 30 , 30 , 28 , 30 , 30 , 28 , 26 , 0 , 0 , 0 , 0 } },0 x11, 0 x12, 0 x15, 0 x17, 0 x41, 0 x42,0 x45, 0 x47, 0 x31, 0 x32, 0 x35, 0 x37,2412 , 1 ),2417 , 1 ),2457 , 1 ),2462 , 1 )2412 , 1 ),2417 , 1 ),2462 , 1 ),0 xFF,2412 , 1 ),2417 , 1 ),2462 , 1 ),0 xFF,2422 , 1 ),2427 , 1 ),2447 , 1 ),2452 , 1 )/* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 0 ,/* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2472 , 1 ),0 ,/* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 0 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 0 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 1 ) } },60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ) } },60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ) } },/* 4 idle,t1,t2,b (4 bits per setting) */ 0 x220),/* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 0 x44444),/* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 0 x150), LE16(0 x150), LE16(0 x150),/* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 0 x19, 0 x19, 0 x19},/* * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin * for merlin (0xa20c/b20c 16:12 0 x14, 0 x14, 0 x14},70 ,0 ,/* spurChans spur channels in usual fbin coding format */ 0 , 0 , 0 , 0 , 0 },/* noiseFloorThreshCh Check if the register is per chain */ 1 , 0 , 0 },0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 },0 ,0 ,0 x0e,0 x0e,3 , /* 4 bits tx_clip, 4 bits dac_scale_cck */ 0 ,0 x2d,30 ,0 ,0 x2,0 xe,28 ,0 x0cf0e0e0),0 x6cf0e0e0),0 ,0 ,0 , 0 , 0 , 0 , 0 , 0 , 0 ,35 ,50 ,0 , 0 , 0 },0 , 0 , 0 },0 , 0 , 0 },0 , 0 , 0 }5160 , 0 ),5220 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5600 , 0 ),5700 , 0 ),5785 , 0 )0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },0 , 0 , 0 , 0 , 0 },5180 , 0 ),5240 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5600 , 0 ),5700 , 0 ),5825 , 0 )5180 , 0 ),5240 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5700 , 0 ),5745 , 0 ),5825 , 0 )5180 , 0 ),5240 , 0 ),5320 , 0 ),5400 , 0 ),5500 , 0 ),5700 , 0 ),5745 , 0 ),5825 , 0 )/* 6-24,36,48,54 */ 30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },30 , 30 , 28 , 24 } },/* * 0_8_16,1-3_9-11_17-19, * 4,5,6,7,12,13,14,15,20,21,22,23 30 , 30 , 30 , 28 , 24 , 20 , 30 , 28 , 24 , 20 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 28 , 24 , 20 , 30 , 28 , 24 , 20 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 26 , 22 , 18 , 30 , 26 , 22 , 18 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 26 , 22 , 18 , 30 , 26 , 22 , 18 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 24 , 20 , 16 , 30 , 24 , 20 , 16 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 24 , 20 , 16 , 30 , 24 , 20 , 16 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 22 , 18 , 14 , 30 , 22 , 18 , 14 , 0 , 0 , 0 , 0 } },30 , 30 , 30 , 22 , 18 , 14 , 30 , 22 , 18 , 14 , 0 , 0 , 0 , 0 } },/* * 0_8_16,1-3_9-11_17-19, * 4,5,6,7,12,13,14,15,20,21,22,23 28 , 28 , 28 , 26 , 22 , 18 , 28 , 26 , 22 , 18 , 0 , 0 , 0 , 0 } },28 , 28 , 28 , 26 , 22 , 18 , 28 , 26 , 22 , 18 , 0 , 0 , 0 , 0 } },28 , 28 , 28 , 24 , 20 , 16 , 28 , 24 , 20 , 16 , 0 , 0 , 0 , 0 } },28 , 28 , 28 , 24 , 20 , 16 , 28 , 24 , 20 , 16 , 0 , 0 , 0 , 0 } },28 , 28 , 28 , 22 , 18 , 14 , 28 , 22 , 18 , 14 , 0 , 0 , 0 , 0 } },28 , 28 , 28 , 22 , 18 , 14 , 28 , 22 , 18 , 14 , 0 , 0 , 0 , 0 } },28 , 28 , 28 , 20 , 16 , 12 , 28 , 20 , 16 , 12 , 0 , 0 , 0 , 0 } },28 , 28 , 28 , 20 , 16 , 12 , 28 , 20 , 16 , 12 , 0 , 0 , 0 , 0 } },0 x10, 0 x16, 0 x18, 0 x40, 0 x46,0 x48, 0 x30, 0 x36, 0 x38/* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[3].ctlEdges[6].bChannel */ 0xFF, /* Data[3].ctlEdges[7].bChannel */ 0xFF, /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), /* Data[4].ctlEdges[4].bChannel */ 0xFF, /* Data[4].ctlEdges[5].bChannel */ 0xFF, /* Data[4].ctlEdges[6].bChannel */ 0xFF, /* Data[4].ctlEdges[7].bChannel */ 0xFF, /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), /* Data[5].ctlEdges[6].bChannel */ 0xFF, /* Data[5].ctlEdges[7].bChannel */ 0xFF /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) 60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 0 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 0 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ),60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ), CTL(60 , 1 ),60 , 1 ), CTL(60 , 1 ), CTL(60 , 0 ), CTL(60 , 1 ),static const struct ar9300_eeprom *ar9300_eep_templates[] = {static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)int it;for (it = 0 ; it < ARRAY_SIZE(ar9300_eep_templates); it++)if (ar9300_eep_templates[it]->templateVersion == id)return ar9300_eep_templates[it];return NULL;static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)return 0 ;static int interpolate(int x, int xa, int xb, int ya, int yb)int bf, factor, plus;2 * (yb - ya) * (x - xa) / (xb - xa);2 ;2 ;return ya + factor + plus;static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,enum eeprom_param param)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;switch (param) {case EEP_MAC_LSW:return get_unaligned_be16(eep->macAddr);case EEP_MAC_MID:return get_unaligned_be16(eep->macAddr + 2 );case EEP_MAC_MSW:return get_unaligned_be16(eep->macAddr + 4 );case EEP_REG_0:return le16_to_cpu(pBase->regDmn[0 ]);case EEP_OP_CAP:return pBase->deviceCap;case EEP_OP_MODE:return pBase->opCapFlags.opFlags;case EEP_RF_SILENT:return pBase->rfSilent;case EEP_TX_MASK:return (pBase->txrxMask >> 4 ) & 0 xf;case EEP_RX_MASK:return pBase->txrxMask & 0 xf;case EEP_PAPRD:return !!(pBase->featureEnable & BIT(5 ));case EEP_CHAIN_MASK_REDUCE:return (pBase->miscConfiguration >> 0 x3) & 0 x1;case EEP_ANT_DIV_CTL1:if (AR_SREV_9565(ah))return AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE;else return eep->base_ext1.ant_div_control;case EEP_ANTENNA_GAIN_5G:return eep->modalHeader5G.antennaGain;case EEP_ANTENNA_GAIN_2G:return eep->modalHeader2G.antennaGain;default :return 0 ;static bool ar9300_eeprom_read_byte(struct ath_hw *ah, int address,if (unlikely(!ath9k_hw_nvram_read(ah, address / 2 , &val)))return false ;8 * (address % 2 ))) & 0 xff;return true ;static bool ar9300_eeprom_read_word(struct ath_hw *ah, int address,if (unlikely(!ath9k_hw_nvram_read(ah, address / 2 , &val)))return false ;0 ] = val >> 8 ;1 ] = val & 0 xff;return true ;static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,int count)struct ath_common *common = ath9k_hw_common(ah);int i;if ((address < 0 ) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1 )) {"eeprom address not in range\n" );return false ;/* * Since we're reading the bytes in reverse order from a little-endian * word stream, an even address means we only use the lower half of * the 16-bit word at that address if (address % 2 == 0 ) {if (!ar9300_eeprom_read_byte(ah, address--, buffer++))goto error;for (i = 0 ; i < count / 2 ; i++) {if (!ar9300_eeprom_read_word(ah, address, buffer))goto error;2 ;2 ;if (count % 2 )if (!ar9300_eeprom_read_byte(ah, address, buffer))goto error;return true ;"unable to read eeprom region at offset %d\n" ,return false ;static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)4 * addr));if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS(ah), AR9300_OTP_STATUS_TYPE,1000 ))return false ;return true ;static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,int count)int i;for (i = 0 ; i < count; i++) {int offset = 8 * ((address - i) % 4 );if (!ar9300_otp_read_word(ah, (address - i) / 4 , &data))return false ;0 xff;return true ;static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,int *length, int *major, int *minor)unsigned long value[4 ];0 ] = best[0 ];1 ] = best[1 ];2 ] = best[2 ];3 ] = best[3 ];0 ] >> 5 ) & 0 x0007);0 ] & 0 x001f) | ((value[1 ] >> 2 ) & 0 x0020);1 ] << 4 ) & 0 x07f0) | ((value[2 ] >> 4 ) & 0 x000f);2 ] & 0 x000f);3 ] & 0 x00ff);static u16 ar9300_comp_cksum(u8 *data, int dsize)int it, checksum = 0 ;for (it = 0 ; it < dsize; it++) {0 xffff;return checksum;static bool ar9300_uncompress_block(struct ath_hw *ah,int mdataSize,int size)int it;int spot;int offset;int length;struct ath_common *common = ath9k_hw_common(ah);0 ;for (it = 0 ; it < size; it += (length+2 )) {0 xff;1 ];0 xff;if (length > 0 && spot >= 0 && spot+length <= mdataSize) {"Restore at %d: spot=%d offset=%d length=%d\n" ,2 ], length);else if (length > 0 ) {"Bad restore at %d: spot=%d offset=%d length=%d\n" ,return false ;return true ;static int ar9300_compress_decision(struct ath_hw *ah,int it,int code,int reference,int length, int mdata_size)struct ath_common *common = ath9k_hw_common(ah);const struct ar9300_eeprom *eep = NULL;switch (code) {case _CompressNone:if (length != mdata_size) {"EEPROM structure size mismatch memory=%d eeprom=%d\n" ,return -1 ;"restored eeprom %d: uncompressed, length %d\n" ,break ;case _CompressBlock:if (reference != 0 ) {if (eep == NULL) {"can't find reference eeprom struct %d\n" ,return -1 ;"restore eeprom %d: block, reference %d, length %d\n" ,break ;default :"unknown compression code %d\n" , code);return -1 ;return 0 ;typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,int count);static bool ar9300_check_header(void *data)return !(*word == 0 || *word == ~0 );static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,int base_addr)4 ];if (!read(ah, base_addr, header, 4 ))return false ;return ar9300_check_header(header);static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,int mdata_size)int i;for (i = 0 ; i < mdata_size / 2 ; i++, data++)if (!ath9k_hw_nvram_read(ah, i, data))return -EIO;return 0 ;/* * Read the configuration data from the eeprom. * The data can be put in any specified memory buffer. * * Returns -1 on error. * Returns address of next memory location on success. static int ar9300_eeprom_restore_internal(struct ath_hw *ah,int mdata_size)#define MDEFAULT 15 #define MSTATE 100 int cptr;int code;int reference, length, major, minor;int osize;int it;struct ath_common *common = ath9k_hw_common(ah);struct ar9300_eeprom *eep;if (ath9k_hw_use_flash(ah)) {if (ar9300_eeprom_restore_flash(ah, mptr, mdata_size))return -EIO;/* check if eeprom contains valid data */ struct ar9300_eeprom *) mptr;if (txrx != 0 && txrx != 0 xff)return 0 ;2048 , GFP_KERNEL);if (!word)return -ENOMEM;if (AR_SREV_9485(ah))else if (AR_SREV_9330(ah))else "Trying EEPROM access at Address 0x%04x\n" ,if (ar9300_check_eeprom_header(ah, read, cptr))goto found;"Trying EEPROM access at Address 0x%04x\n" ,if (ar9300_check_eeprom_header(ah, read, cptr))goto found;"Trying EEPROM access at Address 0x%04x\n" ,if (ar9300_check_eeprom_header(ah, read, cptr))goto found;"Trying OTP access at Address 0x%04x\n" , cptr);if (ar9300_check_eeprom_header(ah, read, cptr))goto found;"Trying OTP access at Address 0x%04x\n" , cptr);if (ar9300_check_eeprom_header(ah, read, cptr))goto found;goto fail;"Found valid EEPROM data\n" );for (it = 0 ; it < MSTATE; it++) {if (!read(ah, cptr, word, COMP_HDR_LEN))goto fail;if (!ar9300_check_header(word))break ;"Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n" ,if ((!AR_SREV_9485(ah) && length >= 1024 ) ||"Skipping bad header\n" );continue ;"checksum %x %x\n" ,if (checksum == mchecksum) {else {"skipping block with bad checksum\n" );return cptr;return -1 ;/* * Restore the configuration structure by reading the eeprom. * This function destroys any existing in-memory structure * content. static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)if (ar9300_eeprom_restore_internal(ah, mptr,sizeof (struct ar9300_eeprom)) < 0 )return false ;return true ;#if defined (CONFIG_ATH9K_DEBUGFS) || defined (CONFIG_ATH9K_HTC_DEBUGFS)static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,struct ar9300_modal_eep_header *modal_hdr)"Chain0 Ant. Control" , le16_to_cpu(modal_hdr->antCtrlChain[0 ]));"Chain1 Ant. Control" , le16_to_cpu(modal_hdr->antCtrlChain[1 ]));"Chain2 Ant. Control" , le16_to_cpu(modal_hdr->antCtrlChain[2 ]));"Ant. Common Control" , le32_to_cpu(modal_hdr->antCtrlCommon));"Ant. Common Control2" , le32_to_cpu(modal_hdr->antCtrlCommon2));"Ant. Gain" , modal_hdr->antennaGain);"Switch Settle" , modal_hdr->switchSettling);"Chain0 xatten1DB" , modal_hdr->xatten1DB[0 ]);"Chain1 xatten1DB" , modal_hdr->xatten1DB[1 ]);"Chain2 xatten1DB" , modal_hdr->xatten1DB[2 ]);"Chain0 xatten1Margin" , modal_hdr->xatten1Margin[0 ]);"Chain1 xatten1Margin" , modal_hdr->xatten1Margin[1 ]);"Chain2 xatten1Margin" , modal_hdr->xatten1Margin[2 ]);"Temp Slope" , modal_hdr->tempSlope);"Volt Slope" , modal_hdr->voltSlope);"spur Channels0" , modal_hdr->spurChans[0 ]);"spur Channels1" , modal_hdr->spurChans[1 ]);"spur Channels2" , modal_hdr->spurChans[2 ]);"spur Channels3" , modal_hdr->spurChans[3 ]);"spur Channels4" , modal_hdr->spurChans[4 ]);"Chain0 NF Threshold" , modal_hdr->noiseFloorThreshCh[0 ]);"Chain1 NF Threshold" , modal_hdr->noiseFloorThreshCh[1 ]);"Chain2 NF Threshold" , modal_hdr->noiseFloorThreshCh[2 ]);"Quick Drop" , modal_hdr->quick_drop);"txEndToXpaOff" , modal_hdr->txEndToXpaOff);"xPA Bias Level" , modal_hdr->xpaBiasLvl);"txFrameToDataStart" , modal_hdr->txFrameToDataStart);"txFrameToPaOn" , modal_hdr->txFrameToPaOn);"txFrameToXpaOn" , modal_hdr->txFrameToXpaOn);"txClip" , modal_hdr->txClip);"ADC Desired size" , modal_hdr->adcDesiredSize);return len;static u32 ar9003_dump_cal_data(struct ath_hw *ah, char *buf, u32 len, u32 size,bool is_2g)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;struct ar9300_base_eep_hdr *pBase;struct ar9300_cal_data_per_freq_op_loop *cal_pier;int cal_pier_nr;int freq;int i, j;if (is_2g)else for (i = 0 ; i < AR9300_MAX_CHAINS; i++) {if (!((pBase->txrxMask >> i) & 1 ))continue ;"Chain %d\n" , i);"Freq\t ref\tvolt\ttemp\tnf_cal\tnf_pow\trx_temp\n" );for (j = 0 ; j < cal_pier_nr; j++) {if (is_2g) {2300 + eep->calFreqPier2G[j];else {4800 + eep->calFreqPier5G[j] * 5 ;"%d\t" , freq);"%d\t%d\t%d\t%d\t%d\t%d\n" ,0 ,0 ,return len;static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;struct ar9300_base_eep_hdr *pBase;if (!dump_base_hdr) {"%20s :\n" , "2GHz modal Header" );"Calibration data\n" );true );"%20s :\n" , "5GHz modal Header" );"Calibration data\n" );false );goto out;"EEPROM Version" , ah->eeprom.ar9300_eep.eepromVersion);"RegDomain1" , le16_to_cpu(pBase->regDmn[0 ]));"RegDomain2" , le16_to_cpu(pBase->regDmn[1 ]));"TX Mask" , (pBase->txrxMask >> 4 ));"RX Mask" , (pBase->txrxMask & 0 x0f));"Allow 5GHz" , !!(pBase->opCapFlags.opFlags &"Allow 2GHz" , !!(pBase->opCapFlags.opFlags &"Disable 2GHz HT20" , !!(pBase->opCapFlags.opFlags &"Disable 2GHz HT40" , !!(pBase->opCapFlags.opFlags &"Disable 5Ghz HT20" , !!(pBase->opCapFlags.opFlags &"Disable 5Ghz HT40" , !!(pBase->opCapFlags.opFlags &"Big Endian" , !!(pBase->opCapFlags.eepMisc &"RF Silent" , pBase->rfSilent);"BT option" , pBase->blueToothOptions);"Device Cap" , pBase->deviceCap);"Device Type" , pBase->deviceType);"Power Table Offset" , pBase->pwrTableOffset);"Tuning Caps1" , pBase->params_for_tuning_caps[0 ]);"Tuning Caps2" , pBase->params_for_tuning_caps[1 ]);"Enable Tx Temp Comp" , !!(pBase->featureEnable & BIT(0 )));"Enable Tx Volt Comp" , !!(pBase->featureEnable & BIT(1 )));"Enable fast clock" , !!(pBase->featureEnable & BIT(2 )));"Enable doubling" , !!(pBase->featureEnable & BIT(3 )));"Internal regulator" , !!(pBase->featureEnable & BIT(4 )));"Enable Paprd" , !!(pBase->featureEnable & BIT(5 )));"Driver Strength" , !!(pBase->miscConfiguration & BIT(0 )));"Quick Drop" , !!(pBase->miscConfiguration & BIT(1 )));"Chain mask Reduce" , (pBase->miscConfiguration >> 0 x3) & 0 x1);"Write enable Gpio" , pBase->eepromWriteEnableGpio);"WLAN Disable Gpio" , pBase->wlanDisableGpio);"WLAN LED Gpio" , pBase->wlanLedGpio);"Rx Band Select Gpio" , pBase->rxBandSelectGpio);"Tx Gain" , pBase->txrxgain >> 4 );"Rx Gain" , pBase->txrxgain & 0 xf);"SW Reg" , le32_to_cpu(pBase->swreg));"%20s : %pM\n" , "MacAddress" ,if (len > size)return len;#else static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,return 0 ;#endif /* XXX: review hardware docs */ static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)return ah->eeprom.ar9300_eep.eepromVersion;/* XXX: could be read from the eepromVersion, not sure yet */ static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)return 0 ;static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,bool is2ghz)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;if (is2ghz)return &eep->modalHeader2G;else return &eep->modalHeader5G;static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah) ||else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah))else {2 );1 );static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);struct ath_hw *ah, bool is2ghz)return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);struct ath_hw *ah, bool is2ghz)return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,bool is2ghz)return le16_to_cpu(val);static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)struct ath_common *common = ath9k_hw_common(ah);struct ath9k_hw_capabilities *pCap = &ah->caps;int chain;static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {if (AR_SREV_9485(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0 )) {if (ah->config.xlna_gpio)else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {else /* * AR9462 defines new switch table for BT/WLAN, * here's new field name in XXX.ref for both 2G and 5G. * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044) * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX * SWITCH_TABLE_COM_SPDT_WLAN_RX * * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX * SWITCH_TABLE_COM_SPDT_WLAN_TX * * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE * SWITCH_TABLE_COM_SPDT_WLAN_IDLE if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) {if (AR_SREV_9485(ah) && common->bt_ant_diversity) {if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0 x2)) {1 , is2ghz);0 ],for (chain = 0 ; chain < AR9300_MAX_CHAINS; chain++) {if ((ah->rxchainmask & BIT(chain)) ||if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {/* * main_lnaconf, alt_lnaconf, main_tb, alt_tb * are the fields present 0 x3f) << AR_ANT_DIV_CTRL_ALL_S;/* enable_lnadiv */ 6 ) & 0 x1) << AR_PHY_ANT_DIV_LNADIV_S;if (AR_SREV_9485(ah) && common->bt_ant_diversity)if (AR_SREV_9565(ah)) {if (common->bt_ant_diversity) {1 << AR_PHY_ANT_SW_RX_PROT_S);/* Force WLAN LNA diversity ON */ else {1 << AR_PHY_ANT_DIV_LNADIV_S);1 << AR_PHY_ANT_SW_RX_PROT_S);1 << AR_PHY_ANT_SW_RX_PROT_S));/* Force WLAN LNA diversity OFF */ /* enable fast_div */ 7 ) & 0 x1) << AR_FAST_DIV_ENABLE_S;if ((AR_SREV_9485(ah) || AR_SREV_9565(ah))if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {/* * clear bits 25-30 main_lnaconf, alt_lnaconf, * main_tb, alt_tb /* by default use LNA1 for the main antenna */ static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;int drive_strength;unsigned long reg;0 );if (!drive_strength)return ;0 x00ffffc0;0 x5 << 21 ;0 x5 << 18 ;0 x5 << 15 ;0 x5 << 12 ;0 x5 << 9 ;0 x5 << 6 ;0 xffffffe0;0 x5 << 29 ;0 x5 << 26 ;0 x5 << 23 ;0 x5 << 20 ;0 x5 << 17 ;0 x5 << 14 ;0 x5 << 11 ;0 x5 << 8 ;0 x5 << 5 ;0 xff800000;0 x5 << 29 ;0 x5 << 26 ;0 x5 << 23 ;static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,struct ath9k_channel *chan)int f[3 ], t[3 ];struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;if (chain >= 0 && chain < 3 ) {if (IS_CHAN_2GHZ(chan))return eep->modalHeader2G.xatten1DB[chain];else if (eep->base_ext2.xatten1DBLow[chain] != 0 ) {0 ] = eep->base_ext2.xatten1DBLow[chain];0 ] = 5180 ;1 ] = eep->modalHeader5G.xatten1DB[chain];1 ] = 5500 ;2 ] = eep->base_ext2.xatten1DBHigh[chain];2 ] = 5785 ;3 );return value;else return eep->modalHeader5G.xatten1DB[chain];return 0 ;static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,struct ath9k_channel *chan)int f[3 ], t[3 ];struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;if (chain >= 0 && chain < 3 ) {if (IS_CHAN_2GHZ(chan))return eep->modalHeader2G.xatten1Margin[chain];else if (eep->base_ext2.xatten1MarginLow[chain] != 0 ) {0 ] = eep->base_ext2.xatten1MarginLow[chain];0 ] = 5180 ;1 ] = eep->modalHeader5G.xatten1Margin[chain];1 ] = 5500 ;2 ] = eep->base_ext2.xatten1MarginHigh[chain];2 ] = 5785 ;3 );return value;else return eep->modalHeader5G.xatten1Margin[chain];return 0 ;static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)int i;unsigned long ext_atten_reg[3 ] = {AR_PHY_EXT_ATTEN_CTL_0,if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0 x2)) {1 , chan);0 ],1 , chan);0 ],/* Test value. if 0 then attenuation is unused. Don't load anything. */ for (i = 0 ; i < AR9300_MAX_CHAINS; i++) {if (ah->txchainmask & BIT(i)) {if (AR_SREV_9485(ah) &&0 ) &&5 ;else if (ah->config.alt_mingainidx)static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)int timeout = 100 ;while (pmu_set != REG_READ(ah, pmu_reg)) {if (timeout-- == 0 )return false ;10 );return true ;void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;if (pBase->featureEnable & BIT(4 )) {if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {int reg_pmu_set;if (!is_pmu_set(ah, AR_PHY_PMU2(ah), reg_pmu_set))return ;if (AR_SREV_9330(ah)) {if (ah->is_clk_25mhz) {3 << 1 ) | (8 << 4 ) |3 << 8 ) | (1 << 14 ) |6 << 17 ) | (1 << 20 ) |3 << 24 );else {4 << 1 ) | (7 << 4 ) |3 << 8 ) | (1 << 14 ) |6 << 17 ) | (1 << 20 ) |3 << 24 );else {5 << 1 ) | (7 << 4 ) |2 << 8 ) | (2 << 14 ) |6 << 17 ) | (1 << 20 ) |3 << 24 ) | (1 << 28 );if (!is_pmu_set(ah, AR_PHY_PMU1(ah), reg_pmu_set))return ;0 xFFC00000)4 << 26 );if (!is_pmu_set(ah, AR_PHY_PMU2(ah), reg_pmu_set))return ;0 x00200000)1 << 21 );if (!is_pmu_set(ah, AR_PHY_PMU2(ah), reg_pmu_set))return ;else if (AR_SREV_9462(ah) || AR_SREV_9565(ah) ||if (AR_SREV_9561(ah))0 x10200000);else {/* Internal regulator is ON. Write swreg register. */ /* Set REG_CONTROL1.SWREG_PROGRAM */ else {if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {0 );while (REG_READ_FIELD(ah, AR_PHY_PMU2(ah),10 );0 x1);while (!REG_READ_FIELD(ah, AR_PHY_PMU1(ah),10 );0 x1);while (!REG_READ_FIELD(ah, AR_PHY_PMU2(ah),10 );else if (AR_SREV_9462(ah) || AR_SREV_9565(ah))0 x1);else {static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;0 ];if (AR_SREV_9340(ah) || AR_SREV_9531(ah))return ;if (eep->baseEepHeader.featureEnable & 0 x40) {0 x7f;static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;int quick_drop;3 ], f[3 ] = {5180 , 5500 , 5785 };if (!(pBase->miscConfiguration & BIT(4 )))return ;if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9340(ah)) {if (freq < 4000 ) {else {0 ] = eep->base_ext1.quick_drop_low;1 ] = eep->modalHeader5G.quick_drop;2 ] = eep->base_ext1.quick_drop_high;3 );static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;if (!(eep->baseEepHeader.featureEnable & 0 x80))return ;if (!AR_SREV_9300(ah) &&return ;if (is2ghz)else static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;if (!(eep->baseEepHeader.miscConfiguration & 0 x40))return ;if (!AR_SREV_9300(ah))return ;0 x3);2 ;0 x3);2 ;0 x3);static int ar9003_hw_get_thermometer(struct ath_hw *ah)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;int thermometer = (pBase->miscConfiguration >> 1 ) & 0 x3;return --thermometer;static void ar9003_hw_thermometer_apply(struct ath_hw *ah)struct ath9k_hw_capabilities *pCap = &ah->caps;int thermometer = ar9003_hw_get_thermometer(ah);0 ) ? 0 : 1 ;if (pCap->chip_chainmask & BIT(1 ))if (pCap->chip_chainmask & BIT(2 ))0 ;if (pCap->chip_chainmask & BIT(1 )) {1 ;if (pCap->chip_chainmask & BIT(2 )) {2 ;static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah)0 , ko, kg;if (!AR_SREV_9462_20_OR_LATER(ah))return ;1 , &data);0 xff;8 ) & 0 xff;if (ko || kg) {256 );static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah,bool is2ghz)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;const u_int32_t cca_ctrl[AR9300_MAX_CHAINS] = {int chain;if (is2ghz) {if (!(eep->base_ext1.misc_enable & BIT(2 )))return ;else {if (!(eep->base_ext1.misc_enable & BIT(3 )))return ;for (chain = 0 ; chain < AR9300_MAX_CHAINS; chain++) {if (!(ah->caps.tx_chainmask & BIT(chain)))continue ;static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,struct ath9k_channel *chan)bool is2ghz = IS_CHAN_2GHZ(chan);if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9531(ah))static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,struct ath9k_channel *chan)/* * Returns the interpolated y value corresponding to the specified x value * from the np ordered pairs of data (px,py). * The pairs do not have to be in any order. * If the specified x value is less than any of the px, * the returned y value is equal to the py for the lowest px. * If the specified x value is greater than any of the px, * the returned y value is equal to the py for the highest px. static int ar9003_hw_power_interpolate(int32_t x,int ip = 0 ;int lx = 0 , ly = 0 , lhave = 0 ;int hx = 0 , hy = 0 , hhave = 0 ;int dx = 0 ;int y = 0 ;0 ;0 ;/* identify best lower and higher x calibration measurement */ for (ip = 0 ; ip < np; ip++) {/* this measurement is higher than our desired x */ if (dx <= 0 ) {if (!hhave || dx > (x - hx)) {/* new best higher x measurement */ 1 ;/* this measurement is lower than our desired x */ if (dx >= 0 ) {if (!lhave || dx < (x - lx)) {/* new best lower x measurement */ 1 ;/* the low x is good */ if (lhave) {/* so is the high x */ if (hhave) {/* they're the same, so just pick one */ if (hx == lx)else /* interpolate */ else /* only low is good, use it */ else if (hhave) /* only high is good, use it */ else /* nothing is good,this should never happen unless np=0, ???? */ 1 << 30 );return y;static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,bool is2GHz)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;struct cal_tgt_pow_legacy *pEepromTargetPwr;if (is2GHz) {else {/* * create array of channels and targetpower from * targetpower piers stored on eeprom for (i = 0 ; i < numPiers; i++) {/* interpolate to get target power for given frequency */ return (u8) ar9003_hw_power_interpolate((s32) freq,static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,bool is2GHz)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;struct cal_tgt_pow_ht *pEepromTargetPwr;if (is2GHz) {else {/* * create array of channels and targetpower * from targetpower piers stored on eeprom for (i = 0 ; i < numPiers; i++) {/* interpolate to get target power for given frequency */ return (u8) ar9003_hw_power_interpolate((s32) freq,static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,bool is2GHz)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;struct cal_tgt_pow_ht *pEepromTargetPwr;if (is2GHz) {else {/* * create array of channels and targetpower from * targetpower piers stored on eeprom for (i = 0 ; i < numPiers; i++) {/* interpolate to get target power for given frequency */ return (u8) ar9003_hw_power_interpolate((s32) freq,static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;/* * create array of channels and targetpower from * targetpower piers stored on eeprom for (i = 0 ; i < numPiers; i++) {1 );/* interpolate to get target power for given frequency */ return (u8) ar9003_hw_power_interpolate((s32) freq,static void ar9003_hw_selfgen_tpc_txpower(struct ath_hw *ah,struct ath9k_channel *chan,/* target power values for self generated frames (ACK,RTS/CTS) */ if (IS_CHAN_2GHZ(chan)) {0 x3f, AR_TPC_CHIRP) | SM(0 x3f, AR_TPC_RPT);else {0 x3f, AR_TPC_CHIRP) | SM(0 x3f, AR_TPC_RPT);/* Set tx power registers to array of values passed in */ int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)#define POW_SM(_r, _s) (((_r) & 0 x3f) << (_s))/* make sure forced gain is not set */ 0 );/* Write the OFDM power per rate set */ /* 6 (LSB), 9, 12, 18 (MSB) */ 0 ),24 ) |16 ) |8 ) |0 ));/* 24 (LSB), 36, 48, 54 (MSB) */ 1 ),24 ) |16 ) |8 ) |0 ));/* Write the CCK power per rate set */ /* 1L (LSB), reserved, 2L, 2S (MSB) */ 2 ),24 ) |16 ) |/* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */ 0 ));/* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 3 ),24 ) |16 ) |8 ) |0 )/* Write the power for duplicated frames - HT40 */ /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */ 8 ),24 ) |16 ) |8 ) |0 )/* Write the HT20 power per rate set */ /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 4 ),24 ) |16 ) |8 ) |0 )/* 6 (LSB), 7, 12, 13 (MSB) */ 5 ),24 ) |16 ) |8 ) |0 )/* 14 (LSB), 15, 20, 21 */ 9 ),24 ) |16 ) |8 ) |0 )/* Mixed HT20 and HT40 rates */ /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 10 ),24 ) |16 ) |8 ) |0 )/* * Write the HT40 power per rate set * correct PAR difference between HT40 and HT20/LEGACY * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) 6 ),24 ) |16 ) |8 ) |0 )/* 6 (LSB), 7, 12, 13 (MSB) */ 7 ),24 ) |16 ) |8 ) |0 )/* 14 (LSB), 15, 20, 21 */ 11 ),24 ) |16 ) |8 ) |0 )return 0 ;#undef POW_SMstatic void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,bool is2GHz)static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,bool is2GHz)static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,bool is2GHz)/* XXX: hard code for now, need to get from eeprom struct */ 0 ;static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,struct ath9k_channel *chan,bool is2GHz = IS_CHAN_2GHZ(chan);unsigned int i = 0 ;struct ath_common *common = ath9k_hw_common(ah);if (is2GHz)if (IS_CHAN_HT40(chan))for (i = 0 ; i < ar9300RateSize; i++) {"TPC[%02d] 0x%08x\n" ,static int ar9003_hw_cal_pier_get(struct ath_hw *ah,bool is2ghz,int ipier,int ichain,int *pfrequency,int *pcorrection,int *ptemperature, int *pvoltage,int *pnf_cal, int *pnf_power)struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;struct ath_common *common = ath9k_hw_common(ah);if (ichain >= AR9300_MAX_CHAINS) {"Invalid chain index, must be less than %d\n" ,return -1 ;if (is2ghz) {if (ipier >= AR9300_NUM_2G_CAL_PIERS) {"Invalid 2GHz cal pier index, must be less than %d\n" ,return -1 ;else {if (ipier >= AR9300_NUM_5G_CAL_PIERS) {"Invalid 5GHz cal pier index, must be less than %d\n" ,return -1 ;0 ;0 ;return 0 ;static void ar9003_hw_power_control_override(struct ath_hw *ah,int frequency,int *correction,int *voltage, int *temperature)int temp_slope = 0 , temp_slope1 = 0 , temp_slope2 = 0 ;struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;int f[8 ], t[8 ], t1[3 ], t2[3 ], i;0 ] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),if (ah->caps.tx_chainmask & BIT(1 ))1 ] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),if (ah->caps.tx_chainmask & BIT(2 ))2 ] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),/* enable open loop power control on chip */ 3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),if (ah->caps.tx_chainmask & BIT(1 ))3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),if (ah->caps.tx_chainmask & BIT(2 ))3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),/* * enable temperature compensation * Need to use register names if (frequency < 4000 ) {else {if (AR_SREV_9550(ah)) {0 ] = eep->base_ext1.tempslopextension[2 ];0 ] = eep->base_ext1.tempslopextension[3 ];0 ] = eep->base_ext1.tempslopextension[4 ];0 ] = 5180 ;1 ] = eep->modalHeader5G.tempSlope;1 ] = eep->base_ext1.tempslopextension[0 ];1 ] = eep->base_ext1.tempslopextension[1 ];1 ] = 5500 ;2 ] = eep->base_ext1.tempslopextension[5 ];2 ] = eep->base_ext1.tempslopextension[6 ];2 ] = eep->base_ext1.tempslopextension[7 ];2 ] = 5785 ;3 );3 );3 );goto tempslope;if ((eep->baseEepHeader.miscConfiguration & 0 x20) != 0 ) {for (i = 0 ; i < 8 ; i++) {0 );8 );else if (eep->base_ext2.tempSlopeLow != 0 ) {0 ] = eep->base_ext2.tempSlopeLow;0 ] = 5180 ;1 ] = eep->modalHeader5G.tempSlope;1 ] = 5500 ;2 ] = eep->base_ext2.tempSlopeHigh;2 ] = 5785 ;3 );else {if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {0 xf0) >> 4 ;/* * AR955x has tempSlope register for each chain. * Check whether temp_compensation feature is enabled or not. if (eep->baseEepHeader.featureEnable & 0 x1) {if (frequency < 4000 ) {if (txmask & BIT(0 ))if (txmask & BIT(1 ))if (txmask & BIT(2 ))else {if (txmask & BIT(0 ))if (txmask & BIT(1 ))if (txmask & BIT(2 ))else {/* * If temp compensation is not enabled, * set all registers to 0. if (txmask & BIT(0 ))0 );if (txmask & BIT(1 ))0 );if (txmask & BIT(2 ))0 );else {if (AR_SREV_9462_20_OR_LATER(ah))0 ]);/* Apply the recorded correction values. */ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)int ichain, ipier, npier;int lfrequency[AR9300_MAX_CHAINS],int hfrequency[AR9300_MAX_CHAINS],int fdiff;int correction[AR9300_MAX_CHAINS],int pfrequency, pcorrection, ptemperature, pvoltage,struct ath_common *common = ath9k_hw_common(ah);bool is2ghz = frequency < 4000 ;if (is2ghz)else for (ichain = 0 ; ichain < AR9300_MAX_CHAINS; ichain++) {0 ;100000 ;/* identify best lower and higher frequency calibration measurement */ for (ichain = 0 ; ichain < AR9300_MAX_CHAINS; ichain++) {for (ipier = 0 ; ipier < npier; ipier++) {if (!ar9003_hw_cal_pier_get(ah, is2ghz, ipier, ichain,/* * this measurement is higher than * our desired frequency if (fdiff <= 0 ) {if (hfrequency[ichain] <= 0 ||100000 ||/* * new best higher * frequency measurement if (fdiff >= 0 ) {if (lfrequency[ichain] <= 0 /* * new best lower * frequency measurement /* interpolate */ for (ichain = 0 ; ichain < AR9300_MAX_CHAINS; ichain++) {"ch=%d f=%d low=%d %d h=%d %d n=%d %d p=%d %d\n" ,/* they're the same, so just pick one */ if (hfrequency[ichain] == lfrequency[ichain]) {/* the low frequency is good */ else if (frequency - lfrequency[ichain] < 1000 ) {/* so is the high frequency, interpolate */ if (hfrequency[ichain] - frequency < 1000 ) {/* only low is good, use it */ else {/* only high is good, use it */ else if (hfrequency[ichain] - frequency < 1000 ) {else { /* nothing is good, presume 0???? */ 0 ;0 ;0 ;0 ;0 ;"for frequency=%d, calibration correction = %d %d %d\n" ,0 ], correction[1 ], correction[2 ]);/* Store calibrated noise floor values */ for (ichain = 0 ; ichain < AR9300_MAX_CHAINS; ichain++)if (is2ghz) {else {return 0 ;static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,int idx,int edge,bool is2GHz)struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;if (is2GHz)return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);else return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,int idx,unsigned int edge,bool is2GHz)struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;0 ] :0 ];if (is2GHz) {if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1 ], 1 ) < freq &&1 ]))return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1 ]);else {if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1 ], 0 ) < freq &&1 ]))return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1 ]);return MAX_RATE_POWER;/* * Find the maximum conformance test limit for the given channel and CTL info static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,int idx, bool is2GHz)0 ] :0 ];unsigned int edge;/* Get the edge power */ for (edge = 0 ;/* * If there's an exact channel match or an inband flag set * on the lower channel use the given rdEdgePower if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {break ;else if ((edge > 0 ) &&/* * Leave loop - no more affecting edges possible in * this monotonic increasing list break ;if (is2GHz && !twiceMaxEdgePower)60 ;return twiceMaxEdgePower;static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,struct ath9k_channel *chan,struct ath_common *common = ath9k_hw_common(ah);struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;int i;0 , minCtlPower;static const u16 ctlModesFor11a[] = {static const u16 ctlModesFor11g[] = {const u16 *pCtlMode;struct chan_centers centers;bool is2ghz = IS_CHAN_2GHZ(chan);if (is2ghz) {/* Setup for CTL modes */ /* CTL_11B, CTL_11G, CTL_2GHT20 */ if (IS_CHAN_HT40(chan))/* All 2G CTL's */ else {/* Setup for CTL modes */ /* CTL_11A, CTL_5GHT20 */ if (IS_CHAN_HT40(chan))/* All 5G CTL's */ /* * For MIMO, need to apply regulatory caps individually across * dynamically running modes: CCK, OFDM, HT20, HT40 * * The outer loop walks through each possible applicable runtime mode. * The inner loop walks through each ctlIndex entry in EEPROM. * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. for (ctlMode = 0 ; ctlMode < numCtlModes; ctlMode++) {bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||if (isHt40CtlMode)else if (pCtlMode[ctlMode] & EXT_ADDITIVE)else "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n" ,/* walk through each CTL index stored in EEPROM */ if (is2ghz) {else {for (i = 0 ; (i < ctlNum) && ctlIndex[i]; i++) {"LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n" ,/* * compare test group from regulatory * channel list with test mode from pCtlMode * list if ((((cfgCtl & ~CTL_MODE_M) |if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)/* * Find the minimum of all CTL * edge powers that apply to * this channel else {/* specific */ break ;"SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n" ,/* Apply ctl mode to correct target power set */ switch (pCtlMode[ctlMode]) {case CTL_11B:for (i = ALL_TARGET_LEGACY_1L_5L;break ;case CTL_11A:case CTL_11G:for (i = ALL_TARGET_LEGACY_6_24;break ;case CTL_5GHT20:case CTL_2GHT20:for (i = ALL_TARGET_HT20_0_8_16;if (ath9k_hw_mci_is_enabled(ah))break ;case CTL_5GHT40:case CTL_2GHT40:for (i = ALL_TARGET_HT40_0_8_16;if (ath9k_hw_mci_is_enabled(ah))break ;default :break ;/* end ctl mode checking */ static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)8 ;if (mod_idx <= 3 )return mod_idx ? (base_pwridx + 1 ) : base_pwridx;else return base_pwridx + 4 * (mcs_idx / 8 ) + mod_idx - 2 ;static void ar9003_paprd_set_txpower(struct ath_hw *ah,struct ath9k_channel *chan,int i;if (!ar9003_is_paprd_enabled(ah))return ;if (IS_CHAN_HT40(chan))else if (IS_CHAN_2GHZ(chan)) {if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) &&if (IS_CHAN_HT40(chan))else static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,struct ath9k_channel *chan, u16 cfgCtl,bool test)struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);struct ath_common *common = ath9k_hw_common(ah);unsigned int i = 0 , paprd_scale_factor = 0 ;0 ;0 , sizeof (targetPowerValT2));/* * Get target powers from EEPROM - our baseline for TX Power if (ar9003_is_paprd_enabled(ah)) {if (!ah->paprd_table_write_done) {sizeof (targetPowerValT2));for (i = 0 ; i < 24 ; i++) {if (ah->paprd_ratemask & (1 << i)) {if (targetPowerValT2[pwr_idx] &&sizeof (targetPowerValT2));sizeof (targetPowerValT2));if (ar9003_is_paprd_enabled(ah)) {for (i = 0 ; i < ar9300RateSize; i++) {if ((ah->paprd_ratemask & (1 << i)) &&1 << i);"paprd disabled for mcs %d\n" , i);0 ;for (i = 0 ; i < ar9300RateSize; i++) {if (targetPowerValT2[i] > regulatory->max_power_level)if (test)return ;for (i = 0 ; i < ar9300RateSize; i++) {"TPC[%02d] 0x%08x\n" ,/* Write target power array to registers */ /* TPC initializations */ if (ah->tpc_enabled) {/* Enable TPC */ /* Disable per chain power reduction */ if (AR_SREV_9340(ah))0 xFFFFFFC0);else 0 xFFFFF000);else {/* Disable TPC */ 0 );static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,bool is2GHz)return AR_NO_SPUR;struct ath_hw *ah)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;return (eep->baseEepHeader.txrxgain >> 4 ) & 0 xf; /* bits 7:4 */ struct ath_hw *ah)struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;return (eep->baseEepHeader.txrxgain) & 0 xf; /* bits 3:0 */ struct ath_hw *ah, bool is2ghz)return ar9003_modal_header(ah, is2ghz)->spurChans;struct ath_hw *ah, bool is2ghz)return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->papdRateMaskHt20);struct ath_hw *ah, bool is2ghz)return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->papdRateMaskHt40);unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,struct ath9k_channel *chan)bool is2ghz = IS_CHAN_2GHZ(chan);if (is2ghz)return MS(ar9003_get_paprd_rate_mask_ht20(ah, is2ghz),else {if (chan->channel >= 5700 )return MS(ar9003_get_paprd_rate_mask_ht20(ah, is2ghz),else if (chan->channel >= 5400 )return MS(ar9003_get_paprd_rate_mask_ht40(ah, is2ghz),else return MS(ar9003_get_paprd_rate_mask_ht40(ah, is2ghz),static u8 ar9003_get_eepmisc(struct ath_hw *ah)return ah->eeprom.ar9300_eep.baseEepHeader.opCapFlags.eepMisc;const struct eeprom_ops eep_ar9300_ops = {
Messung V0.5 in Prozent C=95 H=91 G=92
[0.170QuellennavigatorsProjekt 2026-06-07]
2026-08-25
