# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id:
http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
$schema:
http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments GPMC NAND Flash controller.
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
GPMC NAND controller/Flash is represented as a child of the
GPMC controller node.
properties:
compatible:
items:
- enum:
- ti,am64-nand
- ti,omap2-nand
reg:
maxItems: 1
interrupts:
items:
- description: Interrupt for fifoevent
- description: Interrupt for termcount
"#address-cells": true
"#size-cells": true
ti,nand-ecc-opt:
description: Desired ECC algorithm
$ref: /schemas/types.yaml#/definitions/string
enum: [sw, ham1, bch4, bch8, bch16]
ti,nand-xfer-type:
description: Data transfer method between controller and chip.
$ref: /schemas/types.yaml#/definitions/string
enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq]
default: prefetch-polled
ti,elm-id:
description:
phandle to the ELM (Error Location Module).
$ref: /schemas/types.yaml#/definitions/phandle
nand-bus-width:
description:
Bus width to the NAND chip
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16]
default: 8
rb-gpios:
description:
GPIO connection to R/B signal from NAND chip
maxItems: 1
allOf:
- $ref: /schemas/memory-controllers/ti,gpmc-child.yaml
- $ref: mtd.yaml#
required:
- compatible
- reg
- ti,nand-ecc-opt
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
gpmc: memory-controller@50000000 {
compatible = "ti,am3352-gpmc";
dmas = <&edma 52 0>;
dma-names = "rxtx";
clocks = <&l3s_gclk>;
clock-names = "fck";
reg = <0x50000000 0x2000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
#address-cells = <1>;
#size-cells = <1>;
/* NAND generic properties */
nand-bus-width = <8>;
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
/* GPMC properties*/
gpmc,device-width = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x00040000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00040000 0x00040000>;
};
};
};
