# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2021 Arm Ltd.
%YAML 1.2
---
$id:
http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
$schema:
http://devicetree.org/meta-schemas/core.yaml#
title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
maintainers:
- Suzuki K Poulose <suzuki.poulose@arm.com>
- Robin Murphy <robin.murphy@arm.com>
description:
ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
L3 memory system, control logic and external interfaces to form a multicore
cluster. The PMU enables gathering various statistics on the operation of the
DSU. The PMU provides independent 32-bit counters that can count any of the
supported events, along with a 64-bit cycle counter. The PMU is accessed via
CPU system registers and has no MMIO component.
properties:
compatible:
oneOf:
- const: arm,dsu-pmu
- items:
- const: arm,dsu-110-pmu
- const: arm,dsu-pmu
interrupts:
items:
- description: nCLUSTERPMUIRQ interrupt
cpus:
minItems: 1
maxItems: 12
description: List of phandles for the CPUs connected to this DSU instance.
required:
- compatible
- interrupts
- cpus
additionalProperties: false
