base = md->virt_addr;
size = md->num_pages << EFI_PAGE_SHIFT;
/* * We can only use apply_to_page_range() if we can guarantee that the * entire region was mapped using pages. This should be the case if the * region does not cover any naturally aligned SECTION_SIZE sized * blocks.
*/ if (round_down(base + size, SECTION_SIZE) <
round_up(base, SECTION_SIZE) + SECTION_SIZE) return apply_to_page_range(mm, base, size, set_permissions, md);
/* * Order is important here: memory regions may have all of the * bits below set (and usually do), so we check them in order of * preference.
*/ if (md->attribute & EFI_MEMORY_WB)
desc.type = MT_MEMORY_RWX; elseif (md->attribute & EFI_MEMORY_WT)
desc.type = MT_MEMORY_RWX_NONCACHED; elseif (md->attribute & EFI_MEMORY_WC)
desc.type = MT_DEVICE_WC; else
desc.type = MT_DEVICE;
create_mapping_late(mm, &desc, true);
/* * If stricter permissions were specified, apply them now.
*/ if (md->attribute & (EFI_MEMORY_RO | EFI_MEMORY_XP)) return efi_set_mapping_permissions(mm, md, false); return 0;
}
state = early_memremap_ro(cpu_state_table, sizeof(struct efi_arm_entry_state)); if (state == NULL) {
pr_warn("Unable to map CPU entry state table.\n"); return;
}
if ((state->sctlr_before_ebs & 1) == 0)
pr_warn(FW_BUG "EFI stub was entered with MMU and Dcache disabled, please fix your firmware!\n"); elseif ((state->sctlr_after_ebs & 1) == 0)
pr_warn(FW_BUG "ExitBootServices() returned with MMU and Dcache disabled, please fix your firmware!\n"); else
dump_state = false;
if (dump_state || efi_enabled(EFI_DBG)) {
pr_info("CPSR at EFI stub entry : 0x%08x\n",
state->cpsr_before_ebs);
pr_info("SCTLR at EFI stub entry : 0x%08x\n",
state->sctlr_before_ebs);
pr_info("CPSR after ExitBootServices() : 0x%08x\n",
state->cpsr_after_ebs);
pr_info("SCTLR after ExitBootServices(): 0x%08x\n",
state->sctlr_after_ebs);
}
early_memunmap(state, sizeof(struct efi_arm_entry_state));
}
}
void __init arm_efi_init(void)
{
efi_init();
/* ARM does not permit early mappings to persist across paging_init() */
efi_memmap_unmap();
load_cpu_state_table();
}
Messung V0.5
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