Quelle  imx8qm-ss-dma.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 * Dong Aisheng <aisheng.dong@nxp.com>
 */

/delete-node/ &adma_pwm;
/delete-node/ &adma_pwm_lpcg;

&dma_subsys {
 uart4_lpcg: clock-controller@5a4a0000 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5a4a0000 0x10000>;
  #clock-cells = <1>;
  clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
    <&dma_ipg_clk>;
  clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
  clock-output-names = "uart4_lpcg_baud_clk",
         "uart4_lpcg_ipg_clk";
  power-domains = <&pd IMX_SC_R_UART_4>;
 };

 i2c4: i2c@5a840000 {
  compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
  reg = <0x5a840000 0x4000>;
  interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
  interrupt-parent = <&gic>;
  clocks = <&i2c4_lpcg 0>,
    <&i2c4_lpcg 1>;
  clock-names = "per", "ipg";
  assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>;
  assigned-clock-rates = <24000000>;
  power-domains = <&pd IMX_SC_R_I2C_4>;
  status = "disabled";
 };

 i2c4_lpcg: clock-controller@5ac40000 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5ac40000 0x10000>;
  #clock-cells = <1>;
  clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>,
    <&dma_ipg_clk>;
  clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
  clock-output-names = "i2c4_lpcg_clk",
         "i2c4_lpcg_ipg_clk";
  power-domains = <&pd IMX_SC_R_I2C_4>;
 };

 can1_lpcg: clock-controller@5ace0000 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5ace0000 0x10000>;
  #clock-cells = <1>;
  clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>,
    <&dma_ipg_clk>, <&dma_ipg_clk>;
  clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
  clock-output-names = "can1_lpcg_pe_clk",
         "can1_lpcg_ipg_clk",
         "can1_lpcg_chi_clk";
  power-domains = <&pd IMX_SC_R_CAN_1>;
 };

 can2_lpcg: clock-controller@5acf0000 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5acf0000 0x10000>;
  #clock-cells = <1>;
  clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>,
    <&dma_ipg_clk>, <&dma_ipg_clk>;
  clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
  clock-output-names = "can2_lpcg_pe_clk",
         "can2_lpcg_ipg_clk",
         "can2_lpcg_chi_clk";
  power-domains = <&pd IMX_SC_R_CAN_2>;
 };
};

&edma2 {
 reg = <0x5a1f0000 0x170000>;
 #dma-cells = <3>;
 dma-channels = <22>;
 dma-channel-mask = <0xf00>;
 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
       <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
       <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
       <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
       <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
 power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
   <&pd IMX_SC_R_DMA_0_CH1>,
   <&pd IMX_SC_R_DMA_0_CH2>,
   <&pd IMX_SC_R_DMA_0_CH3>,
   <&pd IMX_SC_R_DMA_0_CH4>,
   <&pd IMX_SC_R_DMA_0_CH5>,
   <&pd IMX_SC_R_DMA_0_CH6>,
   <&pd IMX_SC_R_DMA_0_CH7>,
   <&pd IMX_SC_R_DMA_0_CH8>,
   <&pd IMX_SC_R_DMA_0_CH9>,
   <&pd IMX_SC_R_DMA_0_CH10>,
   <&pd IMX_SC_R_DMA_0_CH11>,
   <&pd IMX_SC_R_DMA_0_CH12>,
   <&pd IMX_SC_R_DMA_0_CH13>,
   <&pd IMX_SC_R_DMA_0_CH14>,
   <&pd IMX_SC_R_DMA_0_CH15>,
   <&pd IMX_SC_R_DMA_0_CH16>,
   <&pd IMX_SC_R_DMA_0_CH17>,
   <&pd IMX_SC_R_DMA_0_CH18>,
   <&pd IMX_SC_R_DMA_0_CH19>,
   <&pd IMX_SC_R_DMA_0_CH20>,
   <&pd IMX_SC_R_DMA_0_CH21>;
 status = "okay";
};

/* It is eDMA1 in 8QM RM, but 8QXP it is eDMA3 */
&edma3 {
 reg = <0x5a9f0000 0x210000>;
 dma-channels = <10>;
 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
       <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
 power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
   <&pd IMX_SC_R_DMA_1_CH1>,
   <&pd IMX_SC_R_DMA_1_CH2>,
   <&pd IMX_SC_R_DMA_1_CH3>,
   <&pd IMX_SC_R_DMA_1_CH4>,
   <&pd IMX_SC_R_DMA_1_CH5>,
   <&pd IMX_SC_R_DMA_1_CH6>,
   <&pd IMX_SC_R_DMA_1_CH7>,
   <&pd IMX_SC_R_DMA_1_CH8>,
   <&pd IMX_SC_R_DMA_1_CH9>;
};

&flexcan1 {
 fsl,clk-source = /bits/ 8 <1>;
};

&flexcan2 {
 clocks = <&can1_lpcg IMX_LPCG_CLK_4>,
   <&can1_lpcg IMX_LPCG_CLK_0>;
 assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>;
 fsl,clk-source = /bits/ 8 <1>;
};

&flexcan3 {
 clocks = <&can2_lpcg IMX_LPCG_CLK_4>,
   <&can2_lpcg IMX_LPCG_CLK_0>;
 assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>;
 fsl,clk-source = /bits/ 8 <1>;
};

&lpuart0 {
 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
 dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
 dma-names = "rx","tx";
};

&lpuart1 {
 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
 dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
 dma-names = "rx","tx";
};

&lpuart2 {
 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
 dmas = <&edma2 17 0 0>, <&edma2 16 0 1>;
 dma-names = "rx","tx";
};

&lpuart3 {
 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
 dmas = <&edma2 19 0 0>, <&edma2 18 0 1>;
 dma-names = "rx","tx";
};

&i2c0 {
 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};

&i2c1 {
 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};

&i2c2 {
 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};

&i2c3 {
 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};