Spracherkennung für: .dtsi vermutete Sprache: Unknown {[0] [0] [0]} [Methode: Schwerpunktbildung, einfache Gewichte, sechs Dimensionen]
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Markus Niebel
*/
#include "imx93.dtsi"
/{
model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM";
compatible = "tq,imx93-tqma9352", "fsl,imx93";
memory@80000000 {
device_type = "memory";
/* our minimum RAM config will be 1024 MiB */
reg = <0x00000000 0x80000000 0 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0 0x80000000 0 0x40000000>;
size = <0 0x10000000>;
linux,cma-default;
};
};
/* SD2 RST# via PMIC SW_EN */
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&buck4>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&adc1 {
vref-supply = <&buck5>;
};
&flexspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi1>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
/*
* no DQS, RXCLKSRC internal loop back, max 66 MHz
* clk framework uses CLK_DIVIDER_ROUND_CLOSEST
* selected value together with root from
* IMX93_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to
* respect the maximum value.
*/
spi-max-frequency = <62000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1>;
status = "okay";
se97_som: temperature-sensor@1b {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1b>;
};
pca9451a: pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9451>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
regulators {
/* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
/* V_DDRQ - 0.6 V for LPDDR4X */
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <600000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
/* V_3V3 - EEPROM, RTC, ... */
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* V_1V8 - SPI NOR, eMMC, RAM VDD1... */
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* V_1V1 - RAM VDD2*/
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
/* V_1V8_BBSM, fix 1.8 */
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* V_0V8_ANA */
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
/* V_SD2 - 3.3/1.8V USDHC2 io Voltage */
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
pcf85063: rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
quartz-load-femtofarads = <7000>;
};
eeprom0: eeprom@53 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
read-only;
vcc-supply = <&buck4>;
};
eeprom1: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
vcc-supply = <&buck4>;
};
/* protectable identification memory (part of M24C64-D @57) */
eeprom@5f {
compatible = "atmel,24c64d-wl";
reg = <0x5f>;
vcc-supply = <&buck4>;
};
imu@6a {
compatible = "st,ism330dhcx";
reg = <0x6a>;
vdd-supply = <&buck4>;
vddio-supply = <&buck4>;
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
vmmc-supply = <&buck4>;
vqmmc-supply = <&buck5>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&wdog3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_flexspi1: flexspi1grp {
fsl,pins = <
/* FSEL 3 | DSE X6 */
MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x01fe
MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x01fe
/* HYS | PU | FSEL 3 | DSE X6 */
MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x13fe
MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x13fe
/* HYS | FSEL 3 | DSE X6 (external PU) */
MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x11fe
MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x11fe
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
/* SION | OD | FSEL 3 | DSE X4 */
MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x4000199e
MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x4000199e
>;
};
pinctrl_pca9451: pca9451grp {
fsl,pins = <
/* HYS | PU */
MX93_PAD_I2C2_SDA__GPIO1_IO03 0x1200
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
/* FSEL 2 | DSE X2 */
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x106
>;
};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
/* PD | FSEL 3 | DSE X5 */
MX93_PAD_SD1_CLK__USDHC1_CLK 0x5be
/* HYS | FSEL 0 | no drive */
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1000
/* HYS | FSEL 3 | X5 */
MX93_PAD_SD1_CMD__USDHC1_CMD 0x400011be
/* HYS | FSEL 3 | X4 */
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
/* PU | FSEL 1 | DSE X4 */
MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
>;
};
};
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